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b/FPGA1212_QLSOFA_HD_PNR/fpga_top/fpga_top_icv_in_design.fm.v index 16f7f8b..84c3355 100644 --- a/FPGA1212_QLSOFA_HD_PNR/fpga_top/fpga_top_icv_in_design.fm.v +++ b/FPGA1212_QLSOFA_HD_PNR/fpga_top/fpga_top_icv_in_design.fm.v @@ -12,19 +12,17 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:0] mem_out ; -wire copt_net_103 ; +wire copt_net_102 ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( copt_net_103 ) ) ; -sky130_fd_sc_hd__buf_8 FTB_18__17 ( .A ( mem_out[0] ) , .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__buf_1 ropt_h_inst_1347 ( .A ( ropt_net_114 ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( copt_net_102 ) ) ; +sky130_fd_sc_hd__buf_1 FTB_18__17 ( .A ( mem_out[0] ) , .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1338 ( .A ( copt_net_105 ) , .X ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1338 ( .A ( copt_net_106 ) , - .X ( copt_net_104 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1340 ( .A ( copt_net_103 ) , - .X ( copt_net_106 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1341 ( .A ( copt_net_104 ) , - .X ( ropt_net_114 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1339 ( .A ( copt_net_107 ) , + .X ( copt_net_105 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1341 ( .A ( copt_net_102 ) , + .X ( copt_net_107 ) ) ; endmodule @@ -291,6 +289,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; cby_2__1__const1 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -320,8 +320,6 @@ sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_89 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , - .X ( out[0] ) ) ; endmodule @@ -907,7 +905,7 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_113 ) , +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_110 ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; @@ -916,23 +914,25 @@ sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1330 ( .A ( ccff_head[0] ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1329 ( .A ( ccff_head[0] ) , + .X ( copt_net_95 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1330 ( .A ( ropt_net_113 ) , .X ( copt_net_96 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1331 ( .A ( copt_net_96 ) , +sky130_fd_sc_hd__dlygate4sd2_1 copt_h_inst_1331 ( .A ( copt_net_99 ) , .X ( copt_net_97 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1332 ( .A ( copt_net_97 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1332 ( .A ( ropt_net_111 ) , .X ( copt_net_98 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1333 ( .A ( copt_net_98 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1333 ( .A ( copt_net_96 ) , .X ( copt_net_99 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1334 ( .A ( copt_net_99 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1334 ( .A ( copt_net_97 ) , .X ( copt_net_100 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 copt_h_inst_1335 ( .A ( copt_net_100 ) , - .X ( copt_net_101 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1344 ( .A ( copt_net_101 ) , +sky130_fd_sc_hd__buf_1 ropt_h_inst_1343 ( .A ( copt_net_98 ) , + .X ( ropt_net_110 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1344 ( .A ( ropt_net_112 ) , .X ( ropt_net_111 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 ropt_h_inst_1345 ( .A ( ropt_net_111 ) , +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1345 ( .A ( copt_net_100 ) , .X ( ropt_net_112 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1346 ( .A ( ropt_net_112 ) , +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1346 ( .A ( copt_net_95 ) , .X ( ropt_net_113 ) ) ; endmodule @@ -1636,7 +1636,7 @@ cby_2__1__mux_tree_tapbuf_size12_0 mux_left_ipin_0 ( .sram ( mux_tree_tapbuf_size12_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , - .out ( right_grid_pin_0_ ) , .p0 ( optlc_net_91 ) ) ; + .out ( right_grid_pin_0_ ) , .p0 ( optlc_net_90 ) ) ; cby_2__1__mux_tree_tapbuf_size12_1 mux_right_ipin_0 ( .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[4] , chany_bottom_out[4] , chany_top_out[7] , chany_bottom_out[7] , @@ -1645,7 +1645,7 @@ cby_2__1__mux_tree_tapbuf_size12_1 mux_right_ipin_0 ( .sram ( mux_tree_tapbuf_size12_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) , - .out ( left_grid_pin_16_ ) , .p0 ( optlc_net_92 ) ) ; + .out ( left_grid_pin_16_ ) , .p0 ( optlc_net_91 ) ) ; cby_2__1__mux_tree_tapbuf_size12_2 mux_right_ipin_2 ( .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[3] , chany_bottom_out[3] , chany_top_out[9] , chany_bottom_out[9] , @@ -1654,7 +1654,7 @@ cby_2__1__mux_tree_tapbuf_size12_2 mux_right_ipin_2 ( .sram ( mux_tree_tapbuf_size12_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , - .out ( left_grid_pin_18_ ) , .p0 ( optlc_net_93 ) ) ; + .out ( left_grid_pin_18_ ) , .p0 ( optlc_net_92 ) ) ; cby_2__1__mux_tree_tapbuf_size12_3 mux_right_ipin_4 ( .in ( { chany_top_out[2] , chany_bottom_out[2] , chany_top_out[5] , chany_bottom_out[5] , chany_top_out[11] , chany_bottom_out[11] , @@ -1663,7 +1663,7 @@ cby_2__1__mux_tree_tapbuf_size12_3 mux_right_ipin_4 ( .sram ( mux_tree_tapbuf_size12_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) , - .out ( left_grid_pin_20_ ) , .p0 ( optlc_net_90 ) ) ; + .out ( left_grid_pin_20_ ) , .p0 ( optlc_net_89 ) ) ; cby_2__1__mux_tree_tapbuf_size12_4 mux_right_ipin_6 ( .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[4] , chany_bottom_out[4] , chany_top_out[7] , chany_bottom_out[7] , @@ -1672,7 +1672,7 @@ cby_2__1__mux_tree_tapbuf_size12_4 mux_right_ipin_6 ( .sram ( mux_tree_tapbuf_size12_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 , SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) , - .out ( left_grid_pin_22_ ) , .p0 ( optlc_net_92 ) ) ; + .out ( left_grid_pin_22_ ) , .p0 ( optlc_net_91 ) ) ; cby_2__1__mux_tree_tapbuf_size12_5 mux_right_ipin_8 ( .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[3] , chany_bottom_out[3] , chany_top_out[9] , chany_bottom_out[9] , @@ -1681,7 +1681,7 @@ cby_2__1__mux_tree_tapbuf_size12_5 mux_right_ipin_8 ( .sram ( mux_tree_tapbuf_size12_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 , SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) , - .out ( left_grid_pin_24_ ) , .p0 ( optlc_net_93 ) ) ; + .out ( left_grid_pin_24_ ) , .p0 ( optlc_net_92 ) ) ; cby_2__1__mux_tree_tapbuf_size12_6 mux_right_ipin_10 ( .in ( { chany_top_out[2] , chany_bottom_out[2] , chany_top_out[5] , chany_bottom_out[5] , chany_top_out[11] , chany_bottom_out[11] , @@ -1690,7 +1690,7 @@ cby_2__1__mux_tree_tapbuf_size12_6 mux_right_ipin_10 ( .sram ( mux_tree_tapbuf_size12_6_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) , - .out ( left_grid_pin_26_ ) , .p0 ( optlc_net_90 ) ) ; + .out ( left_grid_pin_26_ ) , .p0 ( optlc_net_89 ) ) ; cby_2__1__mux_tree_tapbuf_size12_7 mux_right_ipin_12 ( .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[4] , chany_bottom_out[4] , chany_top_out[7] , chany_bottom_out[7] , @@ -1699,7 +1699,7 @@ cby_2__1__mux_tree_tapbuf_size12_7 mux_right_ipin_12 ( .sram ( mux_tree_tapbuf_size12_7_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 , SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) , - .out ( left_grid_pin_28_ ) , .p0 ( optlc_net_93 ) ) ; + .out ( left_grid_pin_28_ ) , .p0 ( optlc_net_92 ) ) ; cby_2__1__mux_tree_tapbuf_size12 mux_right_ipin_14 ( .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[3] , chany_bottom_out[3] , chany_top_out[9] , chany_bottom_out[9] , @@ -1708,7 +1708,7 @@ cby_2__1__mux_tree_tapbuf_size12 mux_right_ipin_14 ( .sram ( mux_tree_tapbuf_size12_8_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 , SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) , - .out ( left_grid_pin_30_ ) , .p0 ( optlc_net_93 ) ) ; + .out ( left_grid_pin_30_ ) , .p0 ( optlc_net_92 ) ) ; cby_2__1__mux_tree_tapbuf_size12_mem_0 mem_left_ipin_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size12_mem_0_ccff_tail ) , @@ -1761,7 +1761,7 @@ cby_2__1__mux_tree_tapbuf_size10_0 mux_right_ipin_1 ( .sram ( mux_tree_tapbuf_size10_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 , SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) , - .out ( left_grid_pin_17_ ) , .p0 ( optlc_net_91 ) ) ; + .out ( left_grid_pin_17_ ) , .p0 ( optlc_net_90 ) ) ; cby_2__1__mux_tree_tapbuf_size10_1 mux_right_ipin_3 ( .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[4] , chany_bottom_out[4] , chany_top_out[10] , chany_bottom_out[10] , @@ -1770,7 +1770,7 @@ cby_2__1__mux_tree_tapbuf_size10_1 mux_right_ipin_3 ( .sram ( mux_tree_tapbuf_size10_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 , SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) , - .out ( left_grid_pin_19_ ) , .p0 ( optlc_net_91 ) ) ; + .out ( left_grid_pin_19_ ) , .p0 ( optlc_net_90 ) ) ; cby_2__1__mux_tree_tapbuf_size10_2 mux_right_ipin_5 ( .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[3] , chany_bottom_out[3] , chany_top_out[6] , chany_bottom_out[6] , @@ -1779,7 +1779,7 @@ cby_2__1__mux_tree_tapbuf_size10_2 mux_right_ipin_5 ( .sram ( mux_tree_tapbuf_size10_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 , SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) , - .out ( left_grid_pin_21_ ) , .p0 ( optlc_net_92 ) ) ; + .out ( left_grid_pin_21_ ) , .p0 ( optlc_net_91 ) ) ; cby_2__1__mux_tree_tapbuf_size10_3 mux_right_ipin_7 ( .in ( { chany_top_out[2] , chany_bottom_out[2] , chany_top_out[5] , chany_bottom_out[5] , chany_top_out[8] , chany_bottom_out[8] , @@ -1788,7 +1788,7 @@ cby_2__1__mux_tree_tapbuf_size10_3 mux_right_ipin_7 ( .sram ( mux_tree_tapbuf_size10_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 , SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) , - .out ( left_grid_pin_23_ ) , .p0 ( optlc_net_92 ) ) ; + .out ( left_grid_pin_23_ ) , .p0 ( optlc_net_91 ) ) ; cby_2__1__mux_tree_tapbuf_size10_4 mux_right_ipin_9 ( .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[4] , chany_bottom_out[4] , chany_top_out[10] , chany_bottom_out[10] , @@ -1797,7 +1797,7 @@ cby_2__1__mux_tree_tapbuf_size10_4 mux_right_ipin_9 ( .sram ( mux_tree_tapbuf_size10_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 , SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) , - .out ( left_grid_pin_25_ ) , .p0 ( optlc_net_92 ) ) ; + .out ( left_grid_pin_25_ ) , .p0 ( optlc_net_91 ) ) ; cby_2__1__mux_tree_tapbuf_size10_5 mux_right_ipin_11 ( .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[3] , chany_bottom_out[3] , chany_top_out[12] , chany_bottom_out[12] , @@ -1806,7 +1806,7 @@ cby_2__1__mux_tree_tapbuf_size10_5 mux_right_ipin_11 ( .sram ( mux_tree_tapbuf_size10_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 , SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) , - .out ( left_grid_pin_27_ ) , .p0 ( optlc_net_92 ) ) ; + .out ( left_grid_pin_27_ ) , .p0 ( optlc_net_91 ) ) ; cby_2__1__mux_tree_tapbuf_size10_6 mux_right_ipin_13 ( .in ( { chany_top_out[2] , chany_bottom_out[2] , chany_top_out[5] , chany_bottom_out[5] , chany_top_out[14] , chany_bottom_out[14] , @@ -1815,7 +1815,7 @@ cby_2__1__mux_tree_tapbuf_size10_6 mux_right_ipin_13 ( .sram ( mux_tree_tapbuf_size10_6_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 , SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) , - .out ( left_grid_pin_29_ ) , .p0 ( optlc_net_91 ) ) ; + .out ( left_grid_pin_29_ ) , .p0 ( optlc_net_90 ) ) ; cby_2__1__mux_tree_tapbuf_size10 mux_right_ipin_15 ( .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[4] , chany_bottom_out[4] , chany_top_out[7] , chany_bottom_out[7] , @@ -1824,7 +1824,7 @@ cby_2__1__mux_tree_tapbuf_size10 mux_right_ipin_15 ( .sram ( mux_tree_tapbuf_size10_7_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 , SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 } ) , - .out ( left_grid_pin_31_ ) , .p0 ( optlc_net_93 ) ) ; + .out ( left_grid_pin_31_ ) , .p0 ( optlc_net_92 ) ) ; cby_2__1__mux_tree_tapbuf_size10_mem_0 mem_right_ipin_1 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size12_mem_1_ccff_tail ) , @@ -1872,15 +1872,15 @@ cby_2__1__logical_tile_io_mode_io_ logical_tile_io_mode_io__0 ( .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) , .io_outpad ( left_width_0_height_0__pin_0_ ) , .ccff_head ( { ccff_tail_mid } ) , - .io_inpad ( left_width_0_height_0__pin_1_lower ) , - .ccff_tail ( ccff_tail ) ) ; + .io_inpad ( left_width_0_height_0__pin_1_lower ) , + .ccff_tail ( { ropt_net_108 } ) ) ; sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_S_in ) , .X ( pReset[0] ) ) ; sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_W_in ) , .X ( prog_clk[0] ) ) ; sky130_fd_sc_hd__clkbuf_1 prog_clk_0_S_FTB01 ( .A ( prog_clk_0_W_in ) , - .X ( ctsbuf_net_194 ) ) ; + .X ( ctsbuf_net_193 ) ) ; sky130_fd_sc_hd__clkbuf_1 prog_clk_0_N_FTB01 ( .A ( prog_clk_0_W_in ) , - .X ( ctsbuf_net_295 ) ) ; + .X ( ctsbuf_net_294 ) ) ; sky130_fd_sc_hd__buf_8 FTB_19__18 ( .A ( chany_bottom_in[0] ) , .X ( chany_top_out[0] ) ) ; sky130_fd_sc_hd__buf_8 FTB_20__19 ( .A ( chany_bottom_in[1] ) , @@ -2004,17 +2004,19 @@ sky130_fd_sc_hd__buf_8 FTB_78__77 ( .A ( chany_top_in[29] ) , sky130_fd_sc_hd__buf_6 FTB_79__78 ( .A ( left_width_0_height_0__pin_1_lower[0] ) , .X ( left_width_0_height_0__pin_1_upper[0] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_92 ( .LO ( SYNOPSYS_UNCONNECTED_69 ) , +sky130_fd_sc_hd__conb_1 optlc_91 ( .LO ( SYNOPSYS_UNCONNECTED_69 ) , + .HI ( optlc_net_89 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_93 ( .LO ( SYNOPSYS_UNCONNECTED_70 ) , .HI ( optlc_net_90 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_94 ( .LO ( SYNOPSYS_UNCONNECTED_70 ) , +sky130_fd_sc_hd__conb_1 optlc_95 ( .LO ( SYNOPSYS_UNCONNECTED_71 ) , .HI ( optlc_net_91 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_96 ( .LO ( SYNOPSYS_UNCONNECTED_71 ) , +sky130_fd_sc_hd__conb_1 optlc_97 ( .LO ( SYNOPSYS_UNCONNECTED_72 ) , .HI ( optlc_net_92 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_98 ( .LO ( SYNOPSYS_UNCONNECTED_72 ) , - .HI ( optlc_net_93 ) ) ; -sky130_fd_sc_hd__buf_6 cts_buf_3591232 ( .A ( ctsbuf_net_194 ) , +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1342 ( .A ( ropt_net_108 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__buf_6 cts_buf_3591231 ( .A ( ctsbuf_net_193 ) , .X ( prog_clk_0_S_out ) ) ; -sky130_fd_sc_hd__buf_6 cts_buf_3641237 ( .A ( ctsbuf_net_295 ) , +sky130_fd_sc_hd__clkbuf_8 cts_buf_3641236 ( .A ( ctsbuf_net_294 ) , .X ( prog_clk_0_N_out ) ) ; endmodule @@ -2027,6 +2029,8 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; +wire copt_net_115 ; + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , @@ -2034,14 +2038,14 @@ sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( copt_net_115 ) ) ; sky130_fd_sc_hd__buf_6 FTB_16__15 ( .A ( copt_net_118 ) , .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1352 ( .A ( mem_out[3] ) , - .X ( copt_net_115 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1352 ( .A ( copt_net_115 ) , + .X ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1355 ( .A ( copt_net_120 ) , .X ( copt_net_118 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1356 ( .A ( copt_net_115 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1356 ( .A ( mem_out[3] ) , .X ( copt_net_119 ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1357 ( .A ( copt_net_119 ) , .X ( copt_net_120 ) ) ; @@ -2809,7 +2813,7 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_130 ) , +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_129 ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; @@ -2830,10 +2834,12 @@ sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1359 ( .A ( copt_net_117 ) , .X ( copt_net_122 ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1360 ( .A ( copt_net_122 ) , .X ( copt_net_123 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1367 ( .A ( ropt_net_131 ) , +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1365 ( .A ( copt_net_123 ) , + .X ( ropt_net_128 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 ropt_h_inst_1366 ( .A ( ropt_net_130 ) , + .X ( ropt_net_129 ) ) ; +sky130_fd_sc_hd__buf_1 ropt_h_inst_1367 ( .A ( ropt_net_128 ) , .X ( ropt_net_130 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 ropt_h_inst_1368 ( .A ( copt_net_123 ) , - .X ( ropt_net_131 ) ) ; endmodule @@ -3758,7 +3764,7 @@ sky130_fd_sc_hd__buf_8 FTB_19__18 ( .A ( chany_bottom_in[2] ) , .X ( chany_top_out[2] ) ) ; sky130_fd_sc_hd__buf_8 FTB_20__19 ( .A ( chany_bottom_in[3] ) , .X ( chany_top_out[3] ) ) ; -sky130_fd_sc_hd__buf_12 FTB_21__20 ( .A ( chany_bottom_in[4] ) , +sky130_fd_sc_hd__buf_8 FTB_21__20 ( .A ( chany_bottom_in[4] ) , .X ( chany_top_out[4] ) ) ; sky130_fd_sc_hd__buf_8 FTB_22__21 ( .A ( chany_bottom_in[5] ) , .X ( chany_top_out[5] ) ) ; @@ -3916,23 +3922,23 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:0] mem_out ; -wire copt_net_78 ; +wire copt_net_74 ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( copt_net_78 ) ) ; + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( copt_net_74 ) ) ; sky130_fd_sc_hd__buf_6 FTB_2__1 ( .A ( mem_out[0] ) , .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1217 ( .A ( copt_net_78 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1217 ( .A ( copt_net_75 ) , .X ( copt_net_73 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1218 ( .A ( copt_net_73 ) , - .X ( copt_net_74 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1218 ( .A ( copt_net_78 ) , + .X ( mem_out[0] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1219 ( .A ( copt_net_74 ) , .X ( copt_net_75 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1220 ( .A ( copt_net_75 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1220 ( .A ( copt_net_73 ) , .X ( copt_net_76 ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1221 ( .A ( copt_net_76 ) , .X ( copt_net_77 ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1222 ( .A ( copt_net_77 ) , - .X ( mem_out[0] ) ) ; + .X ( copt_net_78 ) ) ; endmodule @@ -4023,7 +4029,7 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( copt_net_72 ) , +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( copt_net_71 ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; @@ -4040,9 +4046,9 @@ sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1213 ( .A ( copt_net_68 ) , .X ( copt_net_69 ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1214 ( .A ( copt_net_69 ) , .X ( copt_net_70 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1215 ( .A ( copt_net_70 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1215 ( .A ( copt_net_72 ) , .X ( copt_net_71 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1216 ( .A ( copt_net_71 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1216 ( .A ( copt_net_70 ) , .X ( copt_net_72 ) ) ; endmodule @@ -4138,20 +4144,20 @@ output [0:0] right_width_0_height_0__pin_1_lower ; input pReset_N_in ; input prog_clk_0_E_in ; -wire ropt_net_134 ; -wire ropt_net_128 ; -wire ropt_net_129 ; -wire ropt_net_133 ; -wire ropt_net_127 ; -wire ropt_net_122 ; -wire ropt_net_124 ; -wire ropt_net_132 ; -wire ropt_net_123 ; wire ropt_net_120 ; -wire ropt_net_138 ; -wire ropt_net_125 ; -wire ropt_net_137 ; +wire ropt_net_118 ; +wire ropt_net_136 ; +wire ropt_net_117 ; wire ropt_net_121 ; +wire ropt_net_125 ; +wire ropt_net_124 ; +wire ropt_net_122 ; +wire ropt_net_115 ; +wire ropt_net_116 ; +wire ropt_net_126 ; +wire ropt_net_119 ; +wire ropt_net_123 ; +wire ropt_net_114 ; wire [0:0] prog_clk ; wire prog_clk_0 ; wire [0:3] mux_tree_tapbuf_size12_0_sram ; @@ -4186,21 +4192,21 @@ sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_E_in ) , sky130_fd_sc_hd__buf_8 FTB_3__2 ( .A ( chany_bottom_in[0] ) , .X ( chany_top_out[0] ) ) ; sky130_fd_sc_hd__buf_6 FTB_4__3 ( .A ( chany_bottom_in[1] ) , - .X ( ropt_net_134 ) ) ; -sky130_fd_sc_hd__buf_8 FTB_5__4 ( .A ( chany_bottom_in[2] ) , - .X ( chany_top_out[2] ) ) ; + .X ( chany_top_out[1] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_5__4 ( .A ( chany_bottom_in[2] ) , + .X ( ropt_net_120 ) ) ; sky130_fd_sc_hd__buf_8 FTB_6__5 ( .A ( chany_bottom_in[3] ) , .X ( chany_top_out[3] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_7__6 ( .A ( chany_bottom_in[4] ) , +sky130_fd_sc_hd__buf_6 FTB_7__6 ( .A ( chany_bottom_in[4] ) , .X ( chany_top_out[4] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_8__7 ( .A ( chany_bottom_in[5] ) , - .X ( chany_top_out[5] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_8__7 ( .A ( chany_bottom_in[5] ) , + .X ( ropt_net_118 ) ) ; sky130_fd_sc_hd__buf_8 FTB_9__8 ( .A ( chany_bottom_in[6] ) , .X ( chany_top_out[6] ) ) ; sky130_fd_sc_hd__buf_8 FTB_10__9 ( .A ( chany_bottom_in[7] ) , .X ( chany_top_out[7] ) ) ; sky130_fd_sc_hd__buf_6 FTB_11__10 ( .A ( chany_bottom_in[8] ) , - .X ( ropt_net_128 ) ) ; + .X ( ropt_net_136 ) ) ; sky130_fd_sc_hd__buf_8 FTB_12__11 ( .A ( chany_bottom_in[9] ) , .X ( chany_top_out[9] ) ) ; sky130_fd_sc_hd__buf_8 FTB_13__12 ( .A ( chany_bottom_in[10] ) , @@ -4209,50 +4215,50 @@ sky130_fd_sc_hd__buf_6 FTB_14__13 ( .A ( chany_bottom_in[11] ) , .X ( chany_top_out[11] ) ) ; sky130_fd_sc_hd__buf_8 FTB_15__14 ( .A ( chany_bottom_in[12] ) , .X ( chany_top_out[12] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_16__15 ( .A ( chany_bottom_in[13] ) , - .X ( chany_top_out[13] ) ) ; -sky130_fd_sc_hd__buf_6 FTB_17__16 ( .A ( chany_bottom_in[14] ) , - .X ( ropt_net_129 ) ) ; +sky130_fd_sc_hd__buf_6 FTB_16__15 ( .A ( chany_bottom_in[13] ) , + .X ( ropt_net_117 ) ) ; +sky130_fd_sc_hd__buf_8 FTB_17__16 ( .A ( chany_bottom_in[14] ) , + .X ( chany_top_out[14] ) ) ; sky130_fd_sc_hd__buf_6 FTB_18__17 ( .A ( chany_bottom_in[15] ) , - .X ( ropt_net_133 ) ) ; -sky130_fd_sc_hd__buf_8 FTB_19__18 ( .A ( chany_bottom_in[16] ) , - .X ( chany_top_out[16] ) ) ; + .X ( ropt_net_121 ) ) ; +sky130_fd_sc_hd__buf_6 FTB_19__18 ( .A ( chany_bottom_in[16] ) , + .X ( ropt_net_125 ) ) ; sky130_fd_sc_hd__buf_6 FTB_20__19 ( .A ( chany_bottom_in[17] ) , .X ( chany_top_out[17] ) ) ; sky130_fd_sc_hd__buf_8 FTB_21__20 ( .A ( chany_bottom_in[18] ) , .X ( chany_top_out[18] ) ) ; sky130_fd_sc_hd__buf_6 FTB_22__21 ( .A ( chany_bottom_in[19] ) , - .X ( ropt_net_127 ) ) ; + .X ( chany_top_out[19] ) ) ; sky130_fd_sc_hd__buf_6 FTB_23__22 ( .A ( chany_bottom_in[20] ) , - .X ( chany_top_out[20] ) ) ; + .X ( ropt_net_124 ) ) ; sky130_fd_sc_hd__buf_8 FTB_24__23 ( .A ( chany_bottom_in[21] ) , .X ( chany_top_out[21] ) ) ; -sky130_fd_sc_hd__buf_6 FTB_25__24 ( .A ( chany_bottom_in[22] ) , - .X ( ropt_net_122 ) ) ; +sky130_fd_sc_hd__buf_8 FTB_25__24 ( .A ( chany_bottom_in[22] ) , + .X ( chany_top_out[22] ) ) ; sky130_fd_sc_hd__buf_6 FTB_26__25 ( .A ( chany_bottom_in[23] ) , - .X ( ropt_net_124 ) ) ; + .X ( ropt_net_122 ) ) ; sky130_fd_sc_hd__buf_8 FTB_27__26 ( .A ( chany_bottom_in[24] ) , .X ( chany_top_out[24] ) ) ; sky130_fd_sc_hd__buf_8 FTB_28__27 ( .A ( chany_bottom_in[25] ) , .X ( chany_top_out[25] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_29__28 ( .A ( chany_bottom_in[26] ) , +sky130_fd_sc_hd__buf_6 FTB_29__28 ( .A ( chany_bottom_in[26] ) , .X ( chany_top_out[26] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_30__29 ( .A ( chany_bottom_in[27] ) , - .X ( chany_top_out[27] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_30__29 ( .A ( chany_bottom_in[27] ) , + .X ( ropt_net_115 ) ) ; sky130_fd_sc_hd__buf_8 FTB_31__30 ( .A ( chany_bottom_in[28] ) , .X ( chany_top_out[28] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_32__31 ( .A ( chany_bottom_in[29] ) , +sky130_fd_sc_hd__buf_6 FTB_32__31 ( .A ( chany_bottom_in[29] ) , .X ( chany_top_out[29] ) ) ; sky130_fd_sc_hd__buf_8 FTB_33__32 ( .A ( chany_top_in[0] ) , .X ( chany_bottom_out[0] ) ) ; sky130_fd_sc_hd__buf_6 FTB_34__33 ( .A ( chany_top_in[1] ) , .X ( chany_bottom_out[1] ) ) ; -sky130_fd_sc_hd__buf_6 FTB_35__34 ( .A ( chany_top_in[2] ) , - .X ( ropt_net_132 ) ) ; +sky130_fd_sc_hd__buf_8 FTB_35__34 ( .A ( chany_top_in[2] ) , + .X ( chany_bottom_out[2] ) ) ; sky130_fd_sc_hd__buf_8 FTB_36__35 ( .A ( chany_top_in[3] ) , .X ( chany_bottom_out[3] ) ) ; -sky130_fd_sc_hd__buf_6 FTB_37__36 ( .A ( chany_top_in[4] ) , - .X ( ropt_net_123 ) ) ; +sky130_fd_sc_hd__buf_8 FTB_37__36 ( .A ( chany_top_in[4] ) , + .X ( chany_bottom_out[4] ) ) ; sky130_fd_sc_hd__buf_8 FTB_38__37 ( .A ( chany_top_in[5] ) , .X ( chany_bottom_out[5] ) ) ; sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chany_top_in[6] ) , @@ -4270,37 +4276,37 @@ sky130_fd_sc_hd__buf_6 FTB_44__43 ( .A ( chany_top_in[11] ) , sky130_fd_sc_hd__buf_8 FTB_45__44 ( .A ( chany_top_in[12] ) , .X ( chany_bottom_out[12] ) ) ; sky130_fd_sc_hd__buf_6 FTB_46__45 ( .A ( chany_top_in[13] ) , - .X ( ropt_net_120 ) ) ; + .X ( ropt_net_116 ) ) ; sky130_fd_sc_hd__buf_6 FTB_47__46 ( .A ( chany_top_in[14] ) , - .X ( ropt_net_138 ) ) ; + .X ( ropt_net_126 ) ) ; sky130_fd_sc_hd__buf_8 FTB_48__47 ( .A ( chany_top_in[15] ) , .X ( chany_bottom_out[15] ) ) ; sky130_fd_sc_hd__buf_8 FTB_49__48 ( .A ( chany_top_in[16] ) , .X ( chany_bottom_out[16] ) ) ; sky130_fd_sc_hd__buf_6 FTB_50__49 ( .A ( chany_top_in[17] ) , - .X ( ropt_net_125 ) ) ; + .X ( ropt_net_119 ) ) ; sky130_fd_sc_hd__buf_8 FTB_51__50 ( .A ( chany_top_in[18] ) , .X ( chany_bottom_out[18] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_52__51 ( .A ( chany_top_in[19] ) , +sky130_fd_sc_hd__buf_6 FTB_52__51 ( .A ( chany_top_in[19] ) , .X ( chany_bottom_out[19] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_53__52 ( .A ( chany_top_in[20] ) , - .X ( chany_bottom_out[20] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_53__52 ( .A ( chany_top_in[20] ) , + .X ( ropt_net_123 ) ) ; sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chany_top_in[21] ) , .X ( chany_bottom_out[21] ) ) ; sky130_fd_sc_hd__buf_6 FTB_55__54 ( .A ( chany_top_in[22] ) , - .X ( ropt_net_137 ) ) ; + .X ( chany_bottom_out[22] ) ) ; sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chany_top_in[23] ) , .X ( chany_bottom_out[23] ) ) ; sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chany_top_in[24] ) , .X ( chany_bottom_out[24] ) ) ; -sky130_fd_sc_hd__buf_6 FTB_58__57 ( .A ( chany_top_in[25] ) , +sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chany_top_in[25] ) , .X ( chany_bottom_out[25] ) ) ; sky130_fd_sc_hd__buf_6 FTB_59__58 ( .A ( chany_top_in[26] ) , .X ( chany_bottom_out[26] ) ) ; sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( chany_top_in[27] ) , .X ( chany_bottom_out[27] ) ) ; sky130_fd_sc_hd__buf_6 FTB_61__60 ( .A ( chany_top_in[28] ) , - .X ( ropt_net_121 ) ) ; + .X ( ropt_net_114 ) ) ; sky130_fd_sc_hd__buf_8 FTB_62__61 ( .A ( chany_top_in[29] ) , .X ( chany_bottom_out[29] ) ) ; sky130_fd_sc_hd__buf_6 FTB_63__62 ( @@ -4308,34 +4314,34 @@ sky130_fd_sc_hd__buf_6 FTB_63__62 ( .X ( right_width_0_height_0__pin_1_upper[0] ) ) ; sky130_fd_sc_hd__conb_1 optlc_67 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , .HI ( optlc_net_66 ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1263 ( .A ( ropt_net_120 ) , - .X ( chany_bottom_out[13] ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1264 ( .A ( ropt_net_121 ) , +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1258 ( .A ( ropt_net_114 ) , .X ( chany_bottom_out[28] ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1265 ( .A ( ropt_net_122 ) , - .X ( chany_top_out[22] ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1266 ( .A ( ropt_net_123 ) , - .X ( chany_bottom_out[4] ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1267 ( .A ( ropt_net_124 ) , - .X ( chany_top_out[23] ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1268 ( .A ( ropt_net_125 ) , +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1259 ( .A ( ropt_net_115 ) , + .X ( chany_top_out[27] ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1260 ( .A ( ropt_net_116 ) , + .X ( chany_bottom_out[13] ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1261 ( .A ( ropt_net_117 ) , + .X ( chany_top_out[13] ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1262 ( .A ( ropt_net_118 ) , + .X ( chany_top_out[5] ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1263 ( .A ( ropt_net_119 ) , .X ( chany_bottom_out[17] ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1270 ( .A ( ropt_net_127 ) , - .X ( chany_top_out[19] ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1271 ( .A ( ropt_net_128 ) , - .X ( chany_top_out[8] ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1272 ( .A ( ropt_net_129 ) , - .X ( chany_top_out[14] ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1275 ( .A ( ropt_net_132 ) , - .X ( chany_bottom_out[2] ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1276 ( .A ( ropt_net_133 ) , +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1264 ( .A ( ropt_net_120 ) , + .X ( chany_top_out[2] ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1265 ( .A ( ropt_net_121 ) , .X ( chany_top_out[15] ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1277 ( .A ( ropt_net_134 ) , - .X ( chany_top_out[1] ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1280 ( .A ( ropt_net_137 ) , - .X ( chany_bottom_out[22] ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1281 ( .A ( ropt_net_138 ) , +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1266 ( .A ( ropt_net_122 ) , + .X ( chany_top_out[23] ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1267 ( .A ( ropt_net_123 ) , + .X ( chany_bottom_out[20] ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1268 ( .A ( ropt_net_124 ) , + .X ( chany_top_out[20] ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1269 ( .A ( ropt_net_125 ) , + .X ( chany_top_out[16] ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1270 ( .A ( ropt_net_126 ) , .X ( chany_bottom_out[14] ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1280 ( .A ( ropt_net_136 ) , + .X ( chany_top_out[8] ) ) ; endmodule @@ -6621,7 +6627,7 @@ sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_87 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_88 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -6651,7 +6657,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; cbx_1__1__const1_13 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; @@ -6710,8 +6716,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; cbx_1__1__const1_12 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -6741,6 +6745,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_87 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .X ( out[0] ) ) ; endmodule @@ -6769,7 +6775,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; cbx_1__1__const1_11 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; @@ -6828,6 +6834,66 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; cbx_1__1__const1_10 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_85 ( .A ( BUF_net_86 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_86 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .Y ( BUF_net_86 ) ) ; +endmodule + + +module cbx_1__1__const1_9 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size10_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +cbx_1__1__const1_9 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , @@ -6862,65 +6928,6 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module cbx_1__1__const1_9 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module cbx_1__1__mux_tree_tapbuf_size10_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -cbx_1__1__const1_9 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_86 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , - .X ( out[0] ) ) ; -endmodule - - module cbx_1__1__const1_8 ( const1 ) ; output [0:0] const1 ; endmodule @@ -7128,7 +7135,7 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( copt_net_107 ) , +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( copt_net_101 ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; @@ -7137,22 +7144,16 @@ sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1326 ( .A ( copt_net_101 ) , - .X ( copt_net_100 ) ) ; -sky130_fd_sc_hd__buf_2 copt_h_inst_1327 ( .A ( ccff_head[0] ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1323 ( .A ( ccff_head[0] ) , + .X ( copt_net_95 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1324 ( .A ( copt_net_95 ) , + .X ( copt_net_96 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1325 ( .A ( copt_net_96 ) , + .X ( copt_net_97 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1326 ( .A ( copt_net_97 ) , + .X ( copt_net_98 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1329 ( .A ( copt_net_98 ) , .X ( copt_net_101 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1328 ( .A ( copt_net_100 ) , - .X ( copt_net_102 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 copt_h_inst_1329 ( .A ( copt_net_102 ) , - .X ( copt_net_103 ) ) ; -sky130_fd_sc_hd__buf_1 copt_h_inst_1333 ( .A ( copt_net_103 ) , - .X ( copt_net_104 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1334 ( .A ( copt_net_106 ) , - .X ( copt_net_105 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 copt_h_inst_1335 ( .A ( copt_net_104 ) , - .X ( copt_net_106 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1346 ( .A ( copt_net_105 ) , - .X ( copt_net_107 ) ) ; endmodule @@ -7218,9 +7219,9 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_84 ( .A ( BUF_net_85 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_85 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , - .Y ( BUF_net_85 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_83 ( .A ( BUF_net_84 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_84 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , + .Y ( BUF_net_84 ) ) ; endmodule @@ -7286,7 +7287,7 @@ sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_83 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_82 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -7318,7 +7319,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; cbx_1__1__const1_5 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; @@ -7420,7 +7421,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_82 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_81 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -7621,9 +7622,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_91 ( .A ( BUF_net_92 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_4 BINV_R_92 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , - .Y ( BUF_net_92 ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_80 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , + .X ( out[0] ) ) ; endmodule @@ -7654,7 +7654,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; cbx_1__1__const1_0 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; @@ -7774,11 +7774,6 @@ input clk_3_E_in ; output clk_3_E_out ; output clk_3_W_out ; -wire ropt_net_130 ; -wire ropt_net_121 ; -wire ropt_net_132 ; -wire ropt_net_124 ; -wire ropt_net_125 ; wire [0:0] prog_clk ; wire prog_clk_0 ; wire [0:3] mux_tree_tapbuf_size10_0_sram ; @@ -7830,7 +7825,7 @@ cbx_1__1__mux_tree_tapbuf_size12_0 mux_top_ipin_0 ( .sram ( mux_tree_tapbuf_size12_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , - .out ( bottom_grid_pin_0_ ) , .p0 ( optlc_net_96 ) ) ; + .out ( bottom_grid_pin_0_ ) , .p0 ( optlc_net_92 ) ) ; cbx_1__1__mux_tree_tapbuf_size12_1 mux_top_ipin_2 ( .in ( { chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[5] , chanx_left_out[5] , chanx_right_out[8] , chanx_left_out[8] , @@ -7839,7 +7834,7 @@ cbx_1__1__mux_tree_tapbuf_size12_1 mux_top_ipin_2 ( .sram ( mux_tree_tapbuf_size12_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) , - .out ( bottom_grid_pin_2_ ) , .p0 ( optlc_net_95 ) ) ; + .out ( bottom_grid_pin_2_ ) , .p0 ( optlc_net_91 ) ) ; cbx_1__1__mux_tree_tapbuf_size12_2 mux_top_ipin_4 ( .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[4] , chanx_left_out[4] , chanx_right_out[10] , chanx_left_out[10] , @@ -7848,7 +7843,7 @@ cbx_1__1__mux_tree_tapbuf_size12_2 mux_top_ipin_4 ( .sram ( mux_tree_tapbuf_size12_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , - .out ( bottom_grid_pin_4_ ) , .p0 ( optlc_net_93 ) ) ; + .out ( bottom_grid_pin_4_ ) , .p0 ( optlc_net_89 ) ) ; cbx_1__1__mux_tree_tapbuf_size12_3 mux_top_ipin_6 ( .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] , chanx_left_out[3] , chanx_right_out[6] , chanx_left_out[6] , @@ -7857,7 +7852,7 @@ cbx_1__1__mux_tree_tapbuf_size12_3 mux_top_ipin_6 ( .sram ( mux_tree_tapbuf_size12_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) , - .out ( bottom_grid_pin_6_ ) , .p0 ( optlc_net_97 ) ) ; + .out ( bottom_grid_pin_6_ ) , .p0 ( optlc_net_92 ) ) ; cbx_1__1__mux_tree_tapbuf_size12_4 mux_top_ipin_8 ( .in ( { chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[5] , chanx_left_out[5] , chanx_right_out[8] , chanx_left_out[8] , @@ -7866,7 +7861,7 @@ cbx_1__1__mux_tree_tapbuf_size12_4 mux_top_ipin_8 ( .sram ( mux_tree_tapbuf_size12_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 , SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) , - .out ( bottom_grid_pin_8_ ) , .p0 ( optlc_net_95 ) ) ; + .out ( bottom_grid_pin_8_ ) , .p0 ( optlc_net_89 ) ) ; cbx_1__1__mux_tree_tapbuf_size12_5 mux_top_ipin_10 ( .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[4] , chanx_left_out[4] , chanx_right_out[10] , chanx_left_out[10] , @@ -7875,7 +7870,7 @@ cbx_1__1__mux_tree_tapbuf_size12_5 mux_top_ipin_10 ( .sram ( mux_tree_tapbuf_size12_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 , SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) , - .out ( bottom_grid_pin_10_ ) , .p0 ( optlc_net_93 ) ) ; + .out ( bottom_grid_pin_10_ ) , .p0 ( optlc_net_89 ) ) ; cbx_1__1__mux_tree_tapbuf_size12_6 mux_top_ipin_12 ( .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] , chanx_left_out[3] , chanx_right_out[6] , chanx_left_out[6] , @@ -7884,7 +7879,7 @@ cbx_1__1__mux_tree_tapbuf_size12_6 mux_top_ipin_12 ( .sram ( mux_tree_tapbuf_size12_6_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) , - .out ( bottom_grid_pin_12_ ) , .p0 ( optlc_net_97 ) ) ; + .out ( bottom_grid_pin_12_ ) , .p0 ( optlc_net_92 ) ) ; cbx_1__1__mux_tree_tapbuf_size12 mux_top_ipin_14 ( .in ( { chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[5] , chanx_left_out[5] , chanx_right_out[8] , chanx_left_out[8] , @@ -7893,7 +7888,7 @@ cbx_1__1__mux_tree_tapbuf_size12 mux_top_ipin_14 ( .sram ( mux_tree_tapbuf_size12_7_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 , SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) , - .out ( bottom_grid_pin_14_ ) , .p0 ( optlc_net_93 ) ) ; + .out ( bottom_grid_pin_14_ ) , .p0 ( optlc_net_91 ) ) ; cbx_1__1__mux_tree_tapbuf_size12_mem_0 mem_top_ipin_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size12_mem_0_ccff_tail ) , @@ -7941,7 +7936,7 @@ cbx_1__1__mux_tree_tapbuf_size10_0 mux_top_ipin_1 ( .sram ( mux_tree_tapbuf_size10_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 , SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) , - .out ( bottom_grid_pin_1_ ) , .p0 ( optlc_net_93 ) ) ; + .out ( bottom_grid_pin_1_ ) , .p0 ( optlc_net_89 ) ) ; cbx_1__1__mux_tree_tapbuf_size10_1 mux_top_ipin_3 ( .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] , chanx_left_out[3] , chanx_right_out[9] , chanx_left_out[9] , @@ -7950,7 +7945,7 @@ cbx_1__1__mux_tree_tapbuf_size10_1 mux_top_ipin_3 ( .sram ( mux_tree_tapbuf_size10_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 , SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) , - .out ( bottom_grid_pin_3_ ) , .p0 ( optlc_net_93 ) ) ; + .out ( bottom_grid_pin_3_ ) , .p0 ( optlc_net_92 ) ) ; cbx_1__1__mux_tree_tapbuf_size10_2 mux_top_ipin_5 ( .in ( { chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[5] , chanx_left_out[5] , chanx_right_out[11] , chanx_left_out[11] , @@ -7959,7 +7954,7 @@ cbx_1__1__mux_tree_tapbuf_size10_2 mux_top_ipin_5 ( .sram ( mux_tree_tapbuf_size10_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 , SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) , - .out ( bottom_grid_pin_5_ ) , .p0 ( optlc_net_95 ) ) ; + .out ( bottom_grid_pin_5_ ) , .p0 ( optlc_net_91 ) ) ; cbx_1__1__mux_tree_tapbuf_size10_3 mux_top_ipin_7 ( .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[4] , chanx_left_out[4] , chanx_right_out[7] , chanx_left_out[7] , @@ -7968,7 +7963,7 @@ cbx_1__1__mux_tree_tapbuf_size10_3 mux_top_ipin_7 ( .sram ( mux_tree_tapbuf_size10_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 , SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) , - .out ( bottom_grid_pin_7_ ) , .p0 ( optlc_net_93 ) ) ; + .out ( bottom_grid_pin_7_ ) , .p0 ( optlc_net_91 ) ) ; cbx_1__1__mux_tree_tapbuf_size10_4 mux_top_ipin_9 ( .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] , chanx_left_out[3] , chanx_right_out[9] , chanx_left_out[9] , @@ -7977,7 +7972,7 @@ cbx_1__1__mux_tree_tapbuf_size10_4 mux_top_ipin_9 ( .sram ( mux_tree_tapbuf_size10_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 , SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) , - .out ( bottom_grid_pin_9_ ) , .p0 ( optlc_net_96 ) ) ; + .out ( bottom_grid_pin_9_ ) , .p0 ( optlc_net_92 ) ) ; cbx_1__1__mux_tree_tapbuf_size10_5 mux_top_ipin_11 ( .in ( { chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[5] , chanx_left_out[5] , chanx_right_out[11] , chanx_left_out[11] , @@ -7986,7 +7981,7 @@ cbx_1__1__mux_tree_tapbuf_size10_5 mux_top_ipin_11 ( .sram ( mux_tree_tapbuf_size10_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 , SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) , - .out ( bottom_grid_pin_11_ ) , .p0 ( optlc_net_94 ) ) ; + .out ( bottom_grid_pin_11_ ) , .p0 ( optlc_net_90 ) ) ; cbx_1__1__mux_tree_tapbuf_size10_6 mux_top_ipin_13 ( .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[4] , chanx_left_out[4] , chanx_right_out[13] , chanx_left_out[13] , @@ -7995,7 +7990,7 @@ cbx_1__1__mux_tree_tapbuf_size10_6 mux_top_ipin_13 ( .sram ( mux_tree_tapbuf_size10_6_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 , SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) , - .out ( bottom_grid_pin_13_ ) , .p0 ( optlc_net_94 ) ) ; + .out ( bottom_grid_pin_13_ ) , .p0 ( optlc_net_90 ) ) ; cbx_1__1__mux_tree_tapbuf_size10 mux_top_ipin_15 ( .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] , chanx_left_out[3] , chanx_right_out[6] , chanx_left_out[6] , @@ -8004,7 +7999,7 @@ cbx_1__1__mux_tree_tapbuf_size10 mux_top_ipin_15 ( .sram ( mux_tree_tapbuf_size10_7_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 , SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) , - .out ( bottom_grid_pin_15_ ) , .p0 ( optlc_net_97 ) ) ; + .out ( bottom_grid_pin_15_ ) , .p0 ( optlc_net_92 ) ) ; cbx_1__1__mux_tree_tapbuf_size10_mem_0 mem_top_ipin_1 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size12_mem_0_ccff_tail ) , @@ -8043,19 +8038,19 @@ cbx_1__1__mux_tree_tapbuf_size10_mem_6 mem_top_ipin_13 ( .pReset ( pReset ) , cbx_1__1__mux_tree_tapbuf_size10_mem mem_top_ipin_15 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size12_mem_7_ccff_tail ) , - .ccff_tail ( { copt_net_108 } ) , + .ccff_tail ( { copt_net_100 } ) , .mem_out ( mux_tree_tapbuf_size10_7_sram ) ) ; sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_W_in ) , .X ( pReset[0] ) ) ; sky130_fd_sc_hd__buf_4 pReset_W_FTB01 ( .A ( pReset_W_in ) , .X ( pReset_W_out ) ) ; -sky130_fd_sc_hd__bufbuf_16 pReset_S_FTB01 ( .A ( pReset_W_in ) , +sky130_fd_sc_hd__buf_4 pReset_S_FTB01 ( .A ( pReset_W_in ) , .X ( pReset_S_out ) ) ; sky130_fd_sc_hd__buf_4 pReset_E_FTB01 ( .A ( pReset_W_in ) , .X ( pReset_E_out ) ) ; sky130_fd_sc_hd__buf_2 prog_clk_0_FTB00 ( .A ( prog_clk_0_N_in ) , .X ( prog_clk[0] ) ) ; sky130_fd_sc_hd__clkbuf_1 prog_clk_0_W_FTB01 ( .A ( prog_clk_0_N_in ) , - .X ( ctsbuf_net_198 ) ) ; + .X ( ctsbuf_net_193 ) ) ; sky130_fd_sc_hd__bufbuf_16 prog_clk_1_N_FTB01 ( .A ( prog_clk_1_E_in ) , .X ( prog_clk_1_N_out ) ) ; sky130_fd_sc_hd__buf_4 prog_clk_1_S_FTB01 ( .A ( prog_clk_1_E_in ) , @@ -8063,21 +8058,23 @@ sky130_fd_sc_hd__buf_4 prog_clk_1_S_FTB01 ( .A ( prog_clk_1_E_in ) , sky130_fd_sc_hd__buf_4 prog_clk_2_W_FTB01 ( .A ( prog_clk_2_W_in ) , .X ( prog_clk_2_W_out ) ) ; sky130_fd_sc_hd__buf_4 prog_clk_2_E_FTB01 ( .A ( prog_clk_2_W_in ) , - .X ( prog_clk_2_E_out ) ) ; + .X ( aps_rename_505_ ) ) ; sky130_fd_sc_hd__buf_4 prog_clk_3_E_FTB01 ( .A ( prog_clk_3_E_in ) , - .X ( prog_clk_3_E_out ) ) ; + .X ( aps_rename_506_ ) ) ; sky130_fd_sc_hd__buf_4 prog_clk_3_W_FTB01 ( .A ( prog_clk_3_E_in ) , .X ( prog_clk_3_W_out ) ) ; sky130_fd_sc_hd__bufbuf_16 clk_1_N_FTB01 ( .A ( clk_1_E_in ) , .X ( clk_1_N_out ) ) ; -sky130_fd_sc_hd__buf_1 clk_1_S_FTB01 ( .A ( clk_1_E_in ) , .X ( net_net_88 ) ) ; +sky130_fd_sc_hd__buf_4 clk_1_S_FTB01 ( .A ( clk_1_E_in ) , + .X ( clk_1_S_out ) ) ; sky130_fd_sc_hd__buf_4 clk_2_W_FTB01 ( .A ( clk_2_W_in ) , .X ( clk_2_W_out ) ) ; sky130_fd_sc_hd__buf_4 clk_2_E_FTB01 ( .A ( clk_2_W_in ) , - .X ( clk_2_E_out ) ) ; + .X ( aps_rename_507_ ) ) ; sky130_fd_sc_hd__buf_4 clk_3_E_FTB01 ( .A ( clk_3_E_in ) , - .X ( clk_3_E_out ) ) ; -sky130_fd_sc_hd__buf_4 clk_3_W_FTB01 ( .A ( clk_3_E_in ) , .X ( ZBUF_39_0 ) ) ; + .X ( aps_rename_508_ ) ) ; +sky130_fd_sc_hd__buf_4 clk_3_W_FTB01 ( .A ( clk_3_E_in ) , + .X ( clk_3_W_out ) ) ; sky130_fd_sc_hd__buf_8 FTB_17__16 ( .A ( chanx_left_in[0] ) , .X ( chanx_right_out[0] ) ) ; sky130_fd_sc_hd__buf_8 FTB_18__17 ( .A ( chanx_left_in[1] ) , @@ -8096,8 +8093,8 @@ sky130_fd_sc_hd__buf_8 FTB_24__23 ( .A ( chanx_left_in[7] ) , .X ( chanx_right_out[7] ) ) ; sky130_fd_sc_hd__buf_8 FTB_25__24 ( .A ( chanx_left_in[8] ) , .X ( chanx_right_out[8] ) ) ; -sky130_fd_sc_hd__buf_6 FTB_26__25 ( .A ( chanx_left_in[9] ) , - .X ( ropt_net_130 ) ) ; +sky130_fd_sc_hd__buf_8 FTB_26__25 ( .A ( chanx_left_in[9] ) , + .X ( chanx_right_out[9] ) ) ; sky130_fd_sc_hd__buf_8 FTB_27__26 ( .A ( chanx_left_in[10] ) , .X ( chanx_right_out[10] ) ) ; sky130_fd_sc_hd__buf_8 FTB_28__27 ( .A ( chanx_left_in[11] ) , @@ -8124,8 +8121,8 @@ sky130_fd_sc_hd__buf_8 FTB_38__37 ( .A ( chanx_left_in[21] ) , .X ( chanx_right_out[21] ) ) ; sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chanx_left_in[22] ) , .X ( chanx_right_out[22] ) ) ; -sky130_fd_sc_hd__buf_1 FTB_40__39 ( .A ( chanx_left_in[23] ) , - .X ( ropt_net_121 ) ) ; +sky130_fd_sc_hd__buf_6 FTB_40__39 ( .A ( chanx_left_in[23] ) , + .X ( chanx_right_out[23] ) ) ; sky130_fd_sc_hd__buf_8 FTB_41__40 ( .A ( chanx_left_in[24] ) , .X ( chanx_right_out[24] ) ) ; sky130_fd_sc_hd__buf_8 FTB_42__41 ( .A ( chanx_left_in[25] ) , @@ -8184,8 +8181,8 @@ sky130_fd_sc_hd__buf_8 FTB_68__67 ( .A ( chanx_right_in[21] ) , .X ( chanx_left_out[21] ) ) ; sky130_fd_sc_hd__buf_8 FTB_69__68 ( .A ( chanx_right_in[22] ) , .X ( chanx_left_out[22] ) ) ; -sky130_fd_sc_hd__buf_1 FTB_70__69 ( .A ( chanx_right_in[23] ) , - .X ( ropt_net_132 ) ) ; +sky130_fd_sc_hd__buf_6 FTB_70__69 ( .A ( chanx_right_in[23] ) , + .X ( chanx_left_out[23] ) ) ; sky130_fd_sc_hd__buf_8 FTB_71__70 ( .A ( chanx_right_in[24] ) , .X ( chanx_left_out[24] ) ) ; sky130_fd_sc_hd__buf_8 FTB_72__71 ( .A ( chanx_right_in[25] ) , @@ -8198,55 +8195,34 @@ sky130_fd_sc_hd__buf_8 FTB_75__74 ( .A ( chanx_right_in[28] ) , .X ( chanx_left_out[28] ) ) ; sky130_fd_sc_hd__buf_8 FTB_76__75 ( .A ( chanx_right_in[29] ) , .X ( chanx_left_out[29] ) ) ; -sky130_fd_sc_hd__buf_1 FTB_77__76 ( .A ( SC_IN_TOP ) , .X ( ropt_net_124 ) ) ; +sky130_fd_sc_hd__buf_8 FTB_77__76 ( .A ( SC_IN_TOP ) , .X ( SC_OUT_BOT ) ) ; sky130_fd_sc_hd__buf_6 FTB_78__77 ( .A ( SC_IN_BOT ) , .X ( SC_OUT_TOP ) ) ; sky130_fd_sc_hd__buf_6 FTB_79__78 ( .A ( REGIN_FEEDTHROUGH ) , .X ( REGOUT_FEEDTHROUGH ) ) ; -sky130_fd_sc_hd__buf_1 FTB_80__79 ( .A ( CIN_FEEDTHROUGH ) , - .X ( ropt_net_125 ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_88 ( .A ( net_net_88 ) , .X ( clk_1_S_out ) ) ; -sky130_fd_sc_hd__conb_1 optlc_95 ( .LO ( SYNOPSYS_UNCONNECTED_65 ) , - .HI ( optlc_net_93 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_97 ( .LO ( SYNOPSYS_UNCONNECTED_66 ) , - .HI ( optlc_net_94 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_100 ( .LO ( SYNOPSYS_UNCONNECTED_67 ) , - .HI ( optlc_net_95 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_102 ( .LO ( SYNOPSYS_UNCONNECTED_68 ) , - .HI ( optlc_net_96 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_104 ( .LO ( SYNOPSYS_UNCONNECTED_69 ) , - .HI ( optlc_net_97 ) ) ; -sky130_fd_sc_hd__buf_6 ZBUF_39_inst_1345 ( .A ( ZBUF_39_0 ) , - .X ( clk_3_W_out ) ) ; -sky130_fd_sc_hd__buf_6 cts_buf_3531232 ( .A ( ctsbuf_net_198 ) , - .X ( prog_clk_0_W_out ) ) ; -sky130_fd_sc_hd__bufbuf_8 copt_h_inst_1353 ( .A ( copt_net_109 ) , - .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1354 ( .A ( ropt_net_133 ) , - .X ( copt_net_109 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1355 ( .A ( copt_net_111 ) , - .X ( copt_net_110 ) ) ; -sky130_fd_sc_hd__buf_2 copt_h_inst_1356 ( .A ( copt_net_108 ) , - .X ( copt_net_111 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1357 ( .A ( copt_net_110 ) , - .X ( copt_net_112 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1358 ( .A ( ropt_net_135 ) , - .X ( copt_net_113 ) ) ; -sky130_fd_sc_hd__buf_6 ropt_mt_inst_1371 ( .A ( ropt_net_124 ) , - .X ( SC_OUT_BOT ) ) ; -sky130_fd_sc_hd__buf_6 ropt_mt_inst_1372 ( .A ( ropt_net_125 ) , +sky130_fd_sc_hd__buf_6 FTB_80__79 ( .A ( CIN_FEEDTHROUGH ) , .X ( COUT_FEEDTHROUGH ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1377 ( .A ( ropt_net_130 ) , - .X ( chanx_right_out[9] ) ) ; -sky130_fd_sc_hd__buf_6 ropt_mt_inst_1379 ( .A ( ropt_net_132 ) , - .X ( chanx_left_out[23] ) ) ; -sky130_fd_sc_hd__buf_1 ropt_h_inst_1380 ( .A ( copt_net_113 ) , - .X ( ropt_net_133 ) ) ; -sky130_fd_sc_hd__buf_1 ropt_h_inst_1381 ( .A ( copt_net_112 ) , - .X ( ropt_net_134 ) ) ; -sky130_fd_sc_hd__buf_6 ropt_mt_inst_1367 ( .A ( ropt_net_121 ) , - .X ( chanx_right_out[23] ) ) ; -sky130_fd_sc_hd__buf_1 ropt_h_inst_1382 ( .A ( ropt_net_134 ) , - .X ( ropt_net_135 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_91 ( .LO ( SYNOPSYS_UNCONNECTED_65 ) , + .HI ( optlc_net_89 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_93 ( .LO ( SYNOPSYS_UNCONNECTED_66 ) , + .HI ( optlc_net_90 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_95 ( .LO ( SYNOPSYS_UNCONNECTED_67 ) , + .HI ( optlc_net_91 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_97 ( .LO ( SYNOPSYS_UNCONNECTED_68 ) , + .HI ( optlc_net_92 ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_6_f_inst_602 ( .A ( aps_rename_507_ ) , + .X ( clk_2_E_out ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_6_f_inst_603 ( .A ( aps_rename_505_ ) , + .X ( prog_clk_2_E_out ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_240_f_inst_604 ( .A ( aps_rename_508_ ) , + .X ( clk_3_E_out ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_39_inst_605 ( .A ( aps_rename_506_ ) , + .X ( prog_clk_3_E_out ) ) ; +sky130_fd_sc_hd__buf_6 copt_h_inst_1328 ( .A ( copt_net_102 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__buf_6 cts_buf_3531229 ( .A ( ctsbuf_net_193 ) , + .X ( prog_clk_0_W_out ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1330 ( .A ( copt_net_100 ) , + .X ( copt_net_102 ) ) ; endmodule @@ -9018,7 +8994,7 @@ sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) ) ; sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , .TE_B ( SOC_DIR ) , .Z ( SOC_OUT ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_89 ( .A ( net_net_89 ) , .X ( SOC_DIR ) ) ; +sky130_fd_sc_hd__buf_8 BUFT_RR_89 ( .A ( net_net_89 ) , .X ( SOC_DIR ) ) ; endmodule @@ -10246,7 +10222,7 @@ sky130_fd_sc_hd__buf_8 FTB_37__36 ( .A ( chanx_left_in[18] ) , .X ( chanx_right_out[18] ) ) ; sky130_fd_sc_hd__buf_8 FTB_38__37 ( .A ( chanx_left_in[19] ) , .X ( chanx_right_out[19] ) ) ; -sky130_fd_sc_hd__buf_12 FTB_39__38 ( .A ( chanx_left_in[20] ) , +sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chanx_left_in[20] ) , .X ( chanx_right_out[20] ) ) ; sky130_fd_sc_hd__buf_8 FTB_40__39 ( .A ( chanx_left_in[21] ) , .X ( chanx_right_out[21] ) ) ; @@ -10464,9 +10440,9 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_131 ( .A ( BUF_net_132 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_132 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .Y ( BUF_net_132 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_139 ( .A ( BUF_net_140 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_140 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .Y ( BUF_net_140 ) ) ; endmodule @@ -10519,8 +10495,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; sb_2__2__const1_50 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , @@ -10529,6 +10503,9 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_137 ( .A ( BUF_net_138 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_138 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .Y ( BUF_net_138 ) ) ; endmodule @@ -10558,9 +10535,9 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_129 ( .A ( BUF_net_130 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_130 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .Y ( BUF_net_130 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_135 ( .A ( BUF_net_136 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_136 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .Y ( BUF_net_136 ) ) ; endmodule @@ -10572,15 +10549,14 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -wire copt_net_172 ; - sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( copt_net_172 ) ) ; -sky130_fd_sc_hd__buf_6 FTB_49__48 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1348 ( .A ( copt_net_172 ) , - .X ( mem_out[1] ) ) ; + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_49__48 ( .A ( copt_net_165 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1335 ( .A ( mem_out[1] ) , + .X ( copt_net_165 ) ) ; endmodule @@ -11177,13 +11153,14 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; sb_2__2__const1_48 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_134 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_134 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_149 ( .A ( BUF_net_134 ) , .Y ( out[0] ) ) ; endmodule @@ -11236,9 +11213,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_128 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_128 ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_151 ( .A ( BUF_net_128 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_131 ( .A ( BUF_net_132 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_132 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_132 ) ) ; endmodule @@ -11264,9 +11241,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_149 ( .A ( BUF_net_150 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_150 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_150 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_129 ( .A ( BUF_net_130 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_130 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_130 ) ) ; endmodule @@ -11292,9 +11269,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_147 ( .A ( BUF_net_148 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_148 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_148 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_127 ( .A ( BUF_net_128 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_128 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_128 ) ) ; endmodule @@ -11320,9 +11297,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_121 ( .A ( BUF_net_122 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_122 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_122 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_125 ( .A ( BUF_net_126 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_126 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_126 ) ) ; endmodule @@ -11348,9 +11325,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_119 ( .A ( BUF_net_120 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_120 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_120 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_123 ( .A ( BUF_net_124 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_124 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_124 ) ) ; endmodule @@ -11376,9 +11353,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_117 ( .A ( BUF_net_118 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_118 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_118 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_121 ( .A ( BUF_net_122 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_122 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_122 ) ) ; endmodule @@ -11404,9 +11381,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_145 ( .A ( BUF_net_146 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_146 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_146 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_119 ( .A ( BUF_net_120 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_120 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_120 ) ) ; endmodule @@ -11459,9 +11436,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_113 ( .A ( BUF_net_114 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_114 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_114 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_117 ( .A ( BUF_net_118 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_118 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_118 ) ) ; endmodule @@ -11487,9 +11464,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_111 ( .A ( BUF_net_112 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_112 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_112 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_115 ( .A ( BUF_net_116 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_116 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_116 ) ) ; endmodule @@ -11515,9 +11492,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_109 ( .A ( BUF_net_110 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_110 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_110 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_113 ( .A ( BUF_net_114 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_114 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_114 ) ) ; endmodule @@ -11538,13 +11515,14 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; sb_2__2__const1_35 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_147 ( .A ( BUF_net_148 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_148 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_148 ) ) ; endmodule @@ -11565,13 +11543,13 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; sb_2__2__const1_34 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_108 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .X ( out[0] ) ) ; endmodule @@ -11592,13 +11570,13 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; sb_2__2__const1_33 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_110 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) ) ; endmodule @@ -11619,13 +11597,13 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; sb_2__2__const1_32 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_107 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .X ( out[0] ) ) ; endmodule @@ -11651,9 +11629,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_105 ( .A ( BUF_net_106 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_106 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_106 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_108 ( .A ( BUF_net_109 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_109 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_109 ) ) ; endmodule @@ -11679,9 +11657,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_103 ( .A ( BUF_net_104 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_104 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_104 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_106 ( .A ( BUF_net_107 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_107 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_107 ) ) ; endmodule @@ -11707,9 +11685,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_101 ( .A ( BUF_net_102 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_102 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_102 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_104 ( .A ( BUF_net_105 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_105 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_105 ) ) ; endmodule @@ -11757,13 +11735,14 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; sb_2__2__const1_27 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_102 ( .A ( BUF_net_103 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_103 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_103 ) ) ; endmodule @@ -11789,9 +11768,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_99 ( .A ( BUF_net_100 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_100 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_100 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_100 ( .A ( BUF_net_101 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_101 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_101 ) ) ; endmodule @@ -11817,9 +11796,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_97 ( .A ( BUF_net_98 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_98 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_98 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_98 ( .A ( BUF_net_99 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_99 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_99 ) ) ; endmodule @@ -11845,9 +11824,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_95 ( .A ( BUF_net_96 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_96 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_96 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_96 ( .A ( BUF_net_97 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_97 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_97 ) ) ; endmodule @@ -11868,13 +11847,14 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; sb_2__2__const1_23 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_94 ( .A ( BUF_net_95 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_95 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_95 ) ) ; endmodule @@ -11895,14 +11875,13 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; sb_2__2__const1_22 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_93 ( .A ( BUF_net_94 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_94 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_94 ) ) ; endmodule @@ -11923,13 +11902,13 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; sb_2__2__const1_21 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_93 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) ) ; endmodule @@ -11955,9 +11934,8 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_91 ( .A ( BUF_net_92 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_92 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_92 ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_92 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) ) ; endmodule @@ -11983,9 +11961,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_89 ( .A ( BUF_net_90 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_90 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_90 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_90 ( .A ( BUF_net_91 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_91 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_91 ) ) ; endmodule @@ -12011,9 +11989,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_87 ( .A ( BUF_net_88 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_88 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_88 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_88 ( .A ( BUF_net_89 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_89 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_89 ) ) ; endmodule @@ -12039,9 +12017,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_85 ( .A ( BUF_net_86 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_86 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_86 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_86 ( .A ( BUF_net_87 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_87 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_87 ) ) ; endmodule @@ -12067,9 +12045,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_83 ( .A ( BUF_net_84 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_84 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_84 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_84 ( .A ( BUF_net_85 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_85 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_85 ) ) ; endmodule @@ -12095,9 +12073,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_81 ( .A ( BUF_net_82 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_82 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_82 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_82 ( .A ( BUF_net_83 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_83 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_83 ) ) ; endmodule @@ -12123,9 +12101,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_79 ( .A ( BUF_net_80 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_80 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_80 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_80 ( .A ( BUF_net_81 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_81 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_81 ) ) ; endmodule @@ -12151,7 +12129,7 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_78 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_79 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -12173,13 +12151,13 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; sb_2__2__const1_12 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_77 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .X ( out[0] ) ) ; endmodule @@ -12389,35 +12367,35 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_207 ) , +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_195 ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1339 ( .A ( copt_net_166 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1326 ( .A ( ccff_head[0] ) , + .X ( copt_net_156 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1327 ( .A ( copt_net_156 ) , + .X ( copt_net_157 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1328 ( .A ( copt_net_157 ) , + .X ( copt_net_158 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1329 ( .A ( copt_net_158 ) , + .X ( copt_net_159 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1330 ( .A ( ropt_net_198 ) , + .X ( copt_net_160 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1331 ( .A ( copt_net_160 ) , .X ( copt_net_161 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1340 ( .A ( ccff_head[0] ) , - .X ( copt_net_162 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1341 ( .A ( copt_net_161 ) , - .X ( copt_net_163 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1342 ( .A ( copt_net_162 ) , - .X ( copt_net_164 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1343 ( .A ( copt_net_163 ) , - .X ( copt_net_165 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1344 ( .A ( copt_net_164 ) , - .X ( copt_net_166 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1378 ( .A ( copt_net_165 ) , - .X ( ropt_net_203 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1379 ( .A ( ropt_net_205 ) , - .X ( ropt_net_204 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1380 ( .A ( ropt_net_203 ) , - .X ( ropt_net_205 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1381 ( .A ( ropt_net_204 ) , - .X ( ropt_net_206 ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 ropt_h_inst_1382 ( .A ( ropt_net_206 ) , - .X ( ropt_net_207 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1365 ( .A ( copt_net_161 ) , + .X ( ropt_net_195 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1366 ( .A ( copt_net_159 ) , + .X ( ropt_net_196 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1367 ( .A ( ropt_net_196 ) , + .X ( ropt_net_197 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1368 ( .A ( ropt_net_199 ) , + .X ( ropt_net_198 ) ) ; +sky130_fd_sc_hd__buf_1 ropt_h_inst_1369 ( .A ( ropt_net_197 ) , + .X ( ropt_net_199 ) ) ; endmodule @@ -12486,9 +12464,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_143 ( .A ( BUF_net_144 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_144 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .Y ( BUF_net_144 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_77 ( .A ( BUF_net_78 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_78 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_78 ) ) ; endmodule @@ -12522,9 +12500,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_73 ( .A ( BUF_net_74 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_74 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .Y ( BUF_net_74 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_75 ( .A ( BUF_net_76 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_76 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_76 ) ) ; endmodule @@ -12547,8 +12525,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; sb_2__2__const1_8 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , @@ -12556,10 +12532,13 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_74 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_74 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_141 ( .A ( BUF_net_74 ) , .Y ( out[0] ) ) ; endmodule @@ -12699,8 +12678,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_69 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .X ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_68 ( .A ( BUF_net_69 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_69 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_69 ) ) ; endmodule @@ -12734,9 +12714,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_67 ( .A ( BUF_net_68 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_68 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .Y ( BUF_net_68 ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_67 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .X ( out[0] ) ) ; endmodule @@ -12889,7 +12868,7 @@ output SC_OUT_BOT ; input pReset_W_in ; input prog_clk_0_S_in ; -wire ropt_net_182 ; +wire ropt_net_177 ; wire [0:0] prog_clk ; wire prog_clk_0 ; wire [0:1] mux_tree_tapbuf_size2_0_sram ; @@ -13006,84 +12985,84 @@ sb_2__2__mux_tree_tapbuf_size4_0 mux_bottom_track_1 ( .sram ( mux_tree_tapbuf_size4_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 } ) , - .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_153 ) ) ; + .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_154 ) ) ; sb_2__2__mux_tree_tapbuf_size4_1 mux_bottom_track_3 ( .in ( { bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_47_[0] , bottom_left_grid_pin_50_[0] , chanx_left_in[2] } ) , .sram ( mux_tree_tapbuf_size4_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 } ) , - .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_153 ) ) ; + .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_154 ) ) ; sb_2__2__mux_tree_tapbuf_size4_2 mux_bottom_track_5 ( .in ( { bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_48_[0] , bottom_left_grid_pin_51_[0] , chanx_left_in[3] } ) , .sram ( mux_tree_tapbuf_size4_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 , SYNOPSYS_UNCONNECTED_9 } ) , - .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_153 ) ) ; + .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_154 ) ) ; sb_2__2__mux_tree_tapbuf_size4_3 mux_bottom_track_7 ( .in ( { bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_46_[0] , bottom_left_grid_pin_49_[0] , chanx_left_in[4] } ) , .sram ( mux_tree_tapbuf_size4_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , - .out ( chany_bottom_out[3] ) , .p0 ( optlc_net_153 ) ) ; + .out ( chany_bottom_out[3] ) , .p0 ( optlc_net_154 ) ) ; sb_2__2__mux_tree_tapbuf_size4_4 mux_bottom_track_9 ( .in ( { bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_47_[0] , bottom_left_grid_pin_50_[0] , chanx_left_in[5] } ) , .sram ( mux_tree_tapbuf_size4_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , SYNOPSYS_UNCONNECTED_15 } ) , - .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_158 ) ) ; + .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_155 ) ) ; sb_2__2__mux_tree_tapbuf_size4_5 mux_bottom_track_11 ( .in ( { bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_48_[0] , bottom_left_grid_pin_51_[0] , chanx_left_in[6] } ) , .sram ( mux_tree_tapbuf_size4_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_16 , SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 } ) , - .out ( chany_bottom_out[5] ) , .p0 ( optlc_net_153 ) ) ; + .out ( chany_bottom_out[5] ) , .p0 ( optlc_net_155 ) ) ; sb_2__2__mux_tree_tapbuf_size4_6 mux_left_track_1 ( .in ( { chany_bottom_in[29] , left_top_grid_pin_1_[0] , left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size4_6_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 , SYNOPSYS_UNCONNECTED_21 } ) , - .out ( chanx_left_out[0] ) , .p0 ( optlc_net_154 ) ) ; + .out ( chanx_left_out[0] ) , .p0 ( optlc_net_151 ) ) ; sb_2__2__mux_tree_tapbuf_size4_7 mux_left_track_3 ( .in ( { chany_bottom_in[0] , left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_42_[0] } ) , .sram ( mux_tree_tapbuf_size4_7_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_22 , SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) , - .out ( chanx_left_out[1] ) , .p0 ( optlc_net_156 ) ) ; + .out ( chanx_left_out[1] ) , .p0 ( optlc_net_151 ) ) ; sb_2__2__mux_tree_tapbuf_size4_8 mux_left_track_5 ( .in ( { chany_bottom_in[1] , left_bottom_grid_pin_37_[0] , left_bottom_grid_pin_40_[0] , left_bottom_grid_pin_43_[0] } ) , .sram ( mux_tree_tapbuf_size4_8_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , SYNOPSYS_UNCONNECTED_27 } ) , - .out ( chanx_left_out[2] ) , .p0 ( optlc_net_159 ) ) ; + .out ( chanx_left_out[2] ) , .p0 ( optlc_net_151 ) ) ; sb_2__2__mux_tree_tapbuf_size4_9 mux_left_track_7 ( .in ( { chany_bottom_in[2] , left_top_grid_pin_1_[0] , left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size4_9_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_28 , SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 } ) , - .out ( chanx_left_out[3] ) , .p0 ( optlc_net_155 ) ) ; + .out ( chanx_left_out[3] ) , .p0 ( optlc_net_151 ) ) ; sb_2__2__mux_tree_tapbuf_size4_10 mux_left_track_9 ( .in ( { chany_bottom_in[3] , left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_42_[0] } ) , .sram ( mux_tree_tapbuf_size4_10_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 , SYNOPSYS_UNCONNECTED_33 } ) , - .out ( chanx_left_out[4] ) , .p0 ( optlc_net_156 ) ) ; + .out ( chanx_left_out[4] ) , .p0 ( optlc_net_151 ) ) ; sb_2__2__mux_tree_tapbuf_size4 mux_left_track_11 ( .in ( { chany_bottom_in[4] , left_bottom_grid_pin_37_[0] , left_bottom_grid_pin_40_[0] , left_bottom_grid_pin_43_[0] } ) , .sram ( mux_tree_tapbuf_size4_11_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_34 , SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) , - .out ( chanx_left_out[5] ) , .p0 ( optlc_net_159 ) ) ; + .out ( chanx_left_out[5] ) , .p0 ( optlc_net_151 ) ) ; sb_2__2__mux_tree_tapbuf_size4_mem_0 mem_bottom_track_1 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , @@ -13147,187 +13126,187 @@ sb_2__2__mux_tree_tapbuf_size2_0 mux_bottom_track_13 ( .in ( { bottom_right_grid_pin_1_[0] , chanx_left_in[7] } ) , .sram ( mux_tree_tapbuf_size2_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 } ) , - .out ( chany_bottom_out[6] ) , .p0 ( optlc_net_157 ) ) ; + .out ( chany_bottom_out[6] ) , .p0 ( optlc_net_152 ) ) ; sb_2__2__mux_tree_tapbuf_size2_1 mux_bottom_track_15 ( .in ( { bottom_left_grid_pin_44_[0] , chanx_left_in[8] } ) , .sram ( mux_tree_tapbuf_size2_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) , - .out ( chany_bottom_out[7] ) , .p0 ( optlc_net_158 ) ) ; + .out ( chany_bottom_out[7] ) , .p0 ( optlc_net_152 ) ) ; sb_2__2__mux_tree_tapbuf_size2_2 mux_bottom_track_17 ( .in ( { bottom_left_grid_pin_45_[0] , chanx_left_in[9] } ) , .sram ( mux_tree_tapbuf_size2_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 } ) , - .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_155 ) ) ; + .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_151 ) ) ; sb_2__2__mux_tree_tapbuf_size2_3 mux_bottom_track_19 ( .in ( { bottom_left_grid_pin_46_[0] , chanx_left_in[10] } ) , .sram ( mux_tree_tapbuf_size2_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) , - .out ( chany_bottom_out[9] ) , .p0 ( optlc_net_155 ) ) ; + .out ( chany_bottom_out[9] ) , .p0 ( optlc_net_151 ) ) ; sb_2__2__mux_tree_tapbuf_size2_4 mux_bottom_track_21 ( .in ( { bottom_left_grid_pin_47_[0] , chanx_left_in[11] } ) , .sram ( mux_tree_tapbuf_size2_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 } ) , - .out ( chany_bottom_out[10] ) , .p0 ( optlc_net_154 ) ) ; + .out ( chany_bottom_out[10] ) , .p0 ( optlc_net_151 ) ) ; sb_2__2__mux_tree_tapbuf_size2_5 mux_bottom_track_23 ( .in ( { bottom_left_grid_pin_48_[0] , chanx_left_in[12] } ) , .sram ( mux_tree_tapbuf_size2_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) , - .out ( chany_bottom_out[11] ) , .p0 ( optlc_net_153 ) ) ; + .out ( chany_bottom_out[11] ) , .p0 ( optlc_net_154 ) ) ; sb_2__2__mux_tree_tapbuf_size2_6 mux_bottom_track_25 ( .in ( { bottom_left_grid_pin_49_[0] , chanx_left_in[13] } ) , .sram ( mux_tree_tapbuf_size2_6_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 } ) , - .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_153 ) ) ; + .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_151 ) ) ; sb_2__2__mux_tree_tapbuf_size2_7 mux_bottom_track_27 ( .in ( { bottom_left_grid_pin_50_[0] , chanx_left_in[14] } ) , .sram ( mux_tree_tapbuf_size2_7_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) , - .out ( chany_bottom_out[13] ) , .p0 ( optlc_net_155 ) ) ; + .out ( chany_bottom_out[13] ) , .p0 ( optlc_net_151 ) ) ; sb_2__2__mux_tree_tapbuf_size2_8 mux_bottom_track_39 ( .in ( { bottom_left_grid_pin_44_[0] , chanx_left_in[20] } ) , .sram ( mux_tree_tapbuf_size2_8_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 } ) , - .out ( chany_bottom_out[19] ) , .p0 ( optlc_net_154 ) ) ; + .out ( chany_bottom_out[19] ) , .p0 ( optlc_net_152 ) ) ; sb_2__2__mux_tree_tapbuf_size2_9 mux_bottom_track_41 ( .in ( { bottom_left_grid_pin_45_[0] , chanx_left_in[21] } ) , .sram ( mux_tree_tapbuf_size2_9_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) , - .out ( chany_bottom_out[20] ) , .p0 ( optlc_net_153 ) ) ; + .out ( chany_bottom_out[20] ) , .p0 ( optlc_net_152 ) ) ; sb_2__2__mux_tree_tapbuf_size2_10 mux_bottom_track_43 ( .in ( { bottom_left_grid_pin_46_[0] , chanx_left_in[22] } ) , .sram ( mux_tree_tapbuf_size2_10_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 } ) , - .out ( chany_bottom_out[21] ) , .p0 ( optlc_net_157 ) ) ; + .out ( chany_bottom_out[21] ) , .p0 ( optlc_net_152 ) ) ; sb_2__2__mux_tree_tapbuf_size2_11 mux_bottom_track_47 ( .in ( { bottom_left_grid_pin_48_[0] , chanx_left_in[24] } ) , .sram ( mux_tree_tapbuf_size2_11_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) , - .out ( chany_bottom_out[23] ) , .p0 ( optlc_net_153 ) ) ; + .out ( chany_bottom_out[23] ) , .p0 ( optlc_net_155 ) ) ; sb_2__2__mux_tree_tapbuf_size2_12 mux_bottom_track_49 ( .in ( { bottom_left_grid_pin_49_[0] , chanx_left_in[25] } ) , .sram ( mux_tree_tapbuf_size2_12_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 } ) , - .out ( chany_bottom_out[24] ) , .p0 ( optlc_net_153 ) ) ; + .out ( chany_bottom_out[24] ) , .p0 ( optlc_net_154 ) ) ; sb_2__2__mux_tree_tapbuf_size2_13 mux_bottom_track_51 ( .in ( { bottom_left_grid_pin_50_[0] , chanx_left_in[26] } ) , .sram ( mux_tree_tapbuf_size2_13_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) , - .out ( chany_bottom_out[25] ) , .p0 ( optlc_net_155 ) ) ; + .out ( chany_bottom_out[25] ) , .p0 ( optlc_net_151 ) ) ; sb_2__2__mux_tree_tapbuf_size2_14 mux_bottom_track_53 ( .in ( { bottom_left_grid_pin_51_[0] , chanx_left_in[27] } ) , .sram ( mux_tree_tapbuf_size2_14_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 } ) , - .out ( chany_bottom_out[26] ) , .p0 ( optlc_net_155 ) ) ; + .out ( chany_bottom_out[26] ) , .p0 ( optlc_net_151 ) ) ; sb_2__2__mux_tree_tapbuf_size2_15 mux_left_track_13 ( .in ( { chany_bottom_in[5] , left_top_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size2_15_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 } ) , - .out ( chanx_left_out[6] ) , .p0 ( optlc_net_160 ) ) ; + .out ( chanx_left_out[6] ) , .p0 ( optlc_net_153 ) ) ; sb_2__2__mux_tree_tapbuf_size2_16 mux_left_track_15 ( .in ( { chany_bottom_in[6] , left_bottom_grid_pin_36_[0] } ) , .sram ( mux_tree_tapbuf_size2_16_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_69 , SYNOPSYS_UNCONNECTED_70 } ) , - .out ( chanx_left_out[7] ) , .p0 ( optlc_net_156 ) ) ; + .out ( chanx_left_out[7] ) , .p0 ( optlc_net_152 ) ) ; sb_2__2__mux_tree_tapbuf_size2_17 mux_left_track_17 ( .in ( { chany_bottom_in[7] , left_bottom_grid_pin_37_[0] } ) , .sram ( mux_tree_tapbuf_size2_17_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_71 , SYNOPSYS_UNCONNECTED_72 } ) , - .out ( chanx_left_out[8] ) , .p0 ( optlc_net_156 ) ) ; + .out ( chanx_left_out[8] ) , .p0 ( optlc_net_153 ) ) ; sb_2__2__mux_tree_tapbuf_size2_18 mux_left_track_19 ( .in ( { chany_bottom_in[8] , left_bottom_grid_pin_38_[0] } ) , .sram ( mux_tree_tapbuf_size2_18_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_73 , SYNOPSYS_UNCONNECTED_74 } ) , - .out ( chanx_left_out[9] ) , .p0 ( optlc_net_157 ) ) ; + .out ( chanx_left_out[9] ) , .p0 ( optlc_net_152 ) ) ; sb_2__2__mux_tree_tapbuf_size2_19 mux_left_track_21 ( .in ( { chany_bottom_in[9] , left_bottom_grid_pin_39_[0] } ) , .sram ( mux_tree_tapbuf_size2_19_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_75 , SYNOPSYS_UNCONNECTED_76 } ) , - .out ( chanx_left_out[10] ) , .p0 ( optlc_net_157 ) ) ; + .out ( chanx_left_out[10] ) , .p0 ( optlc_net_152 ) ) ; sb_2__2__mux_tree_tapbuf_size2_20 mux_left_track_23 ( .in ( { chany_bottom_in[10] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_tree_tapbuf_size2_20_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_77 , SYNOPSYS_UNCONNECTED_78 } ) , - .out ( chanx_left_out[11] ) , .p0 ( optlc_net_157 ) ) ; + .out ( chanx_left_out[11] ) , .p0 ( optlc_net_152 ) ) ; sb_2__2__mux_tree_tapbuf_size2_21 mux_left_track_25 ( .in ( { chany_bottom_in[11] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size2_21_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_79 , SYNOPSYS_UNCONNECTED_80 } ) , - .out ( chanx_left_out[12] ) , .p0 ( optlc_net_158 ) ) ; + .out ( chanx_left_out[12] ) , .p0 ( optlc_net_152 ) ) ; sb_2__2__mux_tree_tapbuf_size2_22 mux_left_track_27 ( .in ( { chany_bottom_in[12] , left_bottom_grid_pin_42_[0] } ) , .sram ( mux_tree_tapbuf_size2_22_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_81 , SYNOPSYS_UNCONNECTED_82 } ) , - .out ( chanx_left_out[13] ) , .p0 ( optlc_net_157 ) ) ; + .out ( chanx_left_out[13] ) , .p0 ( optlc_net_152 ) ) ; sb_2__2__mux_tree_tapbuf_size2_23 mux_left_track_31 ( .in ( { chany_bottom_in[14] , left_bottom_grid_pin_36_[0] } ) , .sram ( mux_tree_tapbuf_size2_23_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_83 , SYNOPSYS_UNCONNECTED_84 } ) , - .out ( chanx_left_out[15] ) , .p0 ( optlc_net_157 ) ) ; + .out ( chanx_left_out[15] ) , .p0 ( optlc_net_152 ) ) ; sb_2__2__mux_tree_tapbuf_size2_24 mux_left_track_33 ( .in ( { chany_bottom_in[15] , left_bottom_grid_pin_37_[0] } ) , .sram ( mux_tree_tapbuf_size2_24_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_85 , SYNOPSYS_UNCONNECTED_86 } ) , - .out ( chanx_left_out[16] ) , .p0 ( optlc_net_160 ) ) ; + .out ( chanx_left_out[16] ) , .p0 ( optlc_net_153 ) ) ; sb_2__2__mux_tree_tapbuf_size2_25 mux_left_track_35 ( .in ( { chany_bottom_in[16] , left_bottom_grid_pin_38_[0] } ) , .sram ( mux_tree_tapbuf_size2_25_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_87 , SYNOPSYS_UNCONNECTED_88 } ) , - .out ( chanx_left_out[17] ) , .p0 ( optlc_net_160 ) ) ; + .out ( chanx_left_out[17] ) , .p0 ( optlc_net_153 ) ) ; sb_2__2__mux_tree_tapbuf_size2_26 mux_left_track_37 ( .in ( { chany_bottom_in[17] , left_bottom_grid_pin_39_[0] } ) , .sram ( mux_tree_tapbuf_size2_26_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_89 , SYNOPSYS_UNCONNECTED_90 } ) , - .out ( chanx_left_out[18] ) , .p0 ( optlc_net_160 ) ) ; + .out ( chanx_left_out[18] ) , .p0 ( optlc_net_153 ) ) ; sb_2__2__mux_tree_tapbuf_size2_27 mux_left_track_39 ( .in ( { chany_bottom_in[18] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_tree_tapbuf_size2_27_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_91 , SYNOPSYS_UNCONNECTED_92 } ) , - .out ( chanx_left_out[19] ) , .p0 ( optlc_net_157 ) ) ; + .out ( chanx_left_out[19] ) , .p0 ( optlc_net_152 ) ) ; sb_2__2__mux_tree_tapbuf_size2_28 mux_left_track_41 ( .in ( { chany_bottom_in[19] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size2_28_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_93 , SYNOPSYS_UNCONNECTED_94 } ) , - .out ( chanx_left_out[20] ) , .p0 ( optlc_net_154 ) ) ; + .out ( chanx_left_out[20] ) , .p0 ( optlc_net_152 ) ) ; sb_2__2__mux_tree_tapbuf_size2_29 mux_left_track_43 ( .in ( { chany_bottom_in[20] , left_bottom_grid_pin_42_[0] } ) , .sram ( mux_tree_tapbuf_size2_29_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_95 , SYNOPSYS_UNCONNECTED_96 } ) , - .out ( chanx_left_out[21] ) , .p0 ( optlc_net_154 ) ) ; + .out ( chanx_left_out[21] ) , .p0 ( optlc_net_152 ) ) ; sb_2__2__mux_tree_tapbuf_size2_30 mux_left_track_45 ( .in ( { chany_bottom_in[21] , left_top_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size2_30_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_97 , SYNOPSYS_UNCONNECTED_98 } ) , - .out ( chanx_left_out[22] ) , .p0 ( optlc_net_154 ) ) ; + .out ( chanx_left_out[22] ) , .p0 ( optlc_net_153 ) ) ; sb_2__2__mux_tree_tapbuf_size2_31 mux_left_track_47 ( .in ( { chany_bottom_in[22] , left_bottom_grid_pin_36_[0] } ) , .sram ( mux_tree_tapbuf_size2_31_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_99 , SYNOPSYS_UNCONNECTED_100 } ) , - .out ( chanx_left_out[23] ) , .p0 ( optlc_net_156 ) ) ; + .out ( chanx_left_out[23] ) , .p0 ( optlc_net_153 ) ) ; sb_2__2__mux_tree_tapbuf_size2_32 mux_left_track_49 ( .in ( { chany_bottom_in[23] , left_bottom_grid_pin_37_[0] } ) , .sram ( mux_tree_tapbuf_size2_32_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_101 , SYNOPSYS_UNCONNECTED_102 } ) , - .out ( chanx_left_out[24] ) , .p0 ( optlc_net_156 ) ) ; + .out ( chanx_left_out[24] ) , .p0 ( optlc_net_151 ) ) ; sb_2__2__mux_tree_tapbuf_size2_33 mux_left_track_51 ( .in ( { chany_bottom_in[24] , left_bottom_grid_pin_38_[0] } ) , .sram ( mux_tree_tapbuf_size2_33_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_103 , SYNOPSYS_UNCONNECTED_104 } ) , - .out ( chanx_left_out[25] ) , .p0 ( optlc_net_154 ) ) ; + .out ( chanx_left_out[25] ) , .p0 ( optlc_net_151 ) ) ; sb_2__2__mux_tree_tapbuf_size2_34 mux_left_track_55 ( .in ( { chany_bottom_in[26] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_tree_tapbuf_size2_34_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_105 , SYNOPSYS_UNCONNECTED_106 } ) , - .out ( chanx_left_out[27] ) , .p0 ( optlc_net_154 ) ) ; + .out ( chanx_left_out[27] ) , .p0 ( optlc_net_151 ) ) ; sb_2__2__mux_tree_tapbuf_size2_35 mux_left_track_57 ( .in ( { chany_bottom_in[27] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size2_35_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_107 , SYNOPSYS_UNCONNECTED_108 } ) , - .out ( chanx_left_out[28] ) , .p0 ( optlc_net_158 ) ) ; + .out ( chanx_left_out[28] ) , .p0 ( optlc_net_155 ) ) ; sb_2__2__mux_tree_tapbuf_size2 mux_left_track_59 ( .in ( { chany_bottom_in[28] , left_bottom_grid_pin_42_[0] } ) , .sram ( mux_tree_tapbuf_size2_36_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_109 , SYNOPSYS_UNCONNECTED_110 } ) , - .out ( chanx_left_out[29] ) , .p0 ( optlc_net_158 ) ) ; + .out ( chanx_left_out[29] ) , .p0 ( optlc_net_155 ) ) ; sb_2__2__mux_tree_tapbuf_size2_mem_0 mem_bottom_track_13 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) , @@ -13517,25 +13496,25 @@ sb_2__2__mux_tree_tapbuf_size3_0 mux_bottom_track_29 ( chanx_left_in[15] } ) , .sram ( mux_tree_tapbuf_size3_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_111 , SYNOPSYS_UNCONNECTED_112 } ) , - .out ( chany_bottom_out[14] ) , .p0 ( optlc_net_155 ) ) ; + .out ( chany_bottom_out[14] ) , .p0 ( optlc_net_154 ) ) ; sb_2__2__mux_tree_tapbuf_size3_1 mux_bottom_track_45 ( .in ( { bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_47_[0] , chanx_left_in[23] } ) , .sram ( mux_tree_tapbuf_size3_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_113 , SYNOPSYS_UNCONNECTED_114 } ) , - .out ( chany_bottom_out[22] ) , .p0 ( optlc_net_153 ) ) ; + .out ( chany_bottom_out[22] ) , .p0 ( optlc_net_155 ) ) ; sb_2__2__mux_tree_tapbuf_size3_2 mux_left_track_29 ( .in ( { chany_bottom_in[13] , left_top_grid_pin_1_[0] , left_bottom_grid_pin_43_[0] } ) , .sram ( mux_tree_tapbuf_size3_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_115 , SYNOPSYS_UNCONNECTED_116 } ) , - .out ( chanx_left_out[14] ) , .p0 ( optlc_net_154 ) ) ; + .out ( chanx_left_out[14] ) , .p0 ( optlc_net_153 ) ) ; sb_2__2__mux_tree_tapbuf_size3 mux_left_track_53 ( .in ( { chany_bottom_in[25] , left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_43_[0] } ) , .sram ( mux_tree_tapbuf_size3_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_117 , SYNOPSYS_UNCONNECTED_118 } ) , - .out ( chanx_left_out[26] ) , .p0 ( optlc_net_156 ) ) ; + .out ( chanx_left_out[26] ) , .p0 ( optlc_net_151 ) ) ; sb_2__2__mux_tree_tapbuf_size3_mem_0 mem_bottom_track_29 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , @@ -13559,10 +13538,10 @@ sb_2__2__mux_tree_tapbuf_size3_mem mem_left_track_53 ( .pReset ( pReset ) , sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_W_in ) , .X ( pReset[0] ) ) ; sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_S_in ) , .X ( prog_clk[0] ) ) ; -sky130_fd_sc_hd__buf_6 FTB_54__53 ( .A ( chanx_left_in[0] ) , - .X ( ropt_net_182 ) ) ; -sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chanx_left_in[16] ) , - .X ( chany_bottom_out[15] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chanx_left_in[0] ) , + .X ( chany_bottom_out[29] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_55__54 ( .A ( chanx_left_in[16] ) , + .X ( ropt_net_177 ) ) ; sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chanx_left_in[17] ) , .X ( chany_bottom_out[16] ) ) ; sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chanx_left_in[18] ) , @@ -13574,24 +13553,18 @@ sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( chanx_left_in[28] ) , sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( chanx_left_in[29] ) , .X ( chany_bottom_out[28] ) ) ; sky130_fd_sc_hd__buf_6 FTB_61__60 ( .A ( SC_IN_BOT ) , .X ( SC_OUT_BOT ) ) ; -sky130_fd_sc_hd__conb_1 optlc_157 ( .LO ( SYNOPSYS_UNCONNECTED_119 ) , +sky130_fd_sc_hd__conb_1 optlc_153 ( .LO ( SYNOPSYS_UNCONNECTED_119 ) , + .HI ( optlc_net_151 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_158 ( .LO ( SYNOPSYS_UNCONNECTED_120 ) , + .HI ( optlc_net_152 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_160 ( .LO ( SYNOPSYS_UNCONNECTED_121 ) , .HI ( optlc_net_153 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_161 ( .LO ( SYNOPSYS_UNCONNECTED_120 ) , +sky130_fd_sc_hd__conb_1 optlc_162 ( .LO ( SYNOPSYS_UNCONNECTED_122 ) , .HI ( optlc_net_154 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_164 ( .LO ( SYNOPSYS_UNCONNECTED_121 ) , +sky130_fd_sc_hd__conb_1 optlc_164 ( .LO ( SYNOPSYS_UNCONNECTED_123 ) , .HI ( optlc_net_155 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_168 ( .LO ( SYNOPSYS_UNCONNECTED_122 ) , - .HI ( optlc_net_156 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_170 ( .LO ( SYNOPSYS_UNCONNECTED_123 ) , - .HI ( optlc_net_157 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_173 ( .LO ( SYNOPSYS_UNCONNECTED_124 ) , - .HI ( optlc_net_158 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_175 ( .LO ( SYNOPSYS_UNCONNECTED_125 ) , - .HI ( optlc_net_159 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_177 ( .LO ( SYNOPSYS_UNCONNECTED_126 ) , - .HI ( optlc_net_160 ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1359 ( .A ( ropt_net_182 ) , - .X ( chany_bottom_out[29] ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1347 ( .A ( ropt_net_177 ) , + .X ( chany_bottom_out[15] ) ) ; endmodule @@ -16189,7 +16162,7 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_166 ) , +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_172 ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; @@ -16208,16 +16181,16 @@ sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1322 ( .A ( copt_net_145 ) , .X ( copt_net_148 ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1323 ( .A ( ccff_head[0] ) , .X ( copt_net_149 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1324 ( .A ( ropt_net_168 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1324 ( .A ( ropt_net_174 ) , .X ( copt_net_150 ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1332 ( .A ( copt_net_147 ) , .X ( copt_net_158 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 ropt_h_inst_1337 ( .A ( copt_net_150 ) , - .X ( ropt_net_166 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1338 ( .A ( copt_net_158 ) , - .X ( ropt_net_167 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1339 ( .A ( ropt_net_167 ) , - .X ( ropt_net_168 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 ropt_h_inst_1343 ( .A ( copt_net_150 ) , + .X ( ropt_net_172 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1344 ( .A ( copt_net_158 ) , + .X ( ropt_net_173 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1345 ( .A ( ropt_net_173 ) , + .X ( ropt_net_174 ) ) ; endmodule @@ -16481,6 +16454,7 @@ input pReset_W_in ; output pReset_N_out ; input prog_clk_0_N_in ; +wire ropt_net_162 ; wire [0:0] prog_clk ; wire prog_clk_0 ; wire [0:3] mux_tree_tapbuf_size10_0_sram ; @@ -16747,7 +16721,7 @@ sb_2__1__mux_tree_tapbuf_size9_1 mux_top_track_10 ( SYNOPSYS_UNCONNECTED_44 , SYNOPSYS_UNCONNECTED_45 } ) , .out ( chany_top_out[5] ) , .p0 ( optlc_net_142 ) ) ; sb_2__1__mux_tree_tapbuf_size9 mux_bottom_track_11 ( - .in ( { chany_bottom_out[11] , chany_bottom_out[25] , + .in ( { ropt_net_162 , chany_bottom_out[25] , bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_46_[0] , bottom_left_grid_pin_48_[0] , bottom_left_grid_pin_50_[0] , chanx_left_in[5] , chanx_left_in[16] , chanx_left_in[27] } ) , @@ -16890,7 +16864,7 @@ sb_2__1__mux_tree_tapbuf_size6_3 mux_left_track_7 ( SYNOPSYS_UNCONNECTED_83 } ) , .out ( chanx_left_out[3] ) , .p0 ( optlc_net_143 ) ) ; sb_2__1__mux_tree_tapbuf_size6 mux_left_track_9 ( - .in ( { chany_bottom_out[11] , chany_bottom_in[4] , chany_top_out[11] , + .in ( { ropt_net_162 , chany_bottom_in[4] , chany_top_out[11] , left_bottom_grid_pin_37_[0] , left_bottom_grid_pin_40_[0] , left_bottom_grid_pin_43_[0] } ) , .sram ( mux_tree_tapbuf_size6_4_sram ) , @@ -17190,8 +17164,8 @@ sky130_fd_sc_hd__buf_8 FTB_53__52 ( .A ( chany_top_in[7] ) , .X ( chany_bottom_out[8] ) ) ; sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chany_top_in[8] ) , .X ( chany_bottom_out[9] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chany_top_in[10] ) , - .X ( chany_bottom_out[11] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_55__54 ( .A ( chany_top_in[10] ) , + .X ( ropt_net_162 ) ) ; sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chany_top_in[11] ) , .X ( chany_bottom_out[12] ) ) ; sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chany_top_in[12] ) , @@ -17272,6 +17246,8 @@ sky130_fd_sc_hd__conb_1 optlc_149 ( .LO ( SYNOPSYS_UNCONNECTED_144 ) , .HI ( optlc_net_143 ) ) ; sky130_fd_sc_hd__conb_1 optlc_151 ( .LO ( SYNOPSYS_UNCONNECTED_145 ) , .HI ( optlc_net_144 ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1336 ( .A ( ropt_net_162 ) , + .X ( chany_bottom_out[11] ) ) ; endmodule @@ -17283,14 +17259,14 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -wire copt_net_164 ; +wire copt_net_181 ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( copt_net_164 ) ) ; + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( copt_net_181 ) ) ; sky130_fd_sc_hd__buf_6 FTB_53__52 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1327 ( .A ( copt_net_164 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1345 ( .A ( copt_net_181 ) , .X ( mem_out[1] ) ) ; endmodule @@ -17877,9 +17853,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_119 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_119 ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_142 ( .A ( BUF_net_119 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_124 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_124 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_159 ( .A ( BUF_net_124 ) , .Y ( out[0] ) ) ; endmodule @@ -17905,9 +17881,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_117 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_117 ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_148 ( .A ( BUF_net_117 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_121 ( .A ( BUF_net_122 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_122 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_122 ) ) ; endmodule @@ -17933,7 +17909,7 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_115 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_120 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -17960,9 +17936,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_113 ( .A ( BUF_net_114 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_114 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_114 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_118 ( .A ( BUF_net_119 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_119 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_119 ) ) ; endmodule @@ -17985,12 +17961,11 @@ sb_2__0__const1_48 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_111 ( .A ( BUF_net_112 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_112 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_112 ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_117 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) ) ; endmodule @@ -18042,7 +18017,7 @@ sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; endmodule @@ -18070,9 +18045,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_109 ( .A ( BUF_net_110 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_110 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_110 ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_116 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_116 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_157 ( .A ( BUF_net_116 ) , .Y ( out[0] ) ) ; endmodule @@ -18093,13 +18068,13 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; sb_2__0__const1_44 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_114 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) ) ; endmodule @@ -18125,9 +18100,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_108 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_108 ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_140 ( .A ( BUF_net_108 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_113 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_113 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_155 ( .A ( BUF_net_113 ) , .Y ( out[0] ) ) ; endmodule @@ -18177,11 +18152,12 @@ sb_2__0__const1_41 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_106 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .X ( out[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_111 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_111 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_153 ( .A ( BUF_net_111 ) , .Y ( out[0] ) ) ; endmodule @@ -18207,7 +18183,7 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_105 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_109 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -18258,11 +18234,12 @@ sb_2__0__const1_38 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_104 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .X ( out[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_108 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_108 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_151 ( .A ( BUF_net_108 ) , .Y ( out[0] ) ) ; endmodule @@ -18288,9 +18265,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_102 ( .A ( BUF_net_103 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_103 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_103 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_105 ( .A ( BUF_net_106 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_106 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_106 ) ) ; endmodule @@ -18311,13 +18288,13 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; sb_2__0__const1_36 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_104 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) ) ; endmodule @@ -18343,9 +18320,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_101 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_101 ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_138 ( .A ( BUF_net_101 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_103 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_103 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_149 ( .A ( BUF_net_103 ) , .Y ( out[0] ) ) ; endmodule @@ -18395,11 +18372,12 @@ sb_2__0__const1_33 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_99 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .X ( out[0] ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_100 ( .A ( BUF_net_101 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_101 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_101 ) ) ; endmodule @@ -18425,9 +18403,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_98 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_98 ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_136 ( .A ( BUF_net_98 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_99 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_99 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_147 ( .A ( BUF_net_99 ) , .Y ( out[0] ) ) ; endmodule @@ -18448,13 +18426,14 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; sb_2__0__const1_31 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_97 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_97 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_145 ( .A ( BUF_net_97 ) , .Y ( out[0] ) ) ; endmodule @@ -18529,14 +18508,13 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; sb_2__0__const1_28 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_96 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_96 ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_134 ( .A ( BUF_net_96 ) , .Y ( out[0] ) ) ; endmodule @@ -18562,9 +18540,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_94 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_94 ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_146 ( .A ( BUF_net_94 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_95 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_95 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_143 ( .A ( BUF_net_95 ) , .Y ( out[0] ) ) ; endmodule @@ -18590,9 +18568,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_91 ( .A ( BUF_net_92 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_92 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_92 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_92 ( .A ( BUF_net_93 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_93 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_93 ) ) ; endmodule @@ -18645,9 +18623,8 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_89 ( .A ( BUF_net_90 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_90 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_90 ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_91 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) ) ; endmodule @@ -18727,8 +18704,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_88 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .X ( out[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_90 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_90 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_141 ( .A ( BUF_net_90 ) , .Y ( out[0] ) ) ; endmodule @@ -18749,13 +18727,14 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; sb_2__0__const1_20 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_87 ( .A ( BUF_net_88 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_88 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_88 ) ) ; endmodule @@ -18781,9 +18760,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_87 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_87 ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_132 ( .A ( BUF_net_87 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_86 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_86 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_139 ( .A ( BUF_net_86 ) , .Y ( out[0] ) ) ; endmodule @@ -18809,9 +18788,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_85 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_85 ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_130 ( .A ( BUF_net_85 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_84 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_84 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_137 ( .A ( BUF_net_84 ) , .Y ( out[0] ) ) ; endmodule @@ -18837,9 +18816,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_83 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_83 ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_128 ( .A ( BUF_net_83 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_82 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_82 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_135 ( .A ( BUF_net_82 ) , .Y ( out[0] ) ) ; endmodule @@ -18949,9 +18928,9 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_81 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .Y ( BUF_net_81 ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_126 ( .A ( BUF_net_81 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_79 ( .A ( BUF_net_80 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_80 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .Y ( BUF_net_80 ) ) ; endmodule @@ -18973,6 +18952,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; sb_2__0__const1_15 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , @@ -18981,8 +18962,6 @@ sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_79 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .X ( out[0] ) ) ; endmodule @@ -19014,7 +18993,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; sky130_fd_sc_hd__inv_2 BINV_R_78 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .Y ( BUF_net_78 ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_124 ( .A ( BUF_net_78 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_133 ( .A ( BUF_net_78 ) , .Y ( out[0] ) ) ; endmodule @@ -19067,8 +19046,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; sb_2__0__const1_12 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , @@ -19077,6 +19054,9 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_76 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .Y ( BUF_net_76 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_131 ( .A ( BUF_net_76 ) , .Y ( out[0] ) ) ; endmodule @@ -19286,35 +19266,35 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( copt_net_156 ) , +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_201 ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1318 ( .A ( copt_net_158 ) , - .X ( copt_net_154 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1319 ( .A ( copt_net_154 ) , - .X ( copt_net_155 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1320 ( .A ( copt_net_155 ) , - .X ( copt_net_156 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1321 ( .A ( ccff_head[0] ) , - .X ( copt_net_157 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1322 ( .A ( ropt_net_192 ) , - .X ( copt_net_158 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1323 ( .A ( copt_net_157 ) , - .X ( copt_net_159 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1393 ( .A ( ropt_net_196 ) , - .X ( ropt_net_192 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1394 ( .A ( copt_net_159 ) , - .X ( ropt_net_193 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1395 ( .A ( ropt_net_193 ) , - .X ( ropt_net_194 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1396 ( .A ( ropt_net_194 ) , - .X ( ropt_net_195 ) ) ; -sky130_fd_sc_hd__buf_1 ropt_h_inst_1397 ( .A ( ropt_net_195 ) , - .X ( ropt_net_196 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1336 ( .A ( ccff_head[0] ) , + .X ( copt_net_170 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1337 ( .A ( copt_net_172 ) , + .X ( copt_net_171 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1338 ( .A ( copt_net_170 ) , + .X ( copt_net_172 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1339 ( .A ( copt_net_175 ) , + .X ( copt_net_173 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1340 ( .A ( copt_net_173 ) , + .X ( copt_net_174 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1341 ( .A ( copt_net_171 ) , + .X ( copt_net_175 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1361 ( .A ( copt_net_174 ) , + .X ( ropt_net_197 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1362 ( .A ( ropt_net_197 ) , + .X ( ropt_net_198 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1363 ( .A ( ropt_net_198 ) , + .X ( ropt_net_199 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1364 ( .A ( ropt_net_199 ) , + .X ( ropt_net_200 ) ) ; +sky130_fd_sc_hd__buf_1 ropt_h_inst_1365 ( .A ( ropt_net_200 ) , + .X ( ropt_net_201 ) ) ; endmodule @@ -19348,9 +19328,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_76 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .Y ( BUF_net_76 ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_122 ( .A ( BUF_net_76 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_74 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_74 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_129 ( .A ( BUF_net_74 ) , .Y ( out[0] ) ) ; endmodule @@ -19380,13 +19360,12 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_73 ( .A ( BUF_net_74 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_74 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .Y ( BUF_net_74 ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_72 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .X ( out[0] ) ) ; endmodule @@ -19420,9 +19399,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_71 ( .A ( BUF_net_72 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_72 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .Y ( BUF_net_72 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_163 ( .A ( BUF_net_164 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_164 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_164 ) ) ; endmodule @@ -19456,9 +19435,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_69 ( .A ( BUF_net_70 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_70 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .Y ( BUF_net_70 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_68 ( .A ( BUF_net_69 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_69 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_69 ) ) ; endmodule @@ -19492,9 +19471,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_67 ( .A ( BUF_net_68 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_68 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .Y ( BUF_net_68 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_66 ( .A ( BUF_net_67 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_67 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_67 ) ) ; endmodule @@ -19517,6 +19496,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; sb_2__0__const1_6 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , @@ -19524,13 +19505,10 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_65 ( .A ( BUF_net_66 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_66 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .Y ( BUF_net_66 ) ) ; endmodule @@ -19564,7 +19542,7 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_64 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_65 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -19599,8 +19577,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_63 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .X ( out[0] ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_63 ( .A ( BUF_net_64 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_64 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_64 ) ) ; endmodule @@ -19669,9 +19648,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_62 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .Y ( BUF_net_62 ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_144 ( .A ( BUF_net_62 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_62 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .X ( out[0] ) ) ; endmodule @@ -19705,8 +19683,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_60 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .X ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_61 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_61 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_161 ( .A ( BUF_net_61 ) , .Y ( out[0] ) ) ; endmodule @@ -19784,7 +19763,6 @@ input pReset_W_in ; output pReset_N_out ; input prog_clk_0_N_in ; -wire ropt_net_174 ; wire [0:0] prog_clk ; wire prog_clk_0 ; wire [0:1] mux_tree_tapbuf_size2_0_sram ; @@ -19901,84 +19879,84 @@ sb_2__0__mux_tree_tapbuf_size4_0 mux_top_track_0 ( .sram ( mux_tree_tapbuf_size4_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 } ) , - .out ( chany_top_out[0] ) , .p0 ( optlc_net_152 ) ) ; + .out ( chany_top_out[0] ) , .p0 ( optlc_net_166 ) ) ; sb_2__0__mux_tree_tapbuf_size4_1 mux_top_track_2 ( .in ( { top_left_grid_pin_45_[0] , top_left_grid_pin_48_[0] , top_left_grid_pin_51_[0] , chanx_left_in[29] } ) , .sram ( mux_tree_tapbuf_size4_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 } ) , - .out ( chany_top_out[1] ) , .p0 ( optlc_net_151 ) ) ; + .out ( chany_top_out[1] ) , .p0 ( optlc_net_169 ) ) ; sb_2__0__mux_tree_tapbuf_size4_2 mux_top_track_4 ( .in ( { top_left_grid_pin_46_[0] , top_left_grid_pin_49_[0] , top_right_grid_pin_1_[0] , chanx_left_in[28] } ) , .sram ( mux_tree_tapbuf_size4_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 , SYNOPSYS_UNCONNECTED_9 } ) , - .out ( chany_top_out[2] ) , .p0 ( optlc_net_152 ) ) ; + .out ( chany_top_out[2] ) , .p0 ( optlc_net_166 ) ) ; sb_2__0__mux_tree_tapbuf_size4_3 mux_top_track_6 ( .in ( { top_left_grid_pin_44_[0] , top_left_grid_pin_47_[0] , top_left_grid_pin_50_[0] , chanx_left_in[27] } ) , .sram ( mux_tree_tapbuf_size4_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , - .out ( chany_top_out[3] ) , .p0 ( optlc_net_152 ) ) ; + .out ( chany_top_out[3] ) , .p0 ( optlc_net_166 ) ) ; sb_2__0__mux_tree_tapbuf_size4_4 mux_top_track_8 ( .in ( { top_left_grid_pin_45_[0] , top_left_grid_pin_48_[0] , top_left_grid_pin_51_[0] , chanx_left_in[26] } ) , .sram ( mux_tree_tapbuf_size4_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , SYNOPSYS_UNCONNECTED_15 } ) , - .out ( chany_top_out[4] ) , .p0 ( optlc_net_151 ) ) ; + .out ( chany_top_out[4] ) , .p0 ( optlc_net_169 ) ) ; sb_2__0__mux_tree_tapbuf_size4_5 mux_top_track_10 ( .in ( { top_left_grid_pin_46_[0] , top_left_grid_pin_49_[0] , top_right_grid_pin_1_[0] , chanx_left_in[25] } ) , .sram ( mux_tree_tapbuf_size4_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_16 , SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 } ) , - .out ( chany_top_out[5] ) , .p0 ( optlc_net_151 ) ) ; + .out ( chany_top_out[5] ) , .p0 ( optlc_net_169 ) ) ; sb_2__0__mux_tree_tapbuf_size4_6 mux_left_track_1 ( .in ( { chany_top_in[0] , left_bottom_grid_pin_1_[0] , left_bottom_grid_pin_7_[0] , left_bottom_grid_pin_13_[0] } ) , .sram ( mux_tree_tapbuf_size4_6_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 , SYNOPSYS_UNCONNECTED_21 } ) , - .out ( chanx_left_out[0] ) , .p0 ( optlc_net_153 ) ) ; + .out ( chanx_left_out[0] ) , .p0 ( optlc_net_165 ) ) ; sb_2__0__mux_tree_tapbuf_size4_7 mux_left_track_3 ( .in ( { chany_top_in[29] , left_bottom_grid_pin_3_[0] , left_bottom_grid_pin_9_[0] , left_bottom_grid_pin_15_[0] } ) , .sram ( mux_tree_tapbuf_size4_7_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_22 , SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) , - .out ( chanx_left_out[1] ) , .p0 ( optlc_net_153 ) ) ; + .out ( chanx_left_out[1] ) , .p0 ( optlc_net_165 ) ) ; sb_2__0__mux_tree_tapbuf_size4_8 mux_left_track_5 ( .in ( { chany_top_in[28] , left_bottom_grid_pin_5_[0] , left_bottom_grid_pin_11_[0] , left_bottom_grid_pin_17_[0] } ) , .sram ( mux_tree_tapbuf_size4_8_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , SYNOPSYS_UNCONNECTED_27 } ) , - .out ( chanx_left_out[2] ) , .p0 ( optlc_net_153 ) ) ; + .out ( chanx_left_out[2] ) , .p0 ( optlc_net_167 ) ) ; sb_2__0__mux_tree_tapbuf_size4_9 mux_left_track_7 ( .in ( { chany_top_in[27] , left_bottom_grid_pin_1_[0] , left_bottom_grid_pin_7_[0] , left_bottom_grid_pin_13_[0] } ) , .sram ( mux_tree_tapbuf_size4_9_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_28 , SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 } ) , - .out ( chanx_left_out[3] ) , .p0 ( optlc_net_153 ) ) ; + .out ( chanx_left_out[3] ) , .p0 ( optlc_net_165 ) ) ; sb_2__0__mux_tree_tapbuf_size4_10 mux_left_track_9 ( .in ( { chany_top_in[26] , left_bottom_grid_pin_3_[0] , left_bottom_grid_pin_9_[0] , left_bottom_grid_pin_15_[0] } ) , .sram ( mux_tree_tapbuf_size4_10_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 , SYNOPSYS_UNCONNECTED_33 } ) , - .out ( chanx_left_out[4] ) , .p0 ( optlc_net_150 ) ) ; + .out ( chanx_left_out[4] ) , .p0 ( optlc_net_168 ) ) ; sb_2__0__mux_tree_tapbuf_size4 mux_left_track_11 ( .in ( { chany_top_in[25] , left_bottom_grid_pin_5_[0] , left_bottom_grid_pin_11_[0] , left_bottom_grid_pin_17_[0] } ) , .sram ( mux_tree_tapbuf_size4_11_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_34 , SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) , - .out ( chanx_left_out[5] ) , .p0 ( optlc_net_150 ) ) ; + .out ( chanx_left_out[5] ) , .p0 ( optlc_net_168 ) ) ; sb_2__0__mux_tree_tapbuf_size4_mem_0 mem_top_track_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , @@ -20043,31 +20021,31 @@ sb_2__0__mux_tree_tapbuf_size3_0 mux_top_track_12 ( chanx_left_in[24] } ) , .sram ( mux_tree_tapbuf_size3_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 } ) , - .out ( chany_top_out[6] ) , .p0 ( optlc_net_151 ) ) ; + .out ( chany_top_out[6] ) , .p0 ( optlc_net_168 ) ) ; sb_2__0__mux_tree_tapbuf_size3_1 mux_top_track_44 ( .in ( { top_left_grid_pin_48_[0] , top_right_grid_pin_1_[0] , chanx_left_in[8] } ) , .sram ( mux_tree_tapbuf_size3_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) , - .out ( chany_top_out[22] ) , .p0 ( optlc_net_151 ) ) ; + .out ( chany_top_out[22] ) , .p0 ( optlc_net_169 ) ) ; sb_2__0__mux_tree_tapbuf_size3_2 mux_left_track_13 ( .in ( { chany_top_in[24] , left_bottom_grid_pin_1_[0] , left_bottom_grid_pin_17_[0] } ) , .sram ( mux_tree_tapbuf_size3_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 } ) , - .out ( chanx_left_out[6] ) , .p0 ( optlc_net_150 ) ) ; + .out ( chanx_left_out[6] ) , .p0 ( optlc_net_168 ) ) ; sb_2__0__mux_tree_tapbuf_size3_3 mux_left_track_29 ( .in ( { chany_top_in[16] , left_bottom_grid_pin_1_[0] , left_bottom_grid_pin_17_[0] } ) , .sram ( mux_tree_tapbuf_size3_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) , - .out ( chanx_left_out[14] ) , .p0 ( optlc_net_153 ) ) ; + .out ( chanx_left_out[14] ) , .p0 ( optlc_net_167 ) ) ; sb_2__0__mux_tree_tapbuf_size3 mux_left_track_45 ( .in ( { chany_top_in[8] , left_bottom_grid_pin_1_[0] , left_bottom_grid_pin_17_[0] } ) , .sram ( mux_tree_tapbuf_size3_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 } ) , - .out ( chanx_left_out[22] ) , .p0 ( optlc_net_153 ) ) ; + .out ( chanx_left_out[22] ) , .p0 ( optlc_net_167 ) ) ; sb_2__0__mux_tree_tapbuf_size3_mem_0 mem_top_track_12 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) , @@ -20097,182 +20075,182 @@ sb_2__0__mux_tree_tapbuf_size2_0 mux_top_track_14 ( .in ( { top_left_grid_pin_45_[0] , chanx_left_in[23] } ) , .sram ( mux_tree_tapbuf_size2_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) , - .out ( chany_top_out[7] ) , .p0 ( optlc_net_151 ) ) ; + .out ( chany_top_out[7] ) , .p0 ( optlc_net_169 ) ) ; sb_2__0__mux_tree_tapbuf_size2_1 mux_top_track_16 ( .in ( { top_left_grid_pin_46_[0] , chanx_left_in[22] } ) , .sram ( mux_tree_tapbuf_size2_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 } ) , - .out ( chany_top_out[8] ) , .p0 ( optlc_net_151 ) ) ; + .out ( chany_top_out[8] ) , .p0 ( optlc_net_169 ) ) ; sb_2__0__mux_tree_tapbuf_size2_2 mux_top_track_18 ( .in ( { top_left_grid_pin_47_[0] , chanx_left_in[21] } ) , .sram ( mux_tree_tapbuf_size2_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) , - .out ( chany_top_out[9] ) , .p0 ( optlc_net_151 ) ) ; + .out ( chany_top_out[9] ) , .p0 ( optlc_net_169 ) ) ; sb_2__0__mux_tree_tapbuf_size2_3 mux_top_track_20 ( .in ( { top_left_grid_pin_48_[0] , chanx_left_in[20] } ) , .sram ( mux_tree_tapbuf_size2_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 } ) , - .out ( chany_top_out[10] ) , .p0 ( optlc_net_151 ) ) ; + .out ( chany_top_out[10] ) , .p0 ( optlc_net_169 ) ) ; sb_2__0__mux_tree_tapbuf_size2_4 mux_top_track_22 ( .in ( { top_left_grid_pin_49_[0] , chanx_left_in[19] } ) , .sram ( mux_tree_tapbuf_size2_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) , - .out ( chany_top_out[11] ) , .p0 ( optlc_net_152 ) ) ; + .out ( chany_top_out[11] ) , .p0 ( optlc_net_166 ) ) ; sb_2__0__mux_tree_tapbuf_size2_5 mux_top_track_24 ( .in ( { top_left_grid_pin_50_[0] , chanx_left_in[18] } ) , .sram ( mux_tree_tapbuf_size2_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 } ) , - .out ( chany_top_out[12] ) , .p0 ( optlc_net_152 ) ) ; + .out ( chany_top_out[12] ) , .p0 ( optlc_net_166 ) ) ; sb_2__0__mux_tree_tapbuf_size2_6 mux_top_track_26 ( .in ( { top_left_grid_pin_51_[0] , chanx_left_in[17] } ) , .sram ( mux_tree_tapbuf_size2_6_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) , - .out ( chany_top_out[13] ) , .p0 ( optlc_net_152 ) ) ; + .out ( chany_top_out[13] ) , .p0 ( optlc_net_166 ) ) ; sb_2__0__mux_tree_tapbuf_size2_7 mux_top_track_28 ( .in ( { top_right_grid_pin_1_[0] , chanx_left_in[16] } ) , .sram ( mux_tree_tapbuf_size2_7_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 } ) , - .out ( chany_top_out[14] ) , .p0 ( optlc_net_152 ) ) ; + .out ( chany_top_out[14] ) , .p0 ( optlc_net_166 ) ) ; sb_2__0__mux_tree_tapbuf_size2_8 mux_top_track_36 ( .in ( { top_left_grid_pin_44_[0] , chanx_left_in[12] } ) , .sram ( mux_tree_tapbuf_size2_8_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) , - .out ( chany_top_out[18] ) , .p0 ( optlc_net_152 ) ) ; + .out ( chany_top_out[18] ) , .p0 ( optlc_net_166 ) ) ; sb_2__0__mux_tree_tapbuf_size2_9 mux_top_track_38 ( .in ( { top_left_grid_pin_45_[0] , chanx_left_in[11] } ) , .sram ( mux_tree_tapbuf_size2_9_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 } ) , - .out ( chany_top_out[19] ) , .p0 ( optlc_net_151 ) ) ; + .out ( chany_top_out[19] ) , .p0 ( optlc_net_169 ) ) ; sb_2__0__mux_tree_tapbuf_size2_10 mux_top_track_40 ( .in ( { top_left_grid_pin_46_[0] , chanx_left_in[10] } ) , .sram ( mux_tree_tapbuf_size2_10_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 } ) , - .out ( chany_top_out[20] ) , .p0 ( optlc_net_151 ) ) ; + .out ( chany_top_out[20] ) , .p0 ( optlc_net_166 ) ) ; sb_2__0__mux_tree_tapbuf_size2_11 mux_top_track_42 ( .in ( { top_left_grid_pin_47_[0] , chanx_left_in[9] } ) , .sram ( mux_tree_tapbuf_size2_11_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_69 , SYNOPSYS_UNCONNECTED_70 } ) , - .out ( chany_top_out[21] ) , .p0 ( optlc_net_151 ) ) ; + .out ( chany_top_out[21] ) , .p0 ( optlc_net_166 ) ) ; sb_2__0__mux_tree_tapbuf_size2_12 mux_top_track_46 ( .in ( { top_left_grid_pin_49_[0] , chanx_left_in[7] } ) , .sram ( mux_tree_tapbuf_size2_12_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_71 , SYNOPSYS_UNCONNECTED_72 } ) , - .out ( chany_top_out[23] ) , .p0 ( optlc_net_152 ) ) ; + .out ( chany_top_out[23] ) , .p0 ( optlc_net_166 ) ) ; sb_2__0__mux_tree_tapbuf_size2_13 mux_top_track_48 ( .in ( { top_left_grid_pin_50_[0] , chanx_left_in[6] } ) , .sram ( mux_tree_tapbuf_size2_13_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_73 , SYNOPSYS_UNCONNECTED_74 } ) , - .out ( chany_top_out[24] ) , .p0 ( optlc_net_152 ) ) ; + .out ( chany_top_out[24] ) , .p0 ( optlc_net_166 ) ) ; sb_2__0__mux_tree_tapbuf_size2_14 mux_top_track_50 ( .in ( { top_left_grid_pin_51_[0] , chanx_left_in[5] } ) , .sram ( mux_tree_tapbuf_size2_14_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_75 , SYNOPSYS_UNCONNECTED_76 } ) , - .out ( chany_top_out[25] ) , .p0 ( optlc_net_152 ) ) ; + .out ( chany_top_out[25] ) , .p0 ( optlc_net_166 ) ) ; sb_2__0__mux_tree_tapbuf_size2_15 mux_left_track_15 ( .in ( { chany_top_in[23] , left_bottom_grid_pin_3_[0] } ) , .sram ( mux_tree_tapbuf_size2_15_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_77 , SYNOPSYS_UNCONNECTED_78 } ) , - .out ( chanx_left_out[7] ) , .p0 ( optlc_net_150 ) ) ; + .out ( chanx_left_out[7] ) , .p0 ( optlc_net_168 ) ) ; sb_2__0__mux_tree_tapbuf_size2_16 mux_left_track_17 ( .in ( { chany_top_in[22] , left_bottom_grid_pin_5_[0] } ) , .sram ( mux_tree_tapbuf_size2_16_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_79 , SYNOPSYS_UNCONNECTED_80 } ) , - .out ( chanx_left_out[8] ) , .p0 ( optlc_net_150 ) ) ; + .out ( chanx_left_out[8] ) , .p0 ( optlc_net_169 ) ) ; sb_2__0__mux_tree_tapbuf_size2_17 mux_left_track_19 ( .in ( { chany_top_in[21] , left_bottom_grid_pin_7_[0] } ) , .sram ( mux_tree_tapbuf_size2_17_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_81 , SYNOPSYS_UNCONNECTED_82 } ) , - .out ( chanx_left_out[9] ) , .p0 ( optlc_net_151 ) ) ; + .out ( chanx_left_out[9] ) , .p0 ( optlc_net_169 ) ) ; sb_2__0__mux_tree_tapbuf_size2_18 mux_left_track_21 ( .in ( { chany_top_in[20] , left_bottom_grid_pin_9_[0] } ) , .sram ( mux_tree_tapbuf_size2_18_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_83 , SYNOPSYS_UNCONNECTED_84 } ) , - .out ( chanx_left_out[10] ) , .p0 ( optlc_net_151 ) ) ; + .out ( chanx_left_out[10] ) , .p0 ( optlc_net_169 ) ) ; sb_2__0__mux_tree_tapbuf_size2_19 mux_left_track_23 ( .in ( { chany_top_in[19] , left_bottom_grid_pin_11_[0] } ) , .sram ( mux_tree_tapbuf_size2_19_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_85 , SYNOPSYS_UNCONNECTED_86 } ) , - .out ( chanx_left_out[11] ) , .p0 ( optlc_net_153 ) ) ; + .out ( chanx_left_out[11] ) , .p0 ( optlc_net_167 ) ) ; sb_2__0__mux_tree_tapbuf_size2_20 mux_left_track_25 ( .in ( { chany_top_in[18] , left_bottom_grid_pin_13_[0] } ) , .sram ( mux_tree_tapbuf_size2_20_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_87 , SYNOPSYS_UNCONNECTED_88 } ) , - .out ( chanx_left_out[12] ) , .p0 ( optlc_net_152 ) ) ; + .out ( chanx_left_out[12] ) , .p0 ( optlc_net_167 ) ) ; sb_2__0__mux_tree_tapbuf_size2_21 mux_left_track_27 ( .in ( { chany_top_in[17] , left_bottom_grid_pin_15_[0] } ) , .sram ( mux_tree_tapbuf_size2_21_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_89 , SYNOPSYS_UNCONNECTED_90 } ) , - .out ( chanx_left_out[13] ) , .p0 ( optlc_net_153 ) ) ; + .out ( chanx_left_out[13] ) , .p0 ( optlc_net_167 ) ) ; sb_2__0__mux_tree_tapbuf_size2_22 mux_left_track_31 ( .in ( { chany_top_in[15] , left_bottom_grid_pin_3_[0] } ) , .sram ( mux_tree_tapbuf_size2_22_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_91 , SYNOPSYS_UNCONNECTED_92 } ) , - .out ( chanx_left_out[15] ) , .p0 ( optlc_net_152 ) ) ; + .out ( chanx_left_out[15] ) , .p0 ( optlc_net_166 ) ) ; sb_2__0__mux_tree_tapbuf_size2_23 mux_left_track_33 ( .in ( { chany_top_in[14] , left_bottom_grid_pin_5_[0] } ) , .sram ( mux_tree_tapbuf_size2_23_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_93 , SYNOPSYS_UNCONNECTED_94 } ) , - .out ( chanx_left_out[16] ) , .p0 ( optlc_net_152 ) ) ; + .out ( chanx_left_out[16] ) , .p0 ( optlc_net_166 ) ) ; sb_2__0__mux_tree_tapbuf_size2_24 mux_left_track_35 ( .in ( { chany_top_in[13] , left_bottom_grid_pin_7_[0] } ) , .sram ( mux_tree_tapbuf_size2_24_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_95 , SYNOPSYS_UNCONNECTED_96 } ) , - .out ( chanx_left_out[17] ) , .p0 ( optlc_net_151 ) ) ; + .out ( chanx_left_out[17] ) , .p0 ( optlc_net_169 ) ) ; sb_2__0__mux_tree_tapbuf_size2_25 mux_left_track_37 ( .in ( { chany_top_in[12] , left_bottom_grid_pin_9_[0] } ) , .sram ( mux_tree_tapbuf_size2_25_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_97 , SYNOPSYS_UNCONNECTED_98 } ) , - .out ( chanx_left_out[18] ) , .p0 ( optlc_net_150 ) ) ; + .out ( chanx_left_out[18] ) , .p0 ( optlc_net_167 ) ) ; sb_2__0__mux_tree_tapbuf_size2_26 mux_left_track_39 ( .in ( { chany_top_in[11] , left_bottom_grid_pin_11_[0] } ) , .sram ( mux_tree_tapbuf_size2_26_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_99 , SYNOPSYS_UNCONNECTED_100 } ) , - .out ( chanx_left_out[19] ) , .p0 ( optlc_net_153 ) ) ; + .out ( chanx_left_out[19] ) , .p0 ( optlc_net_167 ) ) ; sb_2__0__mux_tree_tapbuf_size2_27 mux_left_track_41 ( .in ( { chany_top_in[10] , left_bottom_grid_pin_13_[0] } ) , .sram ( mux_tree_tapbuf_size2_27_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_101 , SYNOPSYS_UNCONNECTED_102 } ) , - .out ( chanx_left_out[20] ) , .p0 ( optlc_net_150 ) ) ; + .out ( chanx_left_out[20] ) , .p0 ( optlc_net_165 ) ) ; sb_2__0__mux_tree_tapbuf_size2_28 mux_left_track_43 ( .in ( { chany_top_in[9] , left_bottom_grid_pin_15_[0] } ) , .sram ( mux_tree_tapbuf_size2_28_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_103 , SYNOPSYS_UNCONNECTED_104 } ) , - .out ( chanx_left_out[21] ) , .p0 ( optlc_net_153 ) ) ; + .out ( chanx_left_out[21] ) , .p0 ( optlc_net_165 ) ) ; sb_2__0__mux_tree_tapbuf_size2_29 mux_left_track_47 ( .in ( { chany_top_in[7] , left_bottom_grid_pin_3_[0] } ) , .sram ( mux_tree_tapbuf_size2_29_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_105 , SYNOPSYS_UNCONNECTED_106 } ) , - .out ( chanx_left_out[23] ) , .p0 ( optlc_net_152 ) ) ; + .out ( chanx_left_out[23] ) , .p0 ( optlc_net_167 ) ) ; sb_2__0__mux_tree_tapbuf_size2_30 mux_left_track_49 ( .in ( { chany_top_in[6] , left_bottom_grid_pin_5_[0] } ) , .sram ( mux_tree_tapbuf_size2_30_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_107 , SYNOPSYS_UNCONNECTED_108 } ) , - .out ( chanx_left_out[24] ) , .p0 ( optlc_net_153 ) ) ; + .out ( chanx_left_out[24] ) , .p0 ( optlc_net_167 ) ) ; sb_2__0__mux_tree_tapbuf_size2_31 mux_left_track_51 ( .in ( { chany_top_in[5] , left_bottom_grid_pin_7_[0] } ) , .sram ( mux_tree_tapbuf_size2_31_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_109 , SYNOPSYS_UNCONNECTED_110 } ) , - .out ( chanx_left_out[25] ) , .p0 ( optlc_net_153 ) ) ; + .out ( chanx_left_out[25] ) , .p0 ( optlc_net_165 ) ) ; sb_2__0__mux_tree_tapbuf_size2_32 mux_left_track_53 ( .in ( { chany_top_in[4] , left_bottom_grid_pin_9_[0] } ) , .sram ( mux_tree_tapbuf_size2_32_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_111 , SYNOPSYS_UNCONNECTED_112 } ) , - .out ( chanx_left_out[26] ) , .p0 ( optlc_net_150 ) ) ; + .out ( chanx_left_out[26] ) , .p0 ( optlc_net_168 ) ) ; sb_2__0__mux_tree_tapbuf_size2_33 mux_left_track_55 ( .in ( { chany_top_in[3] , left_bottom_grid_pin_11_[0] } ) , .sram ( mux_tree_tapbuf_size2_33_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_113 , SYNOPSYS_UNCONNECTED_114 } ) , - .out ( chanx_left_out[27] ) , .p0 ( optlc_net_150 ) ) ; + .out ( chanx_left_out[27] ) , .p0 ( optlc_net_168 ) ) ; sb_2__0__mux_tree_tapbuf_size2_34 mux_left_track_57 ( .in ( { chany_top_in[2] , left_bottom_grid_pin_13_[0] } ) , .sram ( mux_tree_tapbuf_size2_34_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_115 , SYNOPSYS_UNCONNECTED_116 } ) , - .out ( chanx_left_out[28] ) , .p0 ( optlc_net_150 ) ) ; + .out ( chanx_left_out[28] ) , .p0 ( optlc_net_168 ) ) ; sb_2__0__mux_tree_tapbuf_size2 mux_left_track_59 ( .in ( { chany_top_in[1] , left_bottom_grid_pin_15_[0] } ) , .sram ( mux_tree_tapbuf_size2_35_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_117 , SYNOPSYS_UNCONNECTED_118 } ) , - .out ( chanx_left_out[29] ) , .p0 ( optlc_net_150 ) ) ; + .out ( chanx_left_out[29] ) , .p0 ( optlc_net_168 ) ) ; sb_2__0__mux_tree_tapbuf_size2_mem_0 mem_top_track_14 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , @@ -20453,12 +20431,12 @@ sb_2__0__mux_tree_tapbuf_size2_mem mem_left_track_59 ( .pReset ( pReset ) , .ccff_head ( mux_tree_tapbuf_size2_mem_34_ccff_tail ) , .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_35_sram ) ) ; sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_W_in ) , .X ( pReset[0] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_152 ( .LO ( SYNOPSYS_UNCONNECTED_119 ) , - .HI ( optlc_net_150 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_167 ( .LO ( SYNOPSYS_UNCONNECTED_119 ) , + .HI ( optlc_net_165 ) ) ; sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_N_in ) , .X ( prog_clk[0] ) ) ; -sky130_fd_sc_hd__buf_6 FTB_54__53 ( .A ( chanx_left_in[1] ) , - .X ( ropt_net_174 ) ) ; +sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chanx_left_in[1] ) , + .X ( chany_top_out[29] ) ) ; sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chanx_left_in[2] ) , .X ( chany_top_out[28] ) ) ; sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chanx_left_in[3] ) , @@ -20471,16 +20449,16 @@ sky130_fd_sc_hd__buf_6 FTB_59__58 ( .A ( chanx_left_in[14] ) , .X ( chany_top_out[16] ) ) ; sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( chanx_left_in[15] ) , .X ( chany_top_out[15] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_120 ( .A ( BUF_net_121 ) , .Y ( pReset_N_out ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_121 ( .A ( pReset_W_in ) , .Y ( BUF_net_121 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_154 ( .LO ( SYNOPSYS_UNCONNECTED_120 ) , - .HI ( optlc_net_151 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_156 ( .LO ( SYNOPSYS_UNCONNECTED_121 ) , - .HI ( optlc_net_152 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_158 ( .LO ( SYNOPSYS_UNCONNECTED_122 ) , - .HI ( optlc_net_153 ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1337 ( .A ( ropt_net_174 ) , - .X ( chany_top_out[29] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_125 ( .A ( BUF_net_126 ) , .Y ( pReset_N_out ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_126 ( .A ( pReset_W_in ) , .Y ( BUF_net_126 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_170 ( .LO ( SYNOPSYS_UNCONNECTED_120 ) , + .HI ( optlc_net_166 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_172 ( .LO ( SYNOPSYS_UNCONNECTED_121 ) , + .HI ( optlc_net_167 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_174 ( .LO ( SYNOPSYS_UNCONNECTED_122 ) , + .HI ( optlc_net_168 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_176 ( .LO ( SYNOPSYS_UNCONNECTED_123 ) , + .HI ( optlc_net_169 ) ) ; endmodule @@ -20682,7 +20660,7 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_138 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_136 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -20817,7 +20795,7 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_137 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_135 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -20841,11 +20819,12 @@ sb_1__2__const1_41 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_136 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .X ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_133 ( .A ( BUF_net_134 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_134 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_134 ) ) ; endmodule @@ -20871,9 +20850,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_134 ( .A ( BUF_net_135 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_135 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_135 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_131 ( .A ( BUF_net_132 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_132 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_132 ) ) ; endmodule @@ -20899,7 +20878,7 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_133 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_130 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -20921,13 +20900,14 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; sb_1__2__const1_38 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_128 ( .A ( BUF_net_129 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_129 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_129 ) ) ; endmodule @@ -20953,7 +20933,7 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_132 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_127 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -21044,13 +21024,12 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_130 ( .A ( BUF_net_131 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_131 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .Y ( BUF_net_131 ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_126 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .X ( out[0] ) ) ; endmodule @@ -21107,13 +21086,12 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_128 ( .A ( BUF_net_129 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_129 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .Y ( BUF_net_129 ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_125 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .X ( out[0] ) ) ; endmodule @@ -21143,9 +21121,9 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_126 ( .A ( BUF_net_127 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_127 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .Y ( BUF_net_127 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_123 ( .A ( BUF_net_124 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_124 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .Y ( BUF_net_124 ) ) ; endmodule @@ -21259,9 +21237,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_124 ( .A ( BUF_net_125 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_125 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .Y ( BUF_net_125 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_121 ( .A ( BUF_net_122 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_122 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .Y ( BUF_net_122 ) ) ; endmodule @@ -21303,9 +21281,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_122 ( .A ( BUF_net_123 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_123 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .Y ( BUF_net_123 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_119 ( .A ( BUF_net_120 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_120 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .Y ( BUF_net_120 ) ) ; endmodule @@ -21347,9 +21325,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_120 ( .A ( BUF_net_121 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_121 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .Y ( BUF_net_121 ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_118 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .X ( out[0] ) ) ; endmodule @@ -21391,9 +21368,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_118 ( .A ( BUF_net_119 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_119 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .Y ( BUF_net_119 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_116 ( .A ( BUF_net_117 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_117 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .Y ( BUF_net_117 ) ) ; endmodule @@ -21411,7 +21388,20 @@ sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__buf_6 FTB_29__28 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_29__28 ( .A ( copt_net_158 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1350 ( .A ( mem_out[2] ) , + .X ( copt_net_153 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1351 ( .A ( copt_net_153 ) , + .X ( copt_net_154 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1352 ( .A ( copt_net_154 ) , + .X ( copt_net_155 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1353 ( .A ( copt_net_155 ) , + .X ( copt_net_156 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1354 ( .A ( copt_net_156 ) , + .X ( copt_net_157 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1355 ( .A ( copt_net_157 ) , + .X ( copt_net_158 ) ) ; endmodule @@ -21560,6 +21550,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; sb_1__2__const1_28 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , @@ -21567,13 +21559,10 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_116 ( .A ( BUF_net_117 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_117 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .Y ( BUF_net_117 ) ) ; endmodule @@ -21638,12 +21627,13 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_115 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .X ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_114 ( .A ( BUF_net_115 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_115 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_115 ) ) ; endmodule @@ -21677,9 +21667,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_113 ( .A ( BUF_net_114 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_114 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .Y ( BUF_net_114 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_112 ( .A ( BUF_net_113 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_113 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_113 ) ) ; endmodule @@ -21713,9 +21703,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_111 ( .A ( BUF_net_112 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_112 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .Y ( BUF_net_112 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_144 ( .A ( BUF_net_145 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_145 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_145 ) ) ; endmodule @@ -21749,9 +21739,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_109 ( .A ( BUF_net_110 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_110 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .Y ( BUF_net_110 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_110 ( .A ( BUF_net_111 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_111 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_111 ) ) ; endmodule @@ -21781,13 +21771,12 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_107 ( .A ( BUF_net_108 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_108 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .Y ( BUF_net_108 ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_109 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .X ( out[0] ) ) ; endmodule @@ -21936,6 +21925,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; sb_1__2__const1_20 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -21946,13 +21937,10 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_105 ( .A ( BUF_net_106 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_106 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .Y ( BUF_net_106 ) ) ; endmodule @@ -21990,9 +21978,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_103 ( .A ( BUF_net_104 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_104 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .Y ( BUF_net_104 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_107 ( .A ( BUF_net_108 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_108 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .Y ( BUF_net_108 ) ) ; endmodule @@ -22026,13 +22014,12 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_101 ( .A ( BUF_net_102 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_102 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .Y ( BUF_net_102 ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_106 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .X ( out[0] ) ) ; endmodule @@ -22070,9 +22057,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_99 ( .A ( BUF_net_100 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_100 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .Y ( BUF_net_100 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_142 ( .A ( BUF_net_143 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_143 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .Y ( BUF_net_143 ) ) ; endmodule @@ -22205,9 +22192,9 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_97 ( .A ( BUF_net_98 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_98 ( .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .Y ( BUF_net_98 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_104 ( .A ( BUF_net_105 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_105 ( .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .Y ( BUF_net_105 ) ) ; endmodule @@ -22331,67 +22318,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; sb_1__2__const1_13 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module sb_1__2__const1_12 ( const1 ) ; -output [0:0] const1 ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sb_1__2__const1_12 const1_0_ ( - .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -22421,6 +22347,68 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_140 ( .A ( BUF_net_141 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_141 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .Y ( BUF_net_141 ) ) ; +endmodule + + +module sb_1__2__const1_12 ( const1 ) ; +output [0:0] const1 ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sb_1__2__const1_12 const1_0_ ( + .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_103 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .X ( out[0] ) ) ; endmodule @@ -22507,8 +22495,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; sb_1__2__const1_11 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , @@ -22532,6 +22518,8 @@ sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_102 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .X ( out[0] ) ) ; endmodule @@ -22789,37 +22777,25 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_185 ) , +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_187 ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1329 ( .A ( ccff_head[0] ) , - .X ( copt_net_146 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1330 ( .A ( copt_net_146 ) , - .X ( copt_net_147 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1331 ( .A ( copt_net_147 ) , - .X ( copt_net_148 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1332 ( .A ( copt_net_150 ) , - .X ( copt_net_149 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1333 ( .A ( copt_net_148 ) , - .X ( copt_net_150 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1334 ( .A ( copt_net_149 ) , - .X ( copt_net_151 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1360 ( .A ( copt_net_151 ) , - .X ( ropt_net_180 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1361 ( .A ( ropt_net_180 ) , - .X ( ropt_net_181 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1362 ( .A ( ropt_net_181 ) , +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1415 ( .A ( ccff_head[0] ) , .X ( ropt_net_182 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1363 ( .A ( ropt_net_182 ) , +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1416 ( .A ( ropt_net_182 ) , .X ( ropt_net_183 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1364 ( .A ( ropt_net_183 ) , +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1417 ( .A ( ropt_net_185 ) , .X ( ropt_net_184 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1365 ( .A ( ropt_net_184 ) , +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1418 ( .A ( ropt_net_183 ) , .X ( ropt_net_185 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1419 ( .A ( ropt_net_184 ) , + .X ( ropt_net_186 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1420 ( .A ( ropt_net_186 ) , + .X ( ropt_net_187 ) ) ; endmodule @@ -22865,9 +22841,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_95 ( .A ( BUF_net_96 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_96 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .Y ( BUF_net_96 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_100 ( .A ( BUF_net_101 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_101 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .Y ( BUF_net_101 ) ) ; endmodule @@ -22893,8 +22869,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; sb_1__2__const1_7 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -22911,10 +22885,13 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_98 ( .A ( BUF_net_99 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_99 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .Y ( BUF_net_99 ) ) ; endmodule @@ -22960,9 +22937,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_93 ( .A ( BUF_net_94 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_94 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .Y ( BUF_net_94 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_96 ( .A ( BUF_net_97 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_97 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .Y ( BUF_net_97 ) ) ; endmodule @@ -22988,8 +22965,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; sb_1__2__const1_5 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -23010,6 +22985,8 @@ sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_95 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .X ( out[0] ) ) ; endmodule @@ -23149,9 +23126,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_91 ( .A ( BUF_net_92 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_92 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .Y ( BUF_net_92 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_93 ( .A ( BUF_net_94 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_94 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .Y ( BUF_net_94 ) ) ; endmodule @@ -23177,8 +23154,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; sb_1__2__const1_1 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -23199,6 +23174,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_91 ( .A ( BUF_net_92 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_92 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .Y ( BUF_net_92 ) ) ; endmodule @@ -23224,8 +23202,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; sb_1__2__const1_0 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -23246,6 +23222,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_138 ( .A ( BUF_net_139 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_139 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .Y ( BUF_net_139 ) ) ; endmodule @@ -23310,7 +23289,7 @@ output pReset_W_out ; output pReset_E_out ; input prog_clk_0_S_in ; -wire ropt_net_167 ; +wire ropt_net_166 ; wire [0:0] prog_clk ; wire prog_clk_0 ; wire [0:3] mux_tree_tapbuf_size10_0_sram ; @@ -23420,7 +23399,7 @@ sb_1__2__mux_tree_tapbuf_size7_0 mux_right_track_0 ( .sram ( mux_tree_tapbuf_size7_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 } ) , - .out ( chanx_right_out[0] ) , .p0 ( optlc_net_145 ) ) ; + .out ( chanx_right_out[0] ) , .p0 ( optlc_net_150 ) ) ; sb_1__2__mux_tree_tapbuf_size7_1 mux_right_track_2 ( .in ( { right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_39_[0] , right_bottom_grid_pin_42_[0] , chany_bottom_in[8] , @@ -23428,7 +23407,7 @@ sb_1__2__mux_tree_tapbuf_size7_1 mux_right_track_2 ( .sram ( mux_tree_tapbuf_size7_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 } ) , - .out ( chanx_right_out[1] ) , .p0 ( optlc_net_145 ) ) ; + .out ( chanx_right_out[1] ) , .p0 ( optlc_net_150 ) ) ; sb_1__2__mux_tree_tapbuf_size7_2 mux_right_track_12 ( .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_41_[0] , chany_bottom_in[4] , chany_bottom_in[15] , chany_bottom_in[26] , @@ -23436,7 +23415,7 @@ sb_1__2__mux_tree_tapbuf_size7_2 mux_right_track_12 ( .sram ( mux_tree_tapbuf_size7_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 , SYNOPSYS_UNCONNECTED_9 } ) , - .out ( chanx_right_out[6] ) , .p0 ( optlc_net_142 ) ) ; + .out ( chanx_right_out[6] ) , .p0 ( optlc_net_148 ) ) ; sb_1__2__mux_tree_tapbuf_size7_3 mux_right_track_20 ( .in ( { right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_42_[0] , chany_bottom_in[3] , chany_bottom_in[14] , chany_bottom_in[25] , @@ -23444,7 +23423,7 @@ sb_1__2__mux_tree_tapbuf_size7_3 mux_right_track_20 ( .sram ( mux_tree_tapbuf_size7_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , - .out ( chanx_right_out[10] ) , .p0 ( optlc_net_143 ) ) ; + .out ( chanx_right_out[10] ) , .p0 ( optlc_net_148 ) ) ; sb_1__2__mux_tree_tapbuf_size7_4 mux_right_track_28 ( .in ( { right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_43_[0] , chany_bottom_in[2] , chany_bottom_in[13] , chany_bottom_in[24] , @@ -23452,7 +23431,7 @@ sb_1__2__mux_tree_tapbuf_size7_4 mux_right_track_28 ( .sram ( mux_tree_tapbuf_size7_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , SYNOPSYS_UNCONNECTED_15 } ) , - .out ( chanx_right_out[14] ) , .p0 ( optlc_net_143 ) ) ; + .out ( chanx_right_out[14] ) , .p0 ( optlc_net_148 ) ) ; sb_1__2__mux_tree_tapbuf_size7_5 mux_left_track_1 ( .in ( { chanx_left_out[4] , chanx_left_out[20] , chany_bottom_in[10] , chany_bottom_in[21] , left_top_grid_pin_1_[0] , @@ -23460,7 +23439,7 @@ sb_1__2__mux_tree_tapbuf_size7_5 mux_left_track_1 ( .sram ( mux_tree_tapbuf_size7_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_16 , SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 } ) , - .out ( chanx_left_out[0] ) , .p0 ( optlc_net_144 ) ) ; + .out ( chanx_left_out[0] ) , .p0 ( optlc_net_149 ) ) ; sb_1__2__mux_tree_tapbuf_size7_6 mux_left_track_13 ( .in ( { chanx_left_out[12] , chanx_left_out[27] , chany_bottom_in[4] , chany_bottom_in[15] , chany_bottom_in[26] , left_top_grid_pin_1_[0] , @@ -23468,7 +23447,7 @@ sb_1__2__mux_tree_tapbuf_size7_6 mux_left_track_13 ( .sram ( mux_tree_tapbuf_size7_6_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 , SYNOPSYS_UNCONNECTED_21 } ) , - .out ( chanx_left_out[6] ) , .p0 ( optlc_net_144 ) ) ; + .out ( chanx_left_out[6] ) , .p0 ( optlc_net_149 ) ) ; sb_1__2__mux_tree_tapbuf_size7_7 mux_left_track_21 ( .in ( { chanx_left_out[13] , chanx_left_out[28] , chany_bottom_in[5] , chany_bottom_in[16] , chany_bottom_in[27] , @@ -23476,7 +23455,7 @@ sb_1__2__mux_tree_tapbuf_size7_7 mux_left_track_21 ( .sram ( mux_tree_tapbuf_size7_7_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_22 , SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) , - .out ( chanx_left_out[10] ) , .p0 ( optlc_net_140 ) ) ; + .out ( chanx_left_out[10] ) , .p0 ( optlc_net_151 ) ) ; sb_1__2__mux_tree_tapbuf_size7 mux_left_track_29 ( .in ( { chanx_left_out[15] , chanx_left_out[29] , chany_bottom_in[6] , chany_bottom_in[17] , chany_bottom_in[28] , @@ -23484,7 +23463,7 @@ sb_1__2__mux_tree_tapbuf_size7 mux_left_track_29 ( .sram ( mux_tree_tapbuf_size7_8_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , SYNOPSYS_UNCONNECTED_27 } ) , - .out ( chanx_left_out[14] ) , .p0 ( optlc_net_140 ) ) ; + .out ( chanx_left_out[14] ) , .p0 ( optlc_net_151 ) ) ; sb_1__2__mux_tree_tapbuf_size7_mem_0 mem_right_track_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , @@ -23537,7 +23516,7 @@ sb_1__2__mux_tree_tapbuf_size8_0 mux_right_track_4 ( .sram ( mux_tree_tapbuf_size8_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_28 , SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 , SYNOPSYS_UNCONNECTED_31 } ) , - .out ( chanx_right_out[2] ) , .p0 ( optlc_net_143 ) ) ; + .out ( chanx_right_out[2] ) , .p0 ( optlc_net_151 ) ) ; sb_1__2__mux_tree_tapbuf_size8_1 mux_left_track_3 ( .in ( { chanx_left_out[7] , chanx_left_out[21] , chany_bottom_in[0] , chany_bottom_in[11] , chany_bottom_in[22] , @@ -23546,7 +23525,7 @@ sb_1__2__mux_tree_tapbuf_size8_1 mux_left_track_3 ( .sram ( mux_tree_tapbuf_size8_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_32 , SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 , SYNOPSYS_UNCONNECTED_35 } ) , - .out ( chanx_left_out[1] ) , .p0 ( optlc_net_144 ) ) ; + .out ( chanx_left_out[1] ) , .p0 ( optlc_net_146 ) ) ; sb_1__2__mux_tree_tapbuf_size8 mux_left_track_5 ( .in ( { chanx_left_out[8] , chanx_left_out[23] , chany_bottom_in[1] , chany_bottom_in[12] , chany_bottom_in[23] , @@ -23555,7 +23534,7 @@ sb_1__2__mux_tree_tapbuf_size8 mux_left_track_5 ( .sram ( mux_tree_tapbuf_size8_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_36 , SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 , SYNOPSYS_UNCONNECTED_39 } ) , - .out ( chanx_left_out[2] ) , .p0 ( optlc_net_140 ) ) ; + .out ( chanx_left_out[2] ) , .p0 ( optlc_net_146 ) ) ; sb_1__2__mux_tree_tapbuf_size8_mem_0 mem_right_track_4 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , @@ -23580,7 +23559,7 @@ sb_1__2__mux_tree_tapbuf_size10_0 mux_right_track_6 ( .sram ( mux_tree_tapbuf_size10_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_40 , SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 , SYNOPSYS_UNCONNECTED_43 } ) , - .out ( chanx_right_out[3] ) , .p0 ( optlc_net_143 ) ) ; + .out ( chanx_right_out[3] ) , .p0 ( optlc_net_148 ) ) ; sb_1__2__mux_tree_tapbuf_size10 mux_left_track_7 ( .in ( { chanx_left_out[9] , chanx_left_out[24] , chany_bottom_in[2] , chany_bottom_in[13] , chany_bottom_in[24] , left_top_grid_pin_1_[0] , @@ -23589,7 +23568,7 @@ sb_1__2__mux_tree_tapbuf_size10 mux_left_track_7 ( .sram ( mux_tree_tapbuf_size10_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_44 , SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 , SYNOPSYS_UNCONNECTED_47 } ) , - .out ( chanx_left_out[3] ) , .p0 ( optlc_net_140 ) ) ; + .out ( chanx_left_out[3] ) , .p0 ( optlc_net_146 ) ) ; sb_1__2__mux_tree_tapbuf_size10_mem_0 mem_right_track_6 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , @@ -23608,7 +23587,7 @@ sb_1__2__mux_tree_tapbuf_size9_0 mux_right_track_10 ( .sram ( mux_tree_tapbuf_size9_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_48 , SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 , SYNOPSYS_UNCONNECTED_51 } ) , - .out ( chanx_right_out[5] ) , .p0 ( optlc_net_143 ) ) ; + .out ( chanx_right_out[5] ) , .p0 ( optlc_net_148 ) ) ; sb_1__2__mux_tree_tapbuf_size9 mux_left_track_11 ( .in ( { chanx_left_out[11] , chanx_left_out[25] , chany_bottom_in[3] , chany_bottom_in[14] , chany_bottom_in[25] , @@ -23617,7 +23596,7 @@ sb_1__2__mux_tree_tapbuf_size9 mux_left_track_11 ( .sram ( mux_tree_tapbuf_size9_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_52 , SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 , SYNOPSYS_UNCONNECTED_55 } ) , - .out ( chanx_left_out[5] ) , .p0 ( optlc_net_144 ) ) ; + .out ( chanx_left_out[5] ) , .p0 ( optlc_net_149 ) ) ; sb_1__2__mux_tree_tapbuf_size9_mem_0 mem_right_track_10 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , @@ -23634,21 +23613,21 @@ sb_1__2__mux_tree_tapbuf_size5_0 mux_right_track_36 ( .sram ( mux_tree_tapbuf_size5_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_56 , SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 } ) , - .out ( chanx_right_out[18] ) , .p0 ( optlc_net_142 ) ) ; + .out ( chanx_right_out[18] ) , .p0 ( optlc_net_148 ) ) ; sb_1__2__mux_tree_tapbuf_size5_1 mux_right_track_44 ( .in ( { right_bottom_grid_pin_39_[0] , chany_bottom_in[0] , - chany_bottom_in[11] , chany_bottom_in[22] , chanx_right_out[17] } ) , + chany_bottom_in[11] , chany_bottom_in[22] , ropt_net_166 } ) , .sram ( mux_tree_tapbuf_size5_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 , SYNOPSYS_UNCONNECTED_61 } ) , - .out ( chanx_right_out[22] ) , .p0 ( optlc_net_142 ) ) ; + .out ( chanx_right_out[22] ) , .p0 ( optlc_net_147 ) ) ; sb_1__2__mux_tree_tapbuf_size5_2 mux_bottom_track_5 ( .in ( { chanx_left_out[8] , bottom_left_grid_pin_46_[0] , bottom_left_grid_pin_49_[0] , chanx_left_in[4] , chanx_right_out[8] } ) , .sram ( mux_tree_tapbuf_size5_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_62 , SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) , - .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_140 ) ) ; + .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_146 ) ) ; sb_1__2__mux_tree_tapbuf_size5_3 mux_bottom_track_11 ( .in ( { chanx_left_out[12] , bottom_left_grid_pin_46_[0] , bottom_left_grid_pin_49_[0] , chanx_right_out[12] , @@ -23656,14 +23635,14 @@ sb_1__2__mux_tree_tapbuf_size5_3 mux_bottom_track_11 ( .sram ( mux_tree_tapbuf_size5_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 , SYNOPSYS_UNCONNECTED_67 } ) , - .out ( chany_bottom_out[5] ) , .p0 ( optlc_net_141 ) ) ; + .out ( chany_bottom_out[5] ) , .p0 ( optlc_net_146 ) ) ; sb_1__2__mux_tree_tapbuf_size5 mux_left_track_37 ( .in ( { chanx_left_out[16] , chany_bottom_in[7] , chany_bottom_in[18] , chany_bottom_in[29] , left_bottom_grid_pin_38_[0] } ) , .sram ( mux_tree_tapbuf_size5_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_68 , SYNOPSYS_UNCONNECTED_69 , SYNOPSYS_UNCONNECTED_70 } ) , - .out ( chanx_left_out[18] ) , .p0 ( optlc_net_140 ) ) ; + .out ( chanx_left_out[18] ) , .p0 ( optlc_net_151 ) ) ; sb_1__2__mux_tree_tapbuf_size5_mem_0 mem_right_track_36 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , @@ -23695,56 +23674,56 @@ sb_1__2__mux_tree_tapbuf_size4_0 mux_right_track_52 ( .sram ( mux_tree_tapbuf_size4_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_71 , SYNOPSYS_UNCONNECTED_72 , SYNOPSYS_UNCONNECTED_73 } ) , - .out ( chanx_right_out[26] ) , .p0 ( optlc_net_142 ) ) ; + .out ( chanx_right_out[26] ) , .p0 ( optlc_net_147 ) ) ; sb_1__2__mux_tree_tapbuf_size4_1 mux_bottom_track_13 ( .in ( { chanx_left_out[13] , bottom_left_grid_pin_44_[0] , chanx_right_out[13] , chanx_left_in[17] } ) , .sram ( mux_tree_tapbuf_size4_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_74 , SYNOPSYS_UNCONNECTED_75 , SYNOPSYS_UNCONNECTED_76 } ) , - .out ( chany_bottom_out[6] ) , .p0 ( optlc_net_140 ) ) ; + .out ( chany_bottom_out[6] ) , .p0 ( optlc_net_146 ) ) ; sb_1__2__mux_tree_tapbuf_size4_2 mux_bottom_track_15 ( .in ( { chanx_left_out[15] , bottom_left_grid_pin_45_[0] , chanx_right_out[15] , chanx_left_in[21] } ) , .sram ( mux_tree_tapbuf_size4_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_77 , SYNOPSYS_UNCONNECTED_78 , SYNOPSYS_UNCONNECTED_79 } ) , - .out ( chany_bottom_out[7] ) , .p0 ( optlc_net_141 ) ) ; + .out ( chany_bottom_out[7] ) , .p0 ( optlc_net_146 ) ) ; sb_1__2__mux_tree_tapbuf_size4_3 mux_bottom_track_17 ( .in ( { chanx_left_out[16] , bottom_left_grid_pin_46_[0] , chanx_right_out[16] , chanx_left_in[25] } ) , .sram ( mux_tree_tapbuf_size4_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_80 , SYNOPSYS_UNCONNECTED_81 , SYNOPSYS_UNCONNECTED_82 } ) , - .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_141 ) ) ; + .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_146 ) ) ; sb_1__2__mux_tree_tapbuf_size4_4 mux_bottom_track_19 ( - .in ( { chanx_left_out[17] , bottom_left_grid_pin_47_[0] , - chanx_right_out[17] , chanx_left_in[29] } ) , + .in ( { chanx_left_out[17] , bottom_left_grid_pin_47_[0] , ropt_net_166 , + chanx_left_in[29] } ) , .sram ( mux_tree_tapbuf_size4_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_83 , SYNOPSYS_UNCONNECTED_84 , SYNOPSYS_UNCONNECTED_85 } ) , - .out ( chany_bottom_out[9] ) , .p0 ( optlc_net_141 ) ) ; + .out ( chany_bottom_out[9] ) , .p0 ( optlc_net_149 ) ) ; sb_1__2__mux_tree_tapbuf_size4_5 mux_bottom_track_37 ( .in ( { chanx_left_out[29] , chanx_right_in[29] , bottom_left_grid_pin_44_[0] , chanx_right_out[29] } ) , .sram ( mux_tree_tapbuf_size4_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_86 , SYNOPSYS_UNCONNECTED_87 , SYNOPSYS_UNCONNECTED_88 } ) , - .out ( chany_bottom_out[18] ) , .p0 ( optlc_net_142 ) ) ; + .out ( chany_bottom_out[18] ) , .p0 ( optlc_net_147 ) ) ; sb_1__2__mux_tree_tapbuf_size4_6 mux_left_track_45 ( .in ( { chanx_left_out[17] , chany_bottom_in[8] , chany_bottom_in[19] , left_bottom_grid_pin_39_[0] } ) , .sram ( mux_tree_tapbuf_size4_6_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_89 , SYNOPSYS_UNCONNECTED_90 , SYNOPSYS_UNCONNECTED_91 } ) , - .out ( chanx_left_out[22] ) , .p0 ( optlc_net_140 ) ) ; + .out ( chanx_left_out[22] ) , .p0 ( optlc_net_151 ) ) ; sb_1__2__mux_tree_tapbuf_size4 mux_left_track_53 ( .in ( { chanx_left_out[19] , chany_bottom_in[9] , chany_bottom_in[20] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_tree_tapbuf_size4_7_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_92 , SYNOPSYS_UNCONNECTED_93 , SYNOPSYS_UNCONNECTED_94 } ) , - .out ( chanx_left_out[26] ) , .p0 ( optlc_net_140 ) ) ; + .out ( chanx_left_out[26] ) , .p0 ( optlc_net_152 ) ) ; sb_1__2__mux_tree_tapbuf_size4_mem_0 mem_right_track_52 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , @@ -23791,7 +23770,7 @@ sb_1__2__mux_tree_tapbuf_size6_0 mux_bottom_track_1 ( .sram ( mux_tree_tapbuf_size6_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_95 , SYNOPSYS_UNCONNECTED_96 , SYNOPSYS_UNCONNECTED_97 } ) , - .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_141 ) ) ; + .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_146 ) ) ; sb_1__2__mux_tree_tapbuf_size6_1 mux_bottom_track_3 ( .in ( { chanx_left_out[7] , bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_48_[0] , bottom_left_grid_pin_51_[0] , @@ -23799,7 +23778,7 @@ sb_1__2__mux_tree_tapbuf_size6_1 mux_bottom_track_3 ( .sram ( mux_tree_tapbuf_size6_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_98 , SYNOPSYS_UNCONNECTED_99 , SYNOPSYS_UNCONNECTED_100 } ) , - .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_141 ) ) ; + .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_146 ) ) ; sb_1__2__mux_tree_tapbuf_size6_2 mux_bottom_track_7 ( .in ( { chanx_left_out[9] , bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_47_[0] , bottom_left_grid_pin_50_[0] , @@ -23807,7 +23786,7 @@ sb_1__2__mux_tree_tapbuf_size6_2 mux_bottom_track_7 ( .sram ( mux_tree_tapbuf_size6_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_101 , SYNOPSYS_UNCONNECTED_102 , SYNOPSYS_UNCONNECTED_103 } ) , - .out ( chany_bottom_out[3] ) , .p0 ( optlc_net_140 ) ) ; + .out ( chany_bottom_out[3] ) , .p0 ( optlc_net_152 ) ) ; sb_1__2__mux_tree_tapbuf_size6 mux_bottom_track_9 ( .in ( { chanx_left_out[11] , bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_48_[0] , bottom_left_grid_pin_51_[0] , @@ -23815,7 +23794,7 @@ sb_1__2__mux_tree_tapbuf_size6 mux_bottom_track_9 ( .sram ( mux_tree_tapbuf_size6_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_104 , SYNOPSYS_UNCONNECTED_105 , SYNOPSYS_UNCONNECTED_106 } ) , - .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_141 ) ) ; + .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_146 ) ) ; sb_1__2__mux_tree_tapbuf_size6_mem_0 mem_bottom_track_1 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , @@ -23841,25 +23820,25 @@ sb_1__2__mux_tree_tapbuf_size3_0 mux_bottom_track_21 ( chanx_right_out[19] } ) , .sram ( mux_tree_tapbuf_size3_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_107 , SYNOPSYS_UNCONNECTED_108 } ) , - .out ( chany_bottom_out[10] ) , .p0 ( optlc_net_144 ) ) ; + .out ( chany_bottom_out[10] ) , .p0 ( optlc_net_149 ) ) ; sb_1__2__mux_tree_tapbuf_size3_1 mux_bottom_track_23 ( .in ( { chanx_left_out[20] , bottom_left_grid_pin_49_[0] , chanx_right_out[20] } ) , .sram ( mux_tree_tapbuf_size3_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_109 , SYNOPSYS_UNCONNECTED_110 } ) , - .out ( chany_bottom_out[11] ) , .p0 ( optlc_net_144 ) ) ; + .out ( chany_bottom_out[11] ) , .p0 ( optlc_net_149 ) ) ; sb_1__2__mux_tree_tapbuf_size3_2 mux_bottom_track_25 ( .in ( { chanx_left_out[21] , bottom_left_grid_pin_50_[0] , chanx_right_out[21] } ) , .sram ( mux_tree_tapbuf_size3_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_111 , SYNOPSYS_UNCONNECTED_112 } ) , - .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_144 ) ) ; + .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_149 ) ) ; sb_1__2__mux_tree_tapbuf_size3 mux_bottom_track_27 ( .in ( { chanx_left_out[23] , bottom_left_grid_pin_51_[0] , chanx_right_out[23] } ) , .sram ( mux_tree_tapbuf_size3_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_113 , SYNOPSYS_UNCONNECTED_114 } ) , - .out ( chany_bottom_out[13] ) , .p0 ( optlc_net_144 ) ) ; + .out ( chany_bottom_out[13] ) , .p0 ( optlc_net_149 ) ) ; sb_1__2__mux_tree_tapbuf_size3_mem_0 mem_bottom_track_21 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_4_ccff_tail ) , @@ -23884,57 +23863,57 @@ sb_1__2__mux_tree_tapbuf_size2_0 mux_bottom_track_29 ( .in ( { chanx_left_out[24] , chanx_right_out[24] } ) , .sram ( mux_tree_tapbuf_size2_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_115 , SYNOPSYS_UNCONNECTED_116 } ) , - .out ( chany_bottom_out[14] ) , .p0 ( optlc_net_144 ) ) ; + .out ( chany_bottom_out[14] ) , .p0 ( optlc_net_149 ) ) ; sb_1__2__mux_tree_tapbuf_size2_1 mux_bottom_track_31 ( .in ( { chanx_left_out[25] , chanx_right_out[25] } ) , .sram ( mux_tree_tapbuf_size2_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_117 , SYNOPSYS_UNCONNECTED_118 } ) , - .out ( chany_bottom_out[15] ) , .p0 ( optlc_net_142 ) ) ; + .out ( chany_bottom_out[15] ) , .p0 ( optlc_net_149 ) ) ; sb_1__2__mux_tree_tapbuf_size2_2 mux_bottom_track_33 ( .in ( { chanx_left_out[27] , chanx_right_out[27] } ) , .sram ( mux_tree_tapbuf_size2_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_119 , SYNOPSYS_UNCONNECTED_120 } ) , - .out ( chany_bottom_out[16] ) , .p0 ( optlc_net_142 ) ) ; + .out ( chany_bottom_out[16] ) , .p0 ( optlc_net_147 ) ) ; sb_1__2__mux_tree_tapbuf_size2_3 mux_bottom_track_35 ( .in ( { chanx_left_out[28] , chanx_right_out[28] } ) , .sram ( mux_tree_tapbuf_size2_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_121 , SYNOPSYS_UNCONNECTED_122 } ) , - .out ( chany_bottom_out[17] ) , .p0 ( optlc_net_142 ) ) ; + .out ( chany_bottom_out[17] ) , .p0 ( optlc_net_147 ) ) ; sb_1__2__mux_tree_tapbuf_size2_4 mux_bottom_track_39 ( .in ( { chanx_right_in[25] , bottom_left_grid_pin_45_[0] } ) , .sram ( mux_tree_tapbuf_size2_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_123 , SYNOPSYS_UNCONNECTED_124 } ) , - .out ( chany_bottom_out[19] ) , .p0 ( optlc_net_142 ) ) ; + .out ( chany_bottom_out[19] ) , .p0 ( optlc_net_147 ) ) ; sb_1__2__mux_tree_tapbuf_size2_5 mux_bottom_track_41 ( .in ( { chanx_right_in[21] , bottom_left_grid_pin_46_[0] } ) , .sram ( mux_tree_tapbuf_size2_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_125 , SYNOPSYS_UNCONNECTED_126 } ) , - .out ( chany_bottom_out[20] ) , .p0 ( optlc_net_142 ) ) ; + .out ( chany_bottom_out[20] ) , .p0 ( optlc_net_147 ) ) ; sb_1__2__mux_tree_tapbuf_size2_6 mux_bottom_track_43 ( .in ( { chanx_right_in[17] , bottom_left_grid_pin_47_[0] } ) , .sram ( mux_tree_tapbuf_size2_6_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_127 , SYNOPSYS_UNCONNECTED_128 } ) , - .out ( chany_bottom_out[21] ) , .p0 ( optlc_net_142 ) ) ; + .out ( chany_bottom_out[21] ) , .p0 ( optlc_net_147 ) ) ; sb_1__2__mux_tree_tapbuf_size2_7 mux_bottom_track_45 ( .in ( { chanx_right_in[13] , bottom_left_grid_pin_48_[0] } ) , .sram ( mux_tree_tapbuf_size2_7_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_129 , SYNOPSYS_UNCONNECTED_130 } ) , - .out ( chany_bottom_out[22] ) , .p0 ( optlc_net_142 ) ) ; + .out ( chany_bottom_out[22] ) , .p0 ( optlc_net_147 ) ) ; sb_1__2__mux_tree_tapbuf_size2_8 mux_bottom_track_47 ( .in ( { chanx_right_in[9] , bottom_left_grid_pin_49_[0] } ) , .sram ( mux_tree_tapbuf_size2_8_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_131 , SYNOPSYS_UNCONNECTED_132 } ) , - .out ( chany_bottom_out[23] ) , .p0 ( optlc_net_144 ) ) ; + .out ( chany_bottom_out[23] ) , .p0 ( optlc_net_149 ) ) ; sb_1__2__mux_tree_tapbuf_size2_9 mux_bottom_track_49 ( .in ( { chanx_right_in[5] , bottom_left_grid_pin_50_[0] } ) , .sram ( mux_tree_tapbuf_size2_9_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_133 , SYNOPSYS_UNCONNECTED_134 } ) , - .out ( chany_bottom_out[24] ) , .p0 ( optlc_net_144 ) ) ; + .out ( chany_bottom_out[24] ) , .p0 ( optlc_net_149 ) ) ; sb_1__2__mux_tree_tapbuf_size2 mux_bottom_track_51 ( .in ( { chanx_right_in[4] , bottom_left_grid_pin_51_[0] } ) , .sram ( mux_tree_tapbuf_size2_10_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_135 , SYNOPSYS_UNCONNECTED_136 } ) , - .out ( chany_bottom_out[25] ) , .p0 ( optlc_net_144 ) ) ; + .out ( chany_bottom_out[25] ) , .p0 ( optlc_net_149 ) ) ; sb_1__2__mux_tree_tapbuf_size2_mem_0 mem_bottom_track_29 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , @@ -23992,10 +23971,10 @@ sb_1__2__mux_tree_tapbuf_size2_mem mem_bottom_track_51 ( .pReset ( pReset ) , .mem_out ( mux_tree_tapbuf_size2_10_sram ) ) ; sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_E_in ) , .X ( pReset[0] ) ) ; sky130_fd_sc_hd__buf_1 pReset_W_FTB01 ( .A ( pReset_E_in ) , - .X ( net_net_139 ) ) ; + .X ( net_net_137 ) ) ; sky130_fd_sc_hd__buf_1 pReset_E_FTB01 ( .A ( pReset_E_in ) , .X ( aps_rename_505_ ) ) ; -sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_S_in ) , +sky130_fd_sc_hd__buf_16 prog_clk_0_FTB00 ( .A ( prog_clk_0_S_in ) , .X ( prog_clk[0] ) ) ; sky130_fd_sc_hd__buf_8 FTB_49__48 ( .A ( chanx_right_in[0] ) , .X ( chany_bottom_out[28] ) ) ; @@ -24041,8 +24020,8 @@ sky130_fd_sc_hd__buf_8 FTB_69__68 ( .A ( chanx_right_in[27] ) , .X ( chanx_left_out[28] ) ) ; sky130_fd_sc_hd__buf_8 FTB_70__69 ( .A ( chanx_right_in[28] ) , .X ( chanx_left_out[29] ) ) ; -sky130_fd_sc_hd__buf_6 FTB_71__70 ( .A ( chanx_left_in[0] ) , - .X ( ropt_net_167 ) ) ; +sky130_fd_sc_hd__buf_8 FTB_71__70 ( .A ( chanx_left_in[0] ) , + .X ( chany_bottom_out[29] ) ) ; sky130_fd_sc_hd__buf_8 FTB_72__71 ( .A ( chanx_left_in[3] ) , .X ( chanx_right_out[4] ) ) ; sky130_fd_sc_hd__buf_8 FTB_73__72 ( .A ( chanx_left_in[6] ) , @@ -24061,8 +24040,8 @@ sky130_fd_sc_hd__buf_8 FTB_79__78 ( .A ( chanx_left_in[14] ) , .X ( chanx_right_out[15] ) ) ; sky130_fd_sc_hd__buf_8 FTB_80__79 ( .A ( chanx_left_in[15] ) , .X ( chanx_right_out[16] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_81__80 ( .A ( chanx_left_in[16] ) , - .X ( chanx_right_out[17] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_81__80 ( .A ( chanx_left_in[16] ) , + .X ( ropt_net_166 ) ) ; sky130_fd_sc_hd__buf_8 FTB_82__81 ( .A ( chanx_left_in[18] ) , .X ( chanx_right_out[19] ) ) ; sky130_fd_sc_hd__buf_8 FTB_83__82 ( .A ( chanx_left_in[19] ) , @@ -24082,24 +24061,26 @@ sky130_fd_sc_hd__buf_8 FTB_89__88 ( .A ( chanx_left_in[27] ) , sky130_fd_sc_hd__buf_8 FTB_90__89 ( .A ( chanx_left_in[28] ) , .X ( chanx_right_out[29] ) ) ; sky130_fd_sc_hd__buf_8 FTB_91__90 ( .A ( SC_IN_BOT ) , .X ( SC_OUT_BOT ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_139 ( .A ( net_net_139 ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_137 ( .A ( net_net_137 ) , .X ( pReset_W_out ) ) ; -sky130_fd_sc_hd__conb_1 optlc_142 ( .LO ( SYNOPSYS_UNCONNECTED_137 ) , - .HI ( optlc_net_140 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_144 ( .LO ( SYNOPSYS_UNCONNECTED_138 ) , - .HI ( optlc_net_141 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_146 ( .LO ( SYNOPSYS_UNCONNECTED_139 ) , - .HI ( optlc_net_142 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_148 ( .LO ( SYNOPSYS_UNCONNECTED_140 ) , - .HI ( optlc_net_143 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_150 ( .LO ( SYNOPSYS_UNCONNECTED_141 ) , - .HI ( optlc_net_144 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_152 ( .LO ( SYNOPSYS_UNCONNECTED_142 ) , - .HI ( optlc_net_145 ) ) ; -sky130_fd_sc_hd__buf_6 ZBUF_6_f_inst_153 ( .A ( aps_rename_505_ ) , +sky130_fd_sc_hd__conb_1 optlc_148 ( .LO ( SYNOPSYS_UNCONNECTED_137 ) , + .HI ( optlc_net_146 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_150 ( .LO ( SYNOPSYS_UNCONNECTED_138 ) , + .HI ( optlc_net_147 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_152 ( .LO ( SYNOPSYS_UNCONNECTED_139 ) , + .HI ( optlc_net_148 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_155 ( .LO ( SYNOPSYS_UNCONNECTED_140 ) , + .HI ( optlc_net_149 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_157 ( .LO ( SYNOPSYS_UNCONNECTED_141 ) , + .HI ( optlc_net_150 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_159 ( .LO ( SYNOPSYS_UNCONNECTED_142 ) , + .HI ( optlc_net_151 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_161 ( .LO ( SYNOPSYS_UNCONNECTED_143 ) , + .HI ( optlc_net_152 ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_6_f_inst_162 ( .A ( aps_rename_505_ ) , .X ( pReset_E_out ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1349 ( .A ( ropt_net_167 ) , - .X ( chany_bottom_out[29] ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1399 ( .A ( ropt_net_166 ) , + .X ( chanx_right_out[17] ) ) ; endmodule @@ -24117,7 +24098,7 @@ sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__buf_1 FTB_44__43 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_44__43 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -24638,12 +24619,9 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; sb_1__1__const1_36 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -24659,8 +24637,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) ) ; endmodule @@ -26105,7 +26082,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; sb_1__1__const1_19 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; @@ -26224,7 +26201,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; sb_1__1__const1_17 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; @@ -26949,20 +26926,26 @@ sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1366 ( .A ( copt_net_175 ) , +sky130_fd_sc_hd__buf_1 ropt_h_inst_1366 ( .A ( copt_net_175 ) , .X ( ropt_net_178 ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1360 ( .A ( copt_net_174 ) , .X ( copt_net_172 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1361 ( .A ( copt_net_172 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1361 ( .A ( ropt_net_181 ) , .X ( copt_net_173 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1362 ( .A ( ropt_net_179 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1362 ( .A ( ccff_head[0] ) , .X ( copt_net_174 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1363 ( .A ( copt_net_173 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1363 ( .A ( ropt_net_183 ) , .X ( copt_net_175 ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1364 ( .A ( ropt_net_178 ) , .X ( copt_net_176 ) ) ; -sky130_fd_sc_hd__buf_1 ropt_h_inst_1367 ( .A ( ccff_head[0] ) , +sky130_fd_sc_hd__buf_4 ropt_h_inst_1371 ( .A ( ropt_net_180 ) , + .X ( ropt_net_183 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1367 ( .A ( copt_net_173 ) , .X ( ropt_net_179 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 ropt_h_inst_1368 ( .A ( ropt_net_179 ) , + .X ( ropt_net_180 ) ) ; +sky130_fd_sc_hd__buf_1 ropt_h_inst_1369 ( .A ( copt_net_172 ) , + .X ( ropt_net_181 ) ) ; endmodule @@ -27055,7 +27038,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; sb_1__1__const1_6 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; @@ -27927,8 +27910,7 @@ sb_1__1__mux_tree_tapbuf_size10_9 mux_left_track_5 ( .sram ( mux_tree_tapbuf_size10_9_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_69 , SYNOPSYS_UNCONNECTED_70 , SYNOPSYS_UNCONNECTED_71 , SYNOPSYS_UNCONNECTED_72 } ) , - .out ( { ropt_net_180 } ) , - .p0 ( optlc_net_159 ) ) ; + .out ( chanx_left_out[2] ) , .p0 ( optlc_net_159 ) ) ; sb_1__1__mux_tree_tapbuf_size10_10 mux_left_track_13 ( .in ( { chany_bottom_out[12] , chany_top_in[13] , chany_bottom_out[27] , chanx_left_out[12] , chanx_left_out[27] , chany_bottom_in[5] , @@ -28076,7 +28058,8 @@ sb_1__1__mux_tree_tapbuf_size12_6 mux_left_track_7 ( .sram ( mux_tree_tapbuf_size12_6_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_105 , SYNOPSYS_UNCONNECTED_106 , SYNOPSYS_UNCONNECTED_107 , SYNOPSYS_UNCONNECTED_108 } ) , - .out ( chanx_left_out[3] ) , .p0 ( optlc_net_159 ) ) ; + .out ( { ropt_net_182 } ) , + .p0 ( optlc_net_159 ) ) ; sb_1__1__mux_tree_tapbuf_size12 mux_left_track_11 ( .in ( { chany_bottom_out[11] , chany_top_in[17] , chany_bottom_out[25] , chanx_left_out[11] , chanx_left_out[25] , chany_bottom_in[4] , @@ -28221,7 +28204,8 @@ sb_1__1__mux_tree_tapbuf_size6_4 mux_right_track_44 ( .sram ( mux_tree_tapbuf_size6_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_141 , SYNOPSYS_UNCONNECTED_142 , SYNOPSYS_UNCONNECTED_143 } ) , - .out ( chanx_right_out[22] ) , .p0 ( optlc_net_158 ) ) ; + .out ( { ZBUF_6_f_0 } ) , + .p0 ( optlc_net_158 ) ) ; sb_1__1__mux_tree_tapbuf_size6_5 mux_right_track_52 ( .in ( { chany_bottom_out[19] , chany_top_in[25] , right_bottom_grid_pin_41_[0] , chany_top_out[19] , @@ -28334,9 +28318,8 @@ sb_1__1__mux_tree_tapbuf_size6_mem_10 mem_left_track_45 ( .pReset ( pReset ) , .mem_out ( mux_tree_tapbuf_size6_10_sram ) ) ; sb_1__1__mux_tree_tapbuf_size6_mem mem_left_track_53 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size6_mem_10_ccff_tail ) , - .ccff_tail ( { copt_net_170 } ) , - .mem_out ( mux_tree_tapbuf_size6_11_sram ) ) ; + .ccff_head ( mux_tree_tapbuf_size6_mem_10_ccff_tail ) , + .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size6_11_sram ) ) ; sky130_fd_sc_hd__buf_4 Test_en_N_FTB01 ( .A ( Test_en_S_in ) , .X ( Test_en_N_out ) ) ; sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_E_in ) , .X ( pReset[0] ) ) ; @@ -28516,10 +28499,10 @@ sky130_fd_sc_hd__conb_1 optlc_166 ( .LO ( SYNOPSYS_UNCONNECTED_169 ) , .HI ( optlc_net_160 ) ) ; sky130_fd_sc_hd__conb_1 optlc_168 ( .LO ( SYNOPSYS_UNCONNECTED_170 ) , .HI ( optlc_net_161 ) ) ; -sky130_fd_sc_hd__buf_8 copt_h_inst_1358 ( .A ( copt_net_170 ) , - .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__buf_6 ropt_mt_inst_1368 ( .A ( ropt_net_180 ) , - .X ( chanx_left_out[2] ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_6_f_inst_1350 ( .A ( ZBUF_6_f_0 ) , + .X ( chanx_right_out[22] ) ) ; +sky130_fd_sc_hd__buf_4 ropt_mt_inst_1370 ( .A ( ropt_net_182 ) , + .X ( chanx_left_out[3] ) ) ; endmodule @@ -28633,9 +28616,9 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_144 ( .A ( BUF_net_145 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_145 ( .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .Y ( BUF_net_145 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_147 ( .A ( BUF_net_148 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_148 ( .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .Y ( BUF_net_148 ) ) ; endmodule @@ -28663,6 +28646,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; sb_1__0__const1_46 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -28685,13 +28670,10 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( +sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_130 ( .A ( BUF_net_131 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_131 ( .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .Y ( BUF_net_131 ) ) ; endmodule @@ -28745,9 +28727,9 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_128 ( .A ( BUF_net_129 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_129 ( .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .Y ( BUF_net_129 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_135 ( .A ( BUF_net_136 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_136 ( .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .Y ( BUF_net_136 ) ) ; endmodule @@ -28825,9 +28807,9 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_126 ( .A ( BUF_net_127 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_127 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , - .Y ( BUF_net_127 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_133 ( .A ( BUF_net_134 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_134 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .Y ( BUF_net_134 ) ) ; endmodule @@ -28988,9 +28970,9 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_124 ( .A ( BUF_net_125 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_125 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , - .Y ( BUF_net_125 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_131 ( .A ( BUF_net_132 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_132 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .Y ( BUF_net_132 ) ) ; endmodule @@ -29017,8 +28999,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; sb_1__0__const1_41 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , @@ -29038,10 +29018,13 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ ( +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_129 ( .A ( BUF_net_130 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_130 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .Y ( BUF_net_130 ) ) ; endmodule @@ -29243,9 +29226,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_122 ( .A ( BUF_net_123 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_123 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_123 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_127 ( .A ( BUF_net_128 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_128 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_128 ) ) ; endmodule @@ -29271,7 +29254,7 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_121 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_126 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -29298,9 +29281,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_119 ( .A ( BUF_net_120 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_120 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_120 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_124 ( .A ( BUF_net_125 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_125 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_125 ) ) ; endmodule @@ -29353,9 +29336,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_117 ( .A ( BUF_net_118 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_118 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_118 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_122 ( .A ( BUF_net_123 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_123 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_123 ) ) ; endmodule @@ -29381,9 +29364,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_115 ( .A ( BUF_net_116 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_116 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_116 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_120 ( .A ( BUF_net_121 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_121 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_121 ) ) ; endmodule @@ -29409,9 +29392,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_113 ( .A ( BUF_net_114 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_114 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_114 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_118 ( .A ( BUF_net_119 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_119 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_119 ) ) ; endmodule @@ -29432,13 +29415,14 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; sb_1__0__const1_33 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_116 ( .A ( BUF_net_117 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_117 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_117 ) ) ; endmodule @@ -29464,9 +29448,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_111 ( .A ( BUF_net_112 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_112 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_112 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_114 ( .A ( BUF_net_115 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_115 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_115 ) ) ; endmodule @@ -29630,9 +29614,9 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_109 ( .A ( BUF_net_110 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_110 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .Y ( BUF_net_110 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_112 ( .A ( BUF_net_113 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_113 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .Y ( BUF_net_113 ) ) ; endmodule @@ -29662,9 +29646,9 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_107 ( .A ( BUF_net_108 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_108 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .Y ( BUF_net_108 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_110 ( .A ( BUF_net_111 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_111 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .Y ( BUF_net_111 ) ) ; endmodule @@ -29694,9 +29678,9 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_105 ( .A ( BUF_net_106 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_106 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .Y ( BUF_net_106 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_108 ( .A ( BUF_net_109 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_109 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .Y ( BUF_net_109 ) ) ; endmodule @@ -29924,6 +29908,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; sb_1__0__const1_23 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , @@ -29935,8 +29921,6 @@ sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_104 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .X ( out[0] ) ) ; endmodule @@ -29994,8 +29978,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; sb_1__0__const1_21 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , @@ -30007,6 +29989,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_106 ( .A ( BUF_net_107 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_107 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_107 ) ) ; endmodule @@ -30040,9 +30025,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_102 ( .A ( BUF_net_103 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_103 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .Y ( BUF_net_103 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_104 ( .A ( BUF_net_105 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_105 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_105 ) ) ; endmodule @@ -30262,9 +30247,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_100 ( .A ( BUF_net_101 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_101 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .Y ( BUF_net_101 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_102 ( .A ( BUF_net_103 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_103 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .Y ( BUF_net_103 ) ) ; endmodule @@ -30288,6 +30273,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; sb_1__0__const1_16 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -30302,8 +30289,6 @@ sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_99 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .X ( out[0] ) ) ; endmodule @@ -30341,7 +30326,7 @@ sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_98 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_101 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -30380,9 +30365,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_96 ( .A ( BUF_net_97 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_97 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .Y ( BUF_net_97 ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_100 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .X ( out[0] ) ) ; endmodule @@ -30778,35 +30762,35 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_185 ) , +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_193 ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1330 ( .A ( copt_net_155 ) , - .X ( copt_net_152 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1331 ( .A ( copt_net_157 ) , - .X ( copt_net_153 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1332 ( .A ( copt_net_152 ) , - .X ( copt_net_154 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1333 ( .A ( ccff_head[0] ) , - .X ( copt_net_155 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1334 ( .A ( copt_net_153 ) , - .X ( copt_net_156 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1335 ( .A ( copt_net_154 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1340 ( .A ( copt_net_159 ) , .X ( copt_net_157 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1357 ( .A ( copt_net_156 ) , - .X ( ropt_net_181 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1358 ( .A ( ropt_net_181 ) , - .X ( ropt_net_182 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1359 ( .A ( ropt_net_184 ) , - .X ( ropt_net_183 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1360 ( .A ( ropt_net_182 ) , - .X ( ropt_net_184 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1361 ( .A ( ropt_net_183 ) , - .X ( ropt_net_185 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1341 ( .A ( copt_net_157 ) , + .X ( copt_net_158 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1342 ( .A ( copt_net_160 ) , + .X ( copt_net_159 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1343 ( .A ( ccff_head[0] ) , + .X ( copt_net_160 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1344 ( .A ( copt_net_158 ) , + .X ( copt_net_161 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1345 ( .A ( copt_net_161 ) , + .X ( copt_net_162 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1371 ( .A ( copt_net_162 ) , + .X ( ropt_net_190 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1372 ( .A ( ropt_net_192 ) , + .X ( ropt_net_191 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1373 ( .A ( ropt_net_190 ) , + .X ( ropt_net_192 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1374 ( .A ( ropt_net_194 ) , + .X ( ropt_net_193 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1375 ( .A ( ropt_net_191 ) , + .X ( ropt_net_194 ) ) ; endmodule @@ -30899,7 +30883,7 @@ sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_95 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_99 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -31040,9 +31024,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_93 ( .A ( BUF_net_94 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_94 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .Y ( BUF_net_94 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_97 ( .A ( BUF_net_98 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_98 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .Y ( BUF_net_98 ) ) ; endmodule @@ -31182,9 +31166,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_142 ( .A ( BUF_net_143 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_143 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .Y ( BUF_net_143 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_95 ( .A ( BUF_net_96 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_96 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .Y ( BUF_net_96 ) ) ; endmodule @@ -31210,8 +31194,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; sb_1__0__const1_1 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -31228,10 +31210,13 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_93 ( .A ( BUF_net_94 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_94 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .Y ( BUF_net_94 ) ) ; endmodule @@ -31353,7 +31338,7 @@ output prog_clk_3_N_out ; input clk_3_S_in ; output clk_3_N_out ; -wire ropt_net_170 ; +wire ropt_net_176 ; wire [0:0] prog_clk ; wire prog_clk_0 ; wire [0:3] mux_tree_tapbuf_size10_0_sram ; @@ -31463,7 +31448,7 @@ sb_1__0__mux_tree_tapbuf_size7_0 mux_top_track_0 ( .sram ( mux_tree_tapbuf_size7_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 } ) , - .out ( chany_top_out[0] ) , .p0 ( optlc_net_146 ) ) ; + .out ( chany_top_out[0] ) , .p0 ( optlc_net_154 ) ) ; sb_1__0__mux_tree_tapbuf_size7_1 mux_right_track_0 ( .in ( { chany_top_in[10] , chany_top_in[21] , right_bottom_grid_pin_1_[0] , right_bottom_grid_pin_7_[0] , @@ -31472,7 +31457,7 @@ sb_1__0__mux_tree_tapbuf_size7_1 mux_right_track_0 ( .sram ( mux_tree_tapbuf_size7_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 } ) , - .out ( chanx_right_out[0] ) , .p0 ( optlc_net_151 ) ) ; + .out ( chanx_right_out[0] ) , .p0 ( optlc_net_154 ) ) ; sb_1__0__mux_tree_tapbuf_size7_2 mux_right_track_12 ( .in ( { chany_top_in[4] , chany_top_in[15] , chany_top_in[26] , right_bottom_grid_pin_1_[0] , right_bottom_grid_pin_13_[0] , @@ -31480,7 +31465,7 @@ sb_1__0__mux_tree_tapbuf_size7_2 mux_right_track_12 ( .sram ( mux_tree_tapbuf_size7_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 , SYNOPSYS_UNCONNECTED_9 } ) , - .out ( chanx_right_out[6] ) , .p0 ( optlc_net_151 ) ) ; + .out ( chanx_right_out[6] ) , .p0 ( optlc_net_154 ) ) ; sb_1__0__mux_tree_tapbuf_size7_3 mux_right_track_20 ( .in ( { chany_top_in[5] , chany_top_in[16] , chany_top_in[27] , right_bottom_grid_pin_3_[0] , right_bottom_grid_pin_15_[0] , @@ -31488,7 +31473,7 @@ sb_1__0__mux_tree_tapbuf_size7_3 mux_right_track_20 ( .sram ( mux_tree_tapbuf_size7_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , - .out ( chanx_right_out[10] ) , .p0 ( optlc_net_147 ) ) ; + .out ( chanx_right_out[10] ) , .p0 ( optlc_net_150 ) ) ; sb_1__0__mux_tree_tapbuf_size7_4 mux_right_track_28 ( .in ( { chany_top_in[6] , chany_top_in[17] , chany_top_in[28] , right_bottom_grid_pin_5_[0] , right_bottom_grid_pin_17_[0] , @@ -31496,7 +31481,7 @@ sb_1__0__mux_tree_tapbuf_size7_4 mux_right_track_28 ( .sram ( mux_tree_tapbuf_size7_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , SYNOPSYS_UNCONNECTED_15 } ) , - .out ( chanx_right_out[14] ) , .p0 ( optlc_net_147 ) ) ; + .out ( chanx_right_out[14] ) , .p0 ( optlc_net_150 ) ) ; sb_1__0__mux_tree_tapbuf_size7_5 mux_left_track_3 ( .in ( { chany_top_in[10] , chany_top_in[21] , chanx_left_out[7] , chanx_left_out[21] , left_bottom_grid_pin_3_[0] , @@ -31504,7 +31489,7 @@ sb_1__0__mux_tree_tapbuf_size7_5 mux_left_track_3 ( .sram ( mux_tree_tapbuf_size7_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_16 , SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 } ) , - .out ( chanx_left_out[1] ) , .p0 ( optlc_net_146 ) ) ; + .out ( chanx_left_out[1] ) , .p0 ( optlc_net_151 ) ) ; sb_1__0__mux_tree_tapbuf_size7_6 mux_left_track_5 ( .in ( { chany_top_in[9] , chany_top_in[20] , chanx_left_out[8] , chanx_left_out[23] , left_bottom_grid_pin_5_[0] , @@ -31512,7 +31497,7 @@ sb_1__0__mux_tree_tapbuf_size7_6 mux_left_track_5 ( .sram ( mux_tree_tapbuf_size7_6_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 , SYNOPSYS_UNCONNECTED_21 } ) , - .out ( chanx_left_out[2] ) , .p0 ( optlc_net_148 ) ) ; + .out ( chanx_left_out[2] ) , .p0 ( optlc_net_149 ) ) ; sb_1__0__mux_tree_tapbuf_size7_7 mux_left_track_13 ( .in ( { chany_top_in[6] , chany_top_in[17] , chany_top_in[28] , chanx_left_out[12] , chanx_left_out[27] , left_bottom_grid_pin_1_[0] , @@ -31520,7 +31505,7 @@ sb_1__0__mux_tree_tapbuf_size7_7 mux_left_track_13 ( .sram ( mux_tree_tapbuf_size7_7_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_22 , SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) , - .out ( chanx_left_out[6] ) , .p0 ( optlc_net_148 ) ) ; + .out ( chanx_left_out[6] ) , .p0 ( optlc_net_149 ) ) ; sb_1__0__mux_tree_tapbuf_size7_8 mux_left_track_21 ( .in ( { chany_top_in[5] , chany_top_in[16] , chany_top_in[27] , chanx_left_out[13] , chanx_left_out[28] , left_bottom_grid_pin_3_[0] , @@ -31528,7 +31513,7 @@ sb_1__0__mux_tree_tapbuf_size7_8 mux_left_track_21 ( .sram ( mux_tree_tapbuf_size7_8_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , SYNOPSYS_UNCONNECTED_27 } ) , - .out ( chanx_left_out[10] ) , .p0 ( optlc_net_146 ) ) ; + .out ( chanx_left_out[10] ) , .p0 ( optlc_net_149 ) ) ; sb_1__0__mux_tree_tapbuf_size7 mux_left_track_29 ( .in ( { chany_top_in[4] , chany_top_in[15] , chany_top_in[26] , chanx_left_out[15] , chanx_left_out[29] , left_bottom_grid_pin_5_[0] , @@ -31536,7 +31521,7 @@ sb_1__0__mux_tree_tapbuf_size7 mux_left_track_29 ( .sram ( mux_tree_tapbuf_size7_9_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_28 , SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 } ) , - .out ( chanx_left_out[14] ) , .p0 ( optlc_net_146 ) ) ; + .out ( chanx_left_out[14] ) , .p0 ( optlc_net_149 ) ) ; sb_1__0__mux_tree_tapbuf_size7_mem_0 mem_top_track_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , @@ -31593,7 +31578,7 @@ sb_1__0__mux_tree_tapbuf_size6_0 mux_top_track_2 ( .sram ( mux_tree_tapbuf_size6_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 , SYNOPSYS_UNCONNECTED_33 } ) , - .out ( chany_top_out[1] ) , .p0 ( optlc_net_151 ) ) ; + .out ( chany_top_out[1] ) , .p0 ( optlc_net_152 ) ) ; sb_1__0__mux_tree_tapbuf_size6_1 mux_top_track_6 ( .in ( { top_left_grid_pin_44_[0] , top_left_grid_pin_47_[0] , top_left_grid_pin_50_[0] , chanx_right_in[5] , chanx_left_out[9] , @@ -31601,7 +31586,7 @@ sb_1__0__mux_tree_tapbuf_size6_1 mux_top_track_6 ( .sram ( mux_tree_tapbuf_size6_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_34 , SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) , - .out ( chany_top_out[3] ) , .p0 ( optlc_net_151 ) ) ; + .out ( chany_top_out[3] ) , .p0 ( optlc_net_152 ) ) ; sb_1__0__mux_tree_tapbuf_size6 mux_top_track_8 ( .in ( { chany_top_out[19] , top_left_grid_pin_48_[0] , top_left_grid_pin_51_[0] , chanx_right_in[9] , chanx_left_out[11] , @@ -31609,7 +31594,7 @@ sb_1__0__mux_tree_tapbuf_size6 mux_top_track_8 ( .sram ( mux_tree_tapbuf_size6_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 , SYNOPSYS_UNCONNECTED_39 } ) , - .out ( chany_top_out[4] ) , .p0 ( optlc_net_150 ) ) ; + .out ( chany_top_out[4] ) , .p0 ( optlc_net_152 ) ) ; sb_1__0__mux_tree_tapbuf_size6_mem_0 mem_top_track_2 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , @@ -31631,42 +31616,42 @@ sb_1__0__mux_tree_tapbuf_size5_0 mux_top_track_4 ( .sram ( mux_tree_tapbuf_size5_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_40 , SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 } ) , - .out ( chany_top_out[2] ) , .p0 ( optlc_net_150 ) ) ; + .out ( chany_top_out[2] ) , .p0 ( optlc_net_152 ) ) ; sb_1__0__mux_tree_tapbuf_size5_1 mux_top_track_10 ( .in ( { top_left_grid_pin_46_[0] , top_left_grid_pin_49_[0] , chanx_left_out[12] , chanx_right_in[13] , chanx_right_out[12] } ) , .sram ( mux_tree_tapbuf_size5_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 , SYNOPSYS_UNCONNECTED_45 } ) , - .out ( chany_top_out[5] ) , .p0 ( optlc_net_149 ) ) ; + .out ( chany_top_out[5] ) , .p0 ( optlc_net_155 ) ) ; sb_1__0__mux_tree_tapbuf_size5_2 mux_right_track_36 ( .in ( { chany_top_in[7] , chany_top_in[18] , chany_top_in[29] , right_bottom_grid_pin_7_[0] , chanx_right_out[16] } ) , .sram ( mux_tree_tapbuf_size5_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_46 , SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) , - .out ( chanx_right_out[18] ) , .p0 ( optlc_net_147 ) ) ; + .out ( chanx_right_out[18] ) , .p0 ( optlc_net_150 ) ) ; sb_1__0__mux_tree_tapbuf_size5_3 mux_left_track_37 ( .in ( { chany_top_in[3] , chany_top_in[14] , chany_top_in[25] , chanx_left_out[16] , left_bottom_grid_pin_7_[0] } ) , .sram ( mux_tree_tapbuf_size5_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 , SYNOPSYS_UNCONNECTED_51 } ) , - .out ( chanx_left_out[18] ) , .p0 ( optlc_net_146 ) ) ; + .out ( chanx_left_out[18] ) , .p0 ( optlc_net_151 ) ) ; sb_1__0__mux_tree_tapbuf_size5_4 mux_left_track_45 ( .in ( { chany_top_in[2] , chany_top_in[13] , chany_top_in[24] , chanx_left_out[17] , left_bottom_grid_pin_9_[0] } ) , .sram ( mux_tree_tapbuf_size5_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_52 , SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 } ) , - .out ( chanx_left_out[22] ) , .p0 ( optlc_net_146 ) ) ; + .out ( chanx_left_out[22] ) , .p0 ( optlc_net_151 ) ) ; sb_1__0__mux_tree_tapbuf_size5 mux_left_track_53 ( .in ( { chany_top_in[1] , chany_top_in[12] , chany_top_in[23] , chanx_left_out[19] , left_bottom_grid_pin_11_[0] } ) , .sram ( mux_tree_tapbuf_size5_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 , SYNOPSYS_UNCONNECTED_57 } ) , - .out ( chanx_left_out[26] ) , .p0 ( optlc_net_148 ) ) ; + .out ( chanx_left_out[26] ) , .p0 ( optlc_net_149 ) ) ; sb_1__0__mux_tree_tapbuf_size5_mem_0 mem_top_track_4 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , @@ -31702,14 +31687,14 @@ sb_1__0__mux_tree_tapbuf_size4_0 mux_top_track_12 ( .sram ( mux_tree_tapbuf_size4_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_58 , SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) , - .out ( chany_top_out[6] ) , .p0 ( optlc_net_151 ) ) ; + .out ( chany_top_out[6] ) , .p0 ( optlc_net_152 ) ) ; sb_1__0__mux_tree_tapbuf_size4_1 mux_top_track_14 ( .in ( { chany_top_out[19] , chanx_left_out[15] , chanx_right_in[21] , chanx_right_out[15] } ) , .sram ( mux_tree_tapbuf_size4_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 , SYNOPSYS_UNCONNECTED_63 } ) , - .out ( chany_top_out[7] ) , .p0 ( optlc_net_147 ) ) ; + .out ( chany_top_out[7] ) , .p0 ( optlc_net_150 ) ) ; sb_1__0__mux_tree_tapbuf_size4_2 mux_top_track_16 ( .in ( { top_left_grid_pin_46_[0] , chanx_left_out[16] , chanx_right_in[25] , chanx_right_out[16] } ) , @@ -31723,21 +31708,21 @@ sb_1__0__mux_tree_tapbuf_size4_3 mux_top_track_18 ( .sram ( mux_tree_tapbuf_size4_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 , SYNOPSYS_UNCONNECTED_69 } ) , - .out ( chany_top_out[9] ) , .p0 ( optlc_net_150 ) ) ; + .out ( chany_top_out[9] ) , .p0 ( optlc_net_155 ) ) ; sb_1__0__mux_tree_tapbuf_size4_4 mux_right_track_44 ( .in ( { chany_top_in[8] , chany_top_in[19] , right_bottom_grid_pin_9_[0] , chanx_right_out[17] } ) , .sram ( mux_tree_tapbuf_size4_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_70 , SYNOPSYS_UNCONNECTED_71 , SYNOPSYS_UNCONNECTED_72 } ) , - .out ( chanx_right_out[22] ) , .p0 ( optlc_net_147 ) ) ; + .out ( chanx_right_out[22] ) , .p0 ( optlc_net_150 ) ) ; sb_1__0__mux_tree_tapbuf_size4 mux_right_track_52 ( .in ( { chany_top_in[9] , chany_top_in[20] , right_bottom_grid_pin_11_[0] , chanx_right_out[19] } ) , .sram ( mux_tree_tapbuf_size4_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_73 , SYNOPSYS_UNCONNECTED_74 , SYNOPSYS_UNCONNECTED_75 } ) , - .out ( chanx_right_out[26] ) , .p0 ( optlc_net_147 ) ) ; + .out ( chanx_right_out[26] ) , .p0 ( optlc_net_150 ) ) ; sb_1__0__mux_tree_tapbuf_size4_mem_0 mem_top_track_12 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , @@ -31773,31 +31758,31 @@ sb_1__0__mux_tree_tapbuf_size3_0 mux_top_track_20 ( chanx_right_out[19] } ) , .sram ( mux_tree_tapbuf_size3_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_76 , SYNOPSYS_UNCONNECTED_77 } ) , - .out ( chany_top_out[10] ) , .p0 ( optlc_net_149 ) ) ; + .out ( chany_top_out[10] ) , .p0 ( optlc_net_155 ) ) ; sb_1__0__mux_tree_tapbuf_size3_1 mux_top_track_22 ( .in ( { top_left_grid_pin_49_[0] , chanx_left_out[20] , chanx_right_out[20] } ) , .sram ( mux_tree_tapbuf_size3_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_78 , SYNOPSYS_UNCONNECTED_79 } ) , - .out ( chany_top_out[11] ) , .p0 ( optlc_net_149 ) ) ; + .out ( chany_top_out[11] ) , .p0 ( optlc_net_156 ) ) ; sb_1__0__mux_tree_tapbuf_size3_2 mux_top_track_24 ( .in ( { top_left_grid_pin_50_[0] , chanx_left_out[21] , chanx_right_out[21] } ) , .sram ( mux_tree_tapbuf_size3_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_80 , SYNOPSYS_UNCONNECTED_81 } ) , - .out ( chany_top_out[12] ) , .p0 ( optlc_net_149 ) ) ; + .out ( chany_top_out[12] ) , .p0 ( optlc_net_155 ) ) ; sb_1__0__mux_tree_tapbuf_size3_3 mux_top_track_26 ( .in ( { top_left_grid_pin_51_[0] , chanx_left_out[23] , chanx_right_out[23] } ) , .sram ( mux_tree_tapbuf_size3_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_82 , SYNOPSYS_UNCONNECTED_83 } ) , - .out ( chany_top_out[13] ) , .p0 ( optlc_net_150 ) ) ; + .out ( chany_top_out[13] ) , .p0 ( optlc_net_155 ) ) ; sb_1__0__mux_tree_tapbuf_size3 mux_top_track_36 ( .in ( { top_left_grid_pin_44_[0] , chanx_left_out[29] , chanx_right_out[29] } ) , .sram ( mux_tree_tapbuf_size3_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_84 , SYNOPSYS_UNCONNECTED_85 } ) , - .out ( chany_top_out[18] ) , .p0 ( optlc_net_149 ) ) ; + .out ( chany_top_out[18] ) , .p0 ( optlc_net_156 ) ) ; sb_1__0__mux_tree_tapbuf_size3_mem_0 mem_top_track_20 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , @@ -31827,57 +31812,57 @@ sb_1__0__mux_tree_tapbuf_size2_0 mux_top_track_28 ( .in ( { chanx_left_out[24] , chanx_right_out[24] } ) , .sram ( mux_tree_tapbuf_size2_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_86 , SYNOPSYS_UNCONNECTED_87 } ) , - .out ( chany_top_out[14] ) , .p0 ( optlc_net_150 ) ) ; + .out ( chany_top_out[14] ) , .p0 ( optlc_net_155 ) ) ; sb_1__0__mux_tree_tapbuf_size2_1 mux_top_track_30 ( .in ( { chanx_left_out[25] , chanx_right_out[25] } ) , .sram ( mux_tree_tapbuf_size2_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_88 , SYNOPSYS_UNCONNECTED_89 } ) , - .out ( chany_top_out[15] ) , .p0 ( optlc_net_150 ) ) ; + .out ( chany_top_out[15] ) , .p0 ( optlc_net_152 ) ) ; sb_1__0__mux_tree_tapbuf_size2_2 mux_top_track_32 ( .in ( { chanx_left_out[27] , chanx_right_out[27] } ) , .sram ( mux_tree_tapbuf_size2_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_90 , SYNOPSYS_UNCONNECTED_91 } ) , - .out ( chany_top_out[16] ) , .p0 ( optlc_net_150 ) ) ; + .out ( chany_top_out[16] ) , .p0 ( optlc_net_155 ) ) ; sb_1__0__mux_tree_tapbuf_size2_3 mux_top_track_34 ( .in ( { chanx_left_out[28] , chanx_right_out[28] } ) , .sram ( mux_tree_tapbuf_size2_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_92 , SYNOPSYS_UNCONNECTED_93 } ) , - .out ( chany_top_out[17] ) , .p0 ( optlc_net_149 ) ) ; + .out ( chany_top_out[17] ) , .p0 ( optlc_net_156 ) ) ; sb_1__0__mux_tree_tapbuf_size2_4 mux_top_track_40 ( .in ( { top_left_grid_pin_46_[0] , chanx_left_in[29] } ) , .sram ( mux_tree_tapbuf_size2_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_94 , SYNOPSYS_UNCONNECTED_95 } ) , - .out ( chany_top_out[20] ) , .p0 ( optlc_net_149 ) ) ; + .out ( chany_top_out[20] ) , .p0 ( optlc_net_156 ) ) ; sb_1__0__mux_tree_tapbuf_size2_5 mux_top_track_42 ( .in ( { top_left_grid_pin_47_[0] , chanx_left_in[25] } ) , .sram ( mux_tree_tapbuf_size2_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_96 , SYNOPSYS_UNCONNECTED_97 } ) , - .out ( chany_top_out[21] ) , .p0 ( optlc_net_149 ) ) ; + .out ( chany_top_out[21] ) , .p0 ( optlc_net_156 ) ) ; sb_1__0__mux_tree_tapbuf_size2_6 mux_top_track_44 ( .in ( { top_left_grid_pin_48_[0] , chanx_left_in[21] } ) , .sram ( mux_tree_tapbuf_size2_6_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_98 , SYNOPSYS_UNCONNECTED_99 } ) , - .out ( chany_top_out[22] ) , .p0 ( optlc_net_149 ) ) ; + .out ( chany_top_out[22] ) , .p0 ( optlc_net_156 ) ) ; sb_1__0__mux_tree_tapbuf_size2_7 mux_top_track_46 ( .in ( { top_left_grid_pin_49_[0] , chanx_left_in[17] } ) , .sram ( mux_tree_tapbuf_size2_7_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_100 , SYNOPSYS_UNCONNECTED_101 } ) , - .out ( chany_top_out[23] ) , .p0 ( optlc_net_149 ) ) ; + .out ( chany_top_out[23] ) , .p0 ( optlc_net_156 ) ) ; sb_1__0__mux_tree_tapbuf_size2_8 mux_top_track_48 ( .in ( { top_left_grid_pin_50_[0] , chanx_left_in[13] } ) , .sram ( mux_tree_tapbuf_size2_8_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_102 , SYNOPSYS_UNCONNECTED_103 } ) , - .out ( chany_top_out[24] ) , .p0 ( optlc_net_149 ) ) ; + .out ( chany_top_out[24] ) , .p0 ( optlc_net_156 ) ) ; sb_1__0__mux_tree_tapbuf_size2_9 mux_top_track_50 ( .in ( { top_left_grid_pin_51_[0] , chanx_left_in[9] } ) , .sram ( mux_tree_tapbuf_size2_9_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_104 , SYNOPSYS_UNCONNECTED_105 } ) , - .out ( chany_top_out[25] ) , .p0 ( optlc_net_149 ) ) ; + .out ( chany_top_out[25] ) , .p0 ( optlc_net_155 ) ) ; sb_1__0__mux_tree_tapbuf_size2 mux_top_track_58 ( .in ( { chanx_right_in[0] , chanx_left_in[1] } ) , .sram ( mux_tree_tapbuf_size2_10_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_106 , SYNOPSYS_UNCONNECTED_107 } ) , - .out ( chany_top_out[29] ) , .p0 ( optlc_net_150 ) ) ; + .out ( chany_top_out[29] ) , .p0 ( optlc_net_154 ) ) ; sb_1__0__mux_tree_tapbuf_size2_mem_0 mem_top_track_28 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , @@ -31941,7 +31926,7 @@ sb_1__0__mux_tree_tapbuf_size8_0 mux_right_track_2 ( .sram ( mux_tree_tapbuf_size8_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_108 , SYNOPSYS_UNCONNECTED_109 , SYNOPSYS_UNCONNECTED_110 , SYNOPSYS_UNCONNECTED_111 } ) , - .out ( chanx_right_out[1] ) , .p0 ( optlc_net_147 ) ) ; + .out ( chanx_right_out[1] ) , .p0 ( optlc_net_150 ) ) ; sb_1__0__mux_tree_tapbuf_size8_1 mux_right_track_4 ( .in ( { chany_top_in[1] , chany_top_in[12] , chany_top_in[23] , right_bottom_grid_pin_5_[0] , right_bottom_grid_pin_11_[0] , @@ -31950,7 +31935,7 @@ sb_1__0__mux_tree_tapbuf_size8_1 mux_right_track_4 ( .sram ( mux_tree_tapbuf_size8_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_112 , SYNOPSYS_UNCONNECTED_113 , SYNOPSYS_UNCONNECTED_114 , SYNOPSYS_UNCONNECTED_115 } ) , - .out ( chanx_right_out[2] ) , .p0 ( optlc_net_147 ) ) ; + .out ( chanx_right_out[2] ) , .p0 ( optlc_net_150 ) ) ; sb_1__0__mux_tree_tapbuf_size8 mux_left_track_1 ( .in ( { chany_top_in[0] , chany_top_in[11] , chany_top_in[22] , chanx_left_out[4] , chanx_left_out[20] , left_bottom_grid_pin_1_[0] , @@ -31958,7 +31943,7 @@ sb_1__0__mux_tree_tapbuf_size8 mux_left_track_1 ( .sram ( mux_tree_tapbuf_size8_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_116 , SYNOPSYS_UNCONNECTED_117 , SYNOPSYS_UNCONNECTED_118 , SYNOPSYS_UNCONNECTED_119 } ) , - .out ( chanx_left_out[0] ) , .p0 ( optlc_net_148 ) ) ; + .out ( chanx_left_out[0] ) , .p0 ( optlc_net_151 ) ) ; sb_1__0__mux_tree_tapbuf_size8_mem_0 mem_right_track_2 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , @@ -31983,7 +31968,7 @@ sb_1__0__mux_tree_tapbuf_size10 mux_right_track_6 ( .sram ( mux_tree_tapbuf_size10_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_120 , SYNOPSYS_UNCONNECTED_121 , SYNOPSYS_UNCONNECTED_122 , SYNOPSYS_UNCONNECTED_123 } ) , - .out ( chanx_right_out[3] ) , .p0 ( optlc_net_151 ) ) ; + .out ( chanx_right_out[3] ) , .p0 ( optlc_net_153 ) ) ; sb_1__0__mux_tree_tapbuf_size10_mem mem_right_track_6 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , @@ -31997,7 +31982,7 @@ sb_1__0__mux_tree_tapbuf_size9_0 mux_right_track_10 ( .sram ( mux_tree_tapbuf_size9_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_124 , SYNOPSYS_UNCONNECTED_125 , SYNOPSYS_UNCONNECTED_126 , SYNOPSYS_UNCONNECTED_127 } ) , - .out ( chanx_right_out[5] ) , .p0 ( optlc_net_151 ) ) ; + .out ( chanx_right_out[5] ) , .p0 ( optlc_net_153 ) ) ; sb_1__0__mux_tree_tapbuf_size9_1 mux_left_track_7 ( .in ( { chany_top_in[8] , chany_top_in[19] , chanx_left_out[9] , chanx_left_out[24] , left_bottom_grid_pin_1_[0] , @@ -32006,7 +31991,7 @@ sb_1__0__mux_tree_tapbuf_size9_1 mux_left_track_7 ( .sram ( mux_tree_tapbuf_size9_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_128 , SYNOPSYS_UNCONNECTED_129 , SYNOPSYS_UNCONNECTED_130 , SYNOPSYS_UNCONNECTED_131 } ) , - .out ( chanx_left_out[3] ) , .p0 ( optlc_net_148 ) ) ; + .out ( chanx_left_out[3] ) , .p0 ( optlc_net_151 ) ) ; sb_1__0__mux_tree_tapbuf_size9 mux_left_track_11 ( .in ( { chany_top_in[7] , chany_top_in[18] , chany_top_in[29] , chanx_left_out[11] , chanx_left_out[25] , left_bottom_grid_pin_3_[0] , @@ -32015,7 +32000,7 @@ sb_1__0__mux_tree_tapbuf_size9 mux_left_track_11 ( .sram ( mux_tree_tapbuf_size9_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_132 , SYNOPSYS_UNCONNECTED_133 , SYNOPSYS_UNCONNECTED_134 , SYNOPSYS_UNCONNECTED_135 } ) , - .out ( chanx_left_out[5] ) , .p0 ( optlc_net_148 ) ) ; + .out ( chanx_left_out[5] ) , .p0 ( optlc_net_149 ) ) ; sb_1__0__mux_tree_tapbuf_size9_mem_0 mem_right_track_10 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , @@ -32031,8 +32016,8 @@ sb_1__0__mux_tree_tapbuf_size9_mem mem_left_track_11 ( .pReset ( pReset ) , .ccff_head ( mux_tree_tapbuf_size9_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size9_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size9_2_sram ) ) ; -sky130_fd_sc_hd__conb_1 optlc_148 ( .LO ( SYNOPSYS_UNCONNECTED_136 ) , - .HI ( optlc_net_146 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_151 ( .LO ( SYNOPSYS_UNCONNECTED_136 ) , + .HI ( optlc_net_149 ) ) ; sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_E_in ) , .X ( pReset[0] ) ) ; sky130_fd_sc_hd__buf_1 pReset_N_FTB01 ( .A ( pReset_E_in ) , .X ( aps_rename_505_ ) ) ; @@ -32040,8 +32025,8 @@ sky130_fd_sc_hd__bufbuf_16 pReset_W_FTB01 ( .A ( pReset_E_in ) , .X ( pReset_W_out ) ) ; sky130_fd_sc_hd__bufbuf_16 pReset_E_FTB01 ( .A ( pReset_E_in ) , .X ( pReset_E_out ) ) ; -sky130_fd_sc_hd__conb_1 optlc_150 ( .LO ( SYNOPSYS_UNCONNECTED_137 ) , - .HI ( optlc_net_147 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_153 ( .LO ( SYNOPSYS_UNCONNECTED_137 ) , + .HI ( optlc_net_150 ) ) ; sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_N_in ) , .X ( prog_clk[0] ) ) ; sky130_fd_sc_hd__buf_1 prog_clk_3_N_FTB01 ( .A ( prog_clk_3_S_in ) , @@ -32050,7 +32035,7 @@ sky130_fd_sc_hd__buf_1 clk_3_N_FTB01 ( .A ( clk_3_S_in ) , .X ( aps_rename_507_ ) ) ; sky130_fd_sc_hd__buf_8 FTB_49__48 ( .A ( top_left_grid_pin_45_[0] ) , .X ( chany_top_out[19] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_50__49 ( .A ( chanx_right_in[3] ) , +sky130_fd_sc_hd__buf_12 FTB_50__49 ( .A ( chanx_right_in[3] ) , .X ( chanx_left_out[4] ) ) ; sky130_fd_sc_hd__buf_8 FTB_51__50 ( .A ( chanx_right_in[6] ) , .X ( chanx_left_out[7] ) ) ; @@ -32132,31 +32117,35 @@ sky130_fd_sc_hd__buf_8 FTB_89__88 ( .A ( chanx_left_in[27] ) , .X ( chanx_right_out[28] ) ) ; sky130_fd_sc_hd__buf_8 FTB_90__89 ( .A ( chanx_left_in[28] ) , .X ( chanx_right_out[29] ) ) ; -sky130_fd_sc_hd__buf_6 FTB_91__90 ( .A ( SC_IN_TOP ) , .X ( ropt_net_170 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_132 ( .A ( BUF_net_133 ) , +sky130_fd_sc_hd__buf_6 FTB_91__90 ( .A ( SC_IN_TOP ) , .X ( ropt_net_176 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_137 ( .A ( BUF_net_138 ) , .Y ( Test_en_N_out ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_133 ( .A ( Test_en_S_in ) , .Y ( BUF_net_133 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_134 ( .A ( BUF_net_135 ) , .Y ( pReset_N_out ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_135 ( .A ( aps_rename_505_ ) , - .Y ( BUF_net_135 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_136 ( .A ( BUF_net_137 ) , .Y ( Reset_N_out ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_137 ( .A ( Reset_S_in ) , .Y ( BUF_net_137 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_138 ( .A ( BUF_net_139 ) , +sky130_fd_sc_hd__inv_1 BINV_R_138 ( .A ( Test_en_S_in ) , .Y ( BUF_net_138 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_139 ( .A ( BUF_net_140 ) , .Y ( pReset_N_out ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_140 ( .A ( aps_rename_505_ ) , + .Y ( BUF_net_140 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_141 ( .A ( BUF_net_142 ) , .Y ( Reset_N_out ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_142 ( .A ( Reset_S_in ) , .Y ( BUF_net_142 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_143 ( .A ( BUF_net_144 ) , .Y ( prog_clk_3_N_out ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_139 ( .A ( aps_rename_506_ ) , - .Y ( BUF_net_139 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_140 ( .A ( BUF_net_141 ) , .Y ( clk_3_N_out ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_141 ( .A ( aps_rename_507_ ) , - .Y ( BUF_net_141 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_152 ( .LO ( SYNOPSYS_UNCONNECTED_138 ) , - .HI ( optlc_net_148 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_154 ( .LO ( SYNOPSYS_UNCONNECTED_139 ) , - .HI ( optlc_net_149 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_156 ( .LO ( SYNOPSYS_UNCONNECTED_140 ) , - .HI ( optlc_net_150 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_158 ( .LO ( SYNOPSYS_UNCONNECTED_141 ) , +sky130_fd_sc_hd__inv_1 BINV_R_144 ( .A ( aps_rename_506_ ) , + .Y ( BUF_net_144 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_145 ( .A ( BUF_net_146 ) , .Y ( clk_3_N_out ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_146 ( .A ( aps_rename_507_ ) , + .Y ( BUF_net_146 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_155 ( .LO ( SYNOPSYS_UNCONNECTED_138 ) , .HI ( optlc_net_151 ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1347 ( .A ( ropt_net_170 ) , +sky130_fd_sc_hd__conb_1 optlc_157 ( .LO ( SYNOPSYS_UNCONNECTED_139 ) , + .HI ( optlc_net_152 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_162 ( .LO ( SYNOPSYS_UNCONNECTED_140 ) , + .HI ( optlc_net_153 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_164 ( .LO ( SYNOPSYS_UNCONNECTED_141 ) , + .HI ( optlc_net_154 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_166 ( .LO ( SYNOPSYS_UNCONNECTED_142 ) , + .HI ( optlc_net_155 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_168 ( .LO ( SYNOPSYS_UNCONNECTED_143 ) , + .HI ( optlc_net_156 ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1359 ( .A ( ropt_net_176 ) , .X ( SC_OUT_TOP ) ) ; endmodule @@ -32263,18 +32252,18 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -wire copt_net_102 ; +wire copt_net_103 ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( copt_net_102 ) ) ; + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( copt_net_103 ) ) ; sky130_fd_sc_hd__buf_6 FTB_33__32 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1267 ( .A ( copt_net_102 ) , - .X ( copt_net_101 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1269 ( .A ( copt_net_101 ) , - .X ( copt_net_103 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1270 ( .A ( copt_net_103 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1265 ( .A ( copt_net_103 ) , + .X ( copt_net_99 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1266 ( .A ( copt_net_99 ) , + .X ( copt_net_100 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1267 ( .A ( copt_net_100 ) , .X ( mem_out[1] ) ) ; endmodule @@ -32712,13 +32701,13 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; sb_0__2__const1_32 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_84 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) ) ; endmodule @@ -32821,13 +32810,14 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; sb_0__2__const1_28 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_79 ( .A ( BUF_net_80 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_80 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_80 ) ) ; endmodule @@ -32875,14 +32865,13 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; sb_0__2__const1_26 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_79 ( .A ( BUF_net_80 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_80 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_80 ) ) ; endmodule @@ -32989,9 +32978,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_77 ( .A ( BUF_net_78 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_78 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_78 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_86 ( .A ( BUF_net_87 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_87 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_87 ) ) ; endmodule @@ -33017,7 +33006,7 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_76 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_78 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -33068,12 +33057,11 @@ sb_0__2__const1_19 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_88 ( .A ( BUF_net_89 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_89 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_89 ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_77 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) ) ; endmodule @@ -33099,9 +33087,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_74 ( .A ( BUF_net_75 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_75 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_75 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_75 ( .A ( BUF_net_76 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_76 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_76 ) ) ; endmodule @@ -33127,9 +33115,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_72 ( .A ( BUF_net_73 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_73 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_73 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_73 ( .A ( BUF_net_74 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_74 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_74 ) ) ; endmodule @@ -33150,14 +33138,13 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; sb_0__2__const1_16 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_86 ( .A ( BUF_net_87 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_87 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_87 ) ) ; endmodule @@ -33178,13 +33165,13 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; sb_0__2__const1_15 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_71 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .X ( out[0] ) ) ; endmodule @@ -33259,14 +33246,13 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; sb_0__2__const1_12 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_84 ( .A ( BUF_net_85 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_85 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_85 ) ) ; endmodule @@ -33292,9 +33278,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_69 ( .A ( BUF_net_70 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_70 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_70 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_71 ( .A ( BUF_net_72 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_72 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_72 ) ) ; endmodule @@ -33320,8 +33306,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_68 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .X ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_69 ( .A ( BUF_net_70 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_70 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_70 ) ) ; endmodule @@ -33396,13 +33383,13 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; sb_0__2__const1_7 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_67 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .X ( out[0] ) ) ; endmodule @@ -33428,9 +33415,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_65 ( .A ( BUF_net_66 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_66 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_66 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_67 ( .A ( BUF_net_68 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_68 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_68 ) ) ; endmodule @@ -33532,33 +33519,31 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_181 ) , +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_190 ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1258 ( .A ( copt_net_94 ) , + .X ( copt_net_92 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1259 ( .A ( copt_net_92 ) , + .X ( copt_net_93 ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1260 ( .A ( copt_net_96 ) , .X ( copt_net_94 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1261 ( .A ( copt_net_94 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1261 ( .A ( ccff_head[0] ) , .X ( copt_net_95 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 copt_h_inst_1262 ( .A ( copt_net_97 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1262 ( .A ( copt_net_95 ) , .X ( copt_net_96 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1263 ( .A ( copt_net_98 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1263 ( .A ( copt_net_93 ) , .X ( copt_net_97 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1264 ( .A ( copt_net_99 ) , - .X ( copt_net_98 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1265 ( .A ( ccff_head[0] ) , - .X ( copt_net_99 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1343 ( .A ( copt_net_95 ) , - .X ( ropt_net_178 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1344 ( .A ( ropt_net_178 ) , - .X ( ropt_net_179 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1345 ( .A ( ropt_net_179 ) , - .X ( ropt_net_180 ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 ropt_h_inst_1346 ( .A ( ropt_net_180 ) , - .X ( ropt_net_181 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1351 ( .A ( copt_net_97 ) , + .X ( ropt_net_188 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1352 ( .A ( ropt_net_188 ) , + .X ( ropt_net_189 ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 ropt_h_inst_1353 ( .A ( ropt_net_189 ) , + .X ( ropt_net_190 ) ) ; endmodule @@ -33592,9 +33577,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_63 ( .A ( BUF_net_64 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_64 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .Y ( BUF_net_64 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_65 ( .A ( BUF_net_66 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_66 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_66 ) ) ; endmodule @@ -33628,9 +33613,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_61 ( .A ( BUF_net_62 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_62 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .Y ( BUF_net_62 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_63 ( .A ( BUF_net_64 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_64 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_64 ) ) ; endmodule @@ -33653,8 +33638,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; sb_0__2__const1_3 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , @@ -33666,6 +33649,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_61 ( .A ( BUF_net_62 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_62 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_62 ) ) ; endmodule @@ -33806,10 +33792,9 @@ output pReset_S_out ; input prog_clk_0_E_in ; wire ropt_net_129 ; -wire ropt_net_127 ; -wire ropt_net_137 ; +wire ropt_net_130 ; +wire ropt_net_131 ; wire ropt_net_128 ; -wire ropt_net_134 ; wire [0:0] prog_clk ; wire prog_clk_0 ; wire [0:1] mux_tree_tapbuf_size2_0_sram ; @@ -33897,7 +33882,7 @@ sb_0__2__mux_tree_tapbuf_size4_1 mux_right_track_2 ( .sram ( mux_tree_tapbuf_size4_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 } ) , - .out ( chanx_right_out[1] ) , .p0 ( optlc_net_92 ) ) ; + .out ( chanx_right_out[1] ) , .p0 ( optlc_net_90 ) ) ; sb_0__2__mux_tree_tapbuf_size4_2 mux_right_track_4 ( .in ( { right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_40_[0] , right_bottom_grid_pin_43_[0] , chany_bottom_in[26] } ) , @@ -33911,7 +33896,7 @@ sb_0__2__mux_tree_tapbuf_size4_3 mux_right_track_6 ( .sram ( mux_tree_tapbuf_size4_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , - .out ( chanx_right_out[3] ) , .p0 ( optlc_net_92 ) ) ; + .out ( chanx_right_out[3] ) , .p0 ( optlc_net_90 ) ) ; sb_0__2__mux_tree_tapbuf_size4_4 mux_right_track_8 ( .in ( { right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_39_[0] , right_bottom_grid_pin_42_[0] , chany_bottom_in[24] } ) , @@ -33959,77 +33944,77 @@ sb_0__2__mux_tree_tapbuf_size2_0 mux_right_track_12 ( .in ( { right_top_grid_pin_1_[0] , chany_bottom_in[22] } ) , .sram ( mux_tree_tapbuf_size2_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) , - .out ( chanx_right_out[6] ) , .p0 ( optlc_net_90 ) ) ; + .out ( chanx_right_out[6] ) , .p0 ( optlc_net_91 ) ) ; sb_0__2__mux_tree_tapbuf_size2_1 mux_right_track_14 ( .in ( { right_bottom_grid_pin_36_[0] , chany_bottom_in[21] } ) , .sram ( mux_tree_tapbuf_size2_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 } ) , - .out ( chanx_right_out[7] ) , .p0 ( optlc_net_93 ) ) ; + .out ( chanx_right_out[7] ) , .p0 ( optlc_net_88 ) ) ; sb_0__2__mux_tree_tapbuf_size2_2 mux_right_track_16 ( .in ( { right_bottom_grid_pin_37_[0] , chany_bottom_in[20] } ) , .sram ( mux_tree_tapbuf_size2_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) , - .out ( chanx_right_out[8] ) , .p0 ( optlc_net_93 ) ) ; + .out ( chanx_right_out[8] ) , .p0 ( optlc_net_88 ) ) ; sb_0__2__mux_tree_tapbuf_size2_3 mux_right_track_18 ( .in ( { right_bottom_grid_pin_38_[0] , chany_bottom_in[19] } ) , .sram ( mux_tree_tapbuf_size2_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 } ) , - .out ( chanx_right_out[9] ) , .p0 ( optlc_net_91 ) ) ; + .out ( chanx_right_out[9] ) , .p0 ( optlc_net_89 ) ) ; sb_0__2__mux_tree_tapbuf_size2_4 mux_right_track_20 ( .in ( { right_bottom_grid_pin_39_[0] , chany_bottom_in[18] } ) , .sram ( mux_tree_tapbuf_size2_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) , - .out ( chanx_right_out[10] ) , .p0 ( optlc_net_93 ) ) ; + .out ( chanx_right_out[10] ) , .p0 ( optlc_net_88 ) ) ; sb_0__2__mux_tree_tapbuf_size2_5 mux_right_track_22 ( .in ( { right_bottom_grid_pin_40_[0] , chany_bottom_in[17] } ) , .sram ( mux_tree_tapbuf_size2_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 } ) , - .out ( chanx_right_out[11] ) , .p0 ( optlc_net_93 ) ) ; + .out ( chanx_right_out[11] ) , .p0 ( optlc_net_88 ) ) ; sb_0__2__mux_tree_tapbuf_size2_6 mux_right_track_24 ( .in ( { right_bottom_grid_pin_41_[0] , chany_bottom_in[16] } ) , .sram ( mux_tree_tapbuf_size2_6_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) , - .out ( chanx_right_out[12] ) , .p0 ( optlc_net_93 ) ) ; + .out ( chanx_right_out[12] ) , .p0 ( optlc_net_88 ) ) ; sb_0__2__mux_tree_tapbuf_size2_7 mux_right_track_26 ( .in ( { right_bottom_grid_pin_42_[0] , chany_bottom_in[15] } ) , .sram ( mux_tree_tapbuf_size2_7_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 } ) , - .out ( chanx_right_out[13] ) , .p0 ( optlc_net_93 ) ) ; + .out ( chanx_right_out[13] ) , .p0 ( optlc_net_88 ) ) ; sb_0__2__mux_tree_tapbuf_size2_8 mux_right_track_30 ( .in ( { right_bottom_grid_pin_36_[0] , chany_bottom_in[13] } ) , .sram ( mux_tree_tapbuf_size2_8_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) , - .out ( chanx_right_out[15] ) , .p0 ( optlc_net_90 ) ) ; + .out ( chanx_right_out[15] ) , .p0 ( optlc_net_88 ) ) ; sb_0__2__mux_tree_tapbuf_size2_9 mux_right_track_32 ( .in ( { right_bottom_grid_pin_37_[0] , chany_bottom_in[12] } ) , .sram ( mux_tree_tapbuf_size2_9_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 } ) , - .out ( chanx_right_out[16] ) , .p0 ( optlc_net_93 ) ) ; + .out ( chanx_right_out[16] ) , .p0 ( optlc_net_89 ) ) ; sb_0__2__mux_tree_tapbuf_size2_10 mux_right_track_34 ( .in ( { right_bottom_grid_pin_38_[0] , chany_bottom_in[11] } ) , .sram ( mux_tree_tapbuf_size2_10_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) , - .out ( chanx_right_out[17] ) , .p0 ( optlc_net_91 ) ) ; + .out ( chanx_right_out[17] ) , .p0 ( optlc_net_89 ) ) ; sb_0__2__mux_tree_tapbuf_size2_11 mux_right_track_36 ( .in ( { right_bottom_grid_pin_39_[0] , chany_bottom_in[10] } ) , .sram ( mux_tree_tapbuf_size2_11_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 } ) , - .out ( chanx_right_out[18] ) , .p0 ( optlc_net_93 ) ) ; + .out ( chanx_right_out[18] ) , .p0 ( optlc_net_88 ) ) ; sb_0__2__mux_tree_tapbuf_size2_12 mux_right_track_38 ( .in ( { right_bottom_grid_pin_40_[0] , chany_bottom_in[9] } ) , .sram ( mux_tree_tapbuf_size2_12_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) , - .out ( chanx_right_out[19] ) , .p0 ( optlc_net_93 ) ) ; + .out ( chanx_right_out[19] ) , .p0 ( optlc_net_88 ) ) ; sb_0__2__mux_tree_tapbuf_size2_13 mux_right_track_40 ( .in ( { right_bottom_grid_pin_41_[0] , chany_bottom_in[8] } ) , .sram ( mux_tree_tapbuf_size2_13_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 } ) , - .out ( chanx_right_out[20] ) , .p0 ( optlc_net_93 ) ) ; + .out ( chanx_right_out[20] ) , .p0 ( optlc_net_88 ) ) ; sb_0__2__mux_tree_tapbuf_size2_14 mux_right_track_42 ( .in ( { right_bottom_grid_pin_42_[0] , chany_bottom_in[7] } ) , .sram ( mux_tree_tapbuf_size2_14_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) , - .out ( chanx_right_out[21] ) , .p0 ( optlc_net_90 ) ) ; + .out ( chanx_right_out[21] ) , .p0 ( optlc_net_88 ) ) ; sb_0__2__mux_tree_tapbuf_size2_15 mux_right_track_44 ( .in ( { right_top_grid_pin_1_[0] , chany_bottom_in[6] } ) , .sram ( mux_tree_tapbuf_size2_15_sram ) , @@ -34044,27 +34029,27 @@ sb_0__2__mux_tree_tapbuf_size2_17 mux_right_track_48 ( .in ( { right_bottom_grid_pin_37_[0] , chany_bottom_in[4] } ) , .sram ( mux_tree_tapbuf_size2_17_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 } ) , - .out ( chanx_right_out[24] ) , .p0 ( optlc_net_92 ) ) ; + .out ( chanx_right_out[24] ) , .p0 ( optlc_net_90 ) ) ; sb_0__2__mux_tree_tapbuf_size2_18 mux_right_track_50 ( .in ( { right_bottom_grid_pin_38_[0] , chany_bottom_in[3] } ) , .sram ( mux_tree_tapbuf_size2_18_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) , - .out ( chanx_right_out[25] ) , .p0 ( optlc_net_92 ) ) ; + .out ( chanx_right_out[25] ) , .p0 ( optlc_net_90 ) ) ; sb_0__2__mux_tree_tapbuf_size2_19 mux_right_track_54 ( .in ( { right_bottom_grid_pin_40_[0] , chany_bottom_in[1] } ) , .sram ( mux_tree_tapbuf_size2_19_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 } ) , - .out ( chanx_right_out[27] ) , .p0 ( optlc_net_92 ) ) ; + .out ( chanx_right_out[27] ) , .p0 ( optlc_net_90 ) ) ; sb_0__2__mux_tree_tapbuf_size2_20 mux_right_track_56 ( .in ( { right_bottom_grid_pin_41_[0] , chany_bottom_in[0] } ) , .sram ( mux_tree_tapbuf_size2_20_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) , - .out ( chanx_right_out[28] ) , .p0 ( optlc_net_93 ) ) ; + .out ( chanx_right_out[28] ) , .p0 ( optlc_net_88 ) ) ; sb_0__2__mux_tree_tapbuf_size2_21 mux_right_track_58 ( .in ( { right_bottom_grid_pin_42_[0] , chany_bottom_in[29] } ) , .sram ( mux_tree_tapbuf_size2_21_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 } ) , - .out ( chanx_right_out[29] ) , .p0 ( optlc_net_93 ) ) ; + .out ( chanx_right_out[29] ) , .p0 ( optlc_net_88 ) ) ; sb_0__2__mux_tree_tapbuf_size2_22 mux_bottom_track_1 ( .in ( { chanx_right_in[28] , bottom_left_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size2_22_sram ) , @@ -34079,17 +34064,17 @@ sb_0__2__mux_tree_tapbuf_size2_24 mux_bottom_track_13 ( .in ( { chanx_right_in[22] , bottom_left_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size2_24_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 } ) , - .out ( chany_bottom_out[6] ) , .p0 ( optlc_net_91 ) ) ; + .out ( chany_bottom_out[6] ) , .p0 ( optlc_net_89 ) ) ; sb_0__2__mux_tree_tapbuf_size2_25 mux_bottom_track_29 ( .in ( { chanx_right_in[14] , bottom_left_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size2_25_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_69 , SYNOPSYS_UNCONNECTED_70 } ) , - .out ( chany_bottom_out[14] ) , .p0 ( optlc_net_91 ) ) ; + .out ( chany_bottom_out[14] ) , .p0 ( optlc_net_89 ) ) ; sb_0__2__mux_tree_tapbuf_size2 mux_bottom_track_45 ( .in ( { chanx_right_in[6] , bottom_left_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size2_26_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_71 , SYNOPSYS_UNCONNECTED_72 } ) , - .out ( chany_bottom_out[22] ) , .p0 ( optlc_net_91 ) ) ; + .out ( chany_bottom_out[22] ) , .p0 ( optlc_net_89 ) ) ; sb_0__2__mux_tree_tapbuf_size2_mem_0 mem_right_track_12 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) , @@ -34235,7 +34220,7 @@ sb_0__2__mux_tree_tapbuf_size3 mux_right_track_52 ( chany_bottom_in[2] } ) , .sram ( mux_tree_tapbuf_size3_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_75 , SYNOPSYS_UNCONNECTED_76 } ) , - .out ( chanx_right_out[26] ) , .p0 ( optlc_net_92 ) ) ; + .out ( chanx_right_out[26] ) , .p0 ( optlc_net_90 ) ) ; sb_0__2__mux_tree_tapbuf_size3_mem_0 mem_right_track_28 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , @@ -34247,8 +34232,8 @@ sb_0__2__mux_tree_tapbuf_size3_mem mem_right_track_52 ( .pReset ( pReset ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_1_sram ) ) ; sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_E_in ) , .X ( pReset[0] ) ) ; -sky130_fd_sc_hd__buf_6 pReset_S_FTB01 ( .A ( pReset_E_in ) , - .X ( pReset_S_out ) ) ; +sky130_fd_sc_hd__conb_1 optlc_90 ( .LO ( SYNOPSYS_UNCONNECTED_77 ) , + .HI ( optlc_net_88 ) ) ; sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_E_in ) , .X ( prog_clk[0] ) ) ; sky130_fd_sc_hd__buf_8 FTB_36__35 ( .A ( chanx_right_in[0] ) , @@ -34257,33 +34242,33 @@ sky130_fd_sc_hd__buf_8 FTB_37__36 ( .A ( chanx_right_in[1] ) , .X ( chany_bottom_out[27] ) ) ; sky130_fd_sc_hd__buf_8 FTB_38__37 ( .A ( chanx_right_in[2] ) , .X ( chany_bottom_out[26] ) ) ; -sky130_fd_sc_hd__buf_6 FTB_39__38 ( .A ( chanx_right_in[3] ) , - .X ( ropt_net_129 ) ) ; +sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chanx_right_in[3] ) , + .X ( chany_bottom_out[25] ) ) ; sky130_fd_sc_hd__buf_6 FTB_40__39 ( .A ( chanx_right_in[4] ) , - .X ( ropt_net_127 ) ) ; + .X ( ropt_net_129 ) ) ; sky130_fd_sc_hd__buf_8 FTB_41__40 ( .A ( chanx_right_in[5] ) , .X ( chany_bottom_out[23] ) ) ; sky130_fd_sc_hd__buf_8 FTB_42__41 ( .A ( chanx_right_in[7] ) , .X ( chany_bottom_out[21] ) ) ; -sky130_fd_sc_hd__buf_6 FTB_43__42 ( .A ( chanx_right_in[8] ) , - .X ( ropt_net_137 ) ) ; +sky130_fd_sc_hd__buf_8 FTB_43__42 ( .A ( chanx_right_in[8] ) , + .X ( chany_bottom_out[20] ) ) ; sky130_fd_sc_hd__buf_8 FTB_44__43 ( .A ( chanx_right_in[9] ) , .X ( chany_bottom_out[19] ) ) ; sky130_fd_sc_hd__buf_8 FTB_45__44 ( .A ( chanx_right_in[10] ) , .X ( chany_bottom_out[18] ) ) ; -sky130_fd_sc_hd__buf_6 FTB_46__45 ( .A ( chanx_right_in[11] ) , - .X ( ropt_net_128 ) ) ; -sky130_fd_sc_hd__buf_8 FTB_47__46 ( .A ( chanx_right_in[12] ) , - .X ( chany_bottom_out[16] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_46__45 ( .A ( chanx_right_in[11] ) , + .X ( chany_bottom_out[17] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_47__46 ( .A ( chanx_right_in[12] ) , + .X ( ropt_net_130 ) ) ; sky130_fd_sc_hd__buf_8 FTB_48__47 ( .A ( chanx_right_in[13] ) , .X ( chany_bottom_out[15] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_49__48 ( .A ( chanx_right_in[15] ) , - .X ( chany_bottom_out[13] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_49__48 ( .A ( chanx_right_in[15] ) , + .X ( ropt_net_131 ) ) ; sky130_fd_sc_hd__buf_8 FTB_50__49 ( .A ( chanx_right_in[16] ) , .X ( chany_bottom_out[12] ) ) ; sky130_fd_sc_hd__buf_8 FTB_51__50 ( .A ( chanx_right_in[17] ) , .X ( chany_bottom_out[11] ) ) ; -sky130_fd_sc_hd__buf_6 FTB_52__51 ( .A ( chanx_right_in[18] ) , +sky130_fd_sc_hd__buf_8 FTB_52__51 ( .A ( chanx_right_in[18] ) , .X ( chany_bottom_out[10] ) ) ; sky130_fd_sc_hd__buf_8 FTB_53__52 ( .A ( chanx_right_in[19] ) , .X ( chany_bottom_out[9] ) ) ; @@ -34294,7 +34279,7 @@ sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chanx_right_in[21] ) , sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chanx_right_in[23] ) , .X ( chany_bottom_out[5] ) ) ; sky130_fd_sc_hd__buf_6 FTB_57__56 ( .A ( chanx_right_in[24] ) , - .X ( ropt_net_134 ) ) ; + .X ( ropt_net_128 ) ) ; sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chanx_right_in[26] ) , .X ( chany_bottom_out[2] ) ) ; sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( chanx_right_in[27] ) , @@ -34302,24 +34287,21 @@ sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( chanx_right_in[27] ) , sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( chanx_right_in[29] ) , .X ( chany_bottom_out[29] ) ) ; sky130_fd_sc_hd__buf_6 FTB_61__60 ( .A ( SC_IN_TOP ) , .X ( SC_OUT_BOT ) ) ; -sky130_fd_sc_hd__conb_1 optlc_92 ( .LO ( SYNOPSYS_UNCONNECTED_77 ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_85 ( .A ( pReset_E_in ) , .X ( pReset_S_out ) ) ; +sky130_fd_sc_hd__conb_1 optlc_92 ( .LO ( SYNOPSYS_UNCONNECTED_78 ) , + .HI ( optlc_net_89 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_94 ( .LO ( SYNOPSYS_UNCONNECTED_79 ) , .HI ( optlc_net_90 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_94 ( .LO ( SYNOPSYS_UNCONNECTED_78 ) , +sky130_fd_sc_hd__conb_1 optlc_96 ( .LO ( SYNOPSYS_UNCONNECTED_80 ) , .HI ( optlc_net_91 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_96 ( .LO ( SYNOPSYS_UNCONNECTED_79 ) , - .HI ( optlc_net_92 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_98 ( .LO ( SYNOPSYS_UNCONNECTED_80 ) , - .HI ( optlc_net_93 ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1293 ( .A ( ropt_net_127 ) , - .X ( chany_bottom_out[24] ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1294 ( .A ( ropt_net_128 ) , - .X ( chany_bottom_out[17] ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1295 ( .A ( ropt_net_129 ) , - .X ( chany_bottom_out[25] ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1300 ( .A ( ropt_net_134 ) , +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1293 ( .A ( ropt_net_128 ) , .X ( chany_bottom_out[4] ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1303 ( .A ( ropt_net_137 ) , - .X ( chany_bottom_out[20] ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1294 ( .A ( ropt_net_129 ) , + .X ( chany_bottom_out[24] ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1295 ( .A ( ropt_net_130 ) , + .X ( chany_bottom_out[16] ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1296 ( .A ( ropt_net_131 ) , + .X ( chany_bottom_out[13] ) ) ; endmodule @@ -34473,9 +34455,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_147 ( .A ( BUF_net_148 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_148 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_148 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_141 ( .A ( BUF_net_142 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_142 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_142 ) ) ; endmodule @@ -34496,13 +34478,14 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; sb_0__1__const1_48 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_139 ( .A ( BUF_net_140 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_140 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_140 ) ) ; endmodule @@ -34523,13 +34506,14 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; sb_0__1__const1_47 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_137 ( .A ( BUF_net_138 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_138 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_138 ) ) ; endmodule @@ -34577,14 +34561,13 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; sb_0__1__const1_45 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_145 ( .A ( BUF_net_146 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_146 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_146 ) ) ; endmodule @@ -34605,13 +34588,13 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; sb_0__1__const1_44 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_144 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .X ( out[0] ) ) ; endmodule @@ -34632,13 +34615,13 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; sb_0__1__const1_43 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_143 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .X ( out[0] ) ) ; endmodule @@ -34664,9 +34647,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_141 ( .A ( BUF_net_142 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_142 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_142 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_135 ( .A ( BUF_net_136 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_136 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_136 ) ) ; endmodule @@ -34678,14 +34661,14 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -wire copt_net_164 ; +wire copt_net_160 ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( copt_net_164 ) ) ; -sky130_fd_sc_hd__buf_8 FTB_42__41 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1334 ( .A ( copt_net_164 ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( copt_net_160 ) ) ; +sky130_fd_sc_hd__buf_6 FTB_42__41 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1336 ( .A ( copt_net_160 ) , .X ( mem_out[1] ) ) ; endmodule @@ -34860,7 +34843,7 @@ sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_140 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_134 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -34887,12 +34870,13 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_139 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .X ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_132 ( .A ( BUF_net_133 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_133 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .Y ( BUF_net_133 ) ) ; endmodule @@ -34922,7 +34906,7 @@ sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_138 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_131 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -34945,16 +34929,17 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; sb_0__1__const1_38 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_129 ( .A ( BUF_net_130 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_130 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .Y ( BUF_net_130 ) ) ; endmodule @@ -34976,17 +34961,16 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; sb_0__1__const1_37 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_136 ( .A ( BUF_net_137 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_137 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .Y ( BUF_net_137 ) ) ; endmodule @@ -35016,9 +35000,9 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_134 ( .A ( BUF_net_135 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_135 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .Y ( BUF_net_135 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_127 ( .A ( BUF_net_128 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_128 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .Y ( BUF_net_128 ) ) ; endmodule @@ -35040,6 +35024,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; sb_0__1__const1_35 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , @@ -35048,8 +35034,6 @@ sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_133 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .X ( out[0] ) ) ; endmodule @@ -35079,9 +35063,9 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_131 ( .A ( BUF_net_132 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_132 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .Y ( BUF_net_132 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_125 ( .A ( BUF_net_126 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_126 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .Y ( BUF_net_126 ) ) ; endmodule @@ -35103,6 +35087,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; sb_0__1__const1_33 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , @@ -35111,9 +35097,6 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_129 ( .A ( BUF_net_130 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_130 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .Y ( BUF_net_130 ) ) ; endmodule @@ -35143,9 +35126,9 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_127 ( .A ( BUF_net_128 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_128 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .Y ( BUF_net_128 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_123 ( .A ( BUF_net_124 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_124 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .Y ( BUF_net_124 ) ) ; endmodule @@ -35384,6 +35367,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; sb_0__1__const1_31 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , @@ -35395,8 +35380,6 @@ sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_126 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .X ( out[0] ) ) ; endmodule @@ -35426,13 +35409,12 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_124 ( .A ( BUF_net_125 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_125 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .Y ( BUF_net_125 ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_122 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .X ( out[0] ) ) ; endmodule @@ -35462,12 +35444,13 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_123 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .X ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_120 ( .A ( BUF_net_121 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_121 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_121 ) ) ; endmodule @@ -35490,8 +35473,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; sb_0__1__const1_28 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , @@ -35499,10 +35480,13 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_118 ( .A ( BUF_net_119 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_119 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_119 ) ) ; endmodule @@ -35525,8 +35509,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; sb_0__1__const1_27 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , @@ -35538,6 +35520,8 @@ sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_117 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .X ( out[0] ) ) ; endmodule @@ -35571,9 +35555,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_121 ( .A ( BUF_net_122 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_122 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .Y ( BUF_net_122 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_115 ( .A ( BUF_net_116 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_116 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_116 ) ) ; endmodule @@ -35642,7 +35626,7 @@ sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_120 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_114 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -35677,9 +35661,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_118 ( .A ( BUF_net_119 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_119 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .Y ( BUF_net_119 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_112 ( .A ( BUF_net_113 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_113 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_113 ) ) ; endmodule @@ -35713,9 +35697,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_116 ( .A ( BUF_net_117 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_117 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .Y ( BUF_net_117 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_110 ( .A ( BUF_net_111 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_111 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_111 ) ) ; endmodule @@ -35749,9 +35733,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_114 ( .A ( BUF_net_115 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_115 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .Y ( BUF_net_115 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_108 ( .A ( BUF_net_109 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_109 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_109 ) ) ; endmodule @@ -35774,6 +35758,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; sb_0__1__const1_20 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , @@ -35785,9 +35771,6 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_112 ( .A ( BUF_net_113 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_113 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .Y ( BUF_net_113 ) ) ; endmodule @@ -36041,9 +36024,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_110 ( .A ( BUF_net_111 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_111 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .Y ( BUF_net_111 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_106 ( .A ( BUF_net_107 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_107 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .Y ( BUF_net_107 ) ) ; endmodule @@ -36067,6 +36050,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; sb_0__1__const1_18 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -36081,8 +36066,6 @@ sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_109 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .X ( out[0] ) ) ; endmodule @@ -36120,9 +36103,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_107 ( .A ( BUF_net_108 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_108 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .Y ( BUF_net_108 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_104 ( .A ( BUF_net_105 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_105 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .Y ( BUF_net_105 ) ) ; endmodule @@ -36160,7 +36143,7 @@ sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_106 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_103 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -36238,9 +36221,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_104 ( .A ( BUF_net_105 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_105 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .Y ( BUF_net_105 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_101 ( .A ( BUF_net_102 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_102 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .Y ( BUF_net_102 ) ) ; endmodule @@ -36278,9 +36261,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_102 ( .A ( BUF_net_103 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_103 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .Y ( BUF_net_103 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_99 ( .A ( BUF_net_100 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_100 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .Y ( BUF_net_100 ) ) ; endmodule @@ -36357,9 +36340,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_100 ( .A ( BUF_net_101 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_101 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .Y ( BUF_net_101 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_97 ( .A ( BUF_net_98 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_98 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .Y ( BUF_net_98 ) ) ; endmodule @@ -36383,6 +36366,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; sb_0__1__const1_10 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -36397,9 +36382,6 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_98 ( .A ( BUF_net_99 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_99 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .Y ( BUF_net_99 ) ) ; endmodule @@ -36615,35 +36597,39 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_181 ) , +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_168 ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1325 ( .A ( ccff_head[0] ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1326 ( .A ( ropt_net_172 ) , + .X ( copt_net_149 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1327 ( .A ( copt_net_149 ) , + .X ( copt_net_150 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1328 ( .A ( ropt_net_170 ) , + .X ( copt_net_151 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1329 ( .A ( copt_net_153 ) , + .X ( copt_net_152 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1330 ( .A ( copt_net_150 ) , .X ( copt_net_153 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1326 ( .A ( copt_net_153 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1331 ( .A ( ccff_head[0] ) , .X ( copt_net_154 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1327 ( .A ( copt_net_154 ) , - .X ( copt_net_155 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1328 ( .A ( copt_net_155 ) , - .X ( copt_net_156 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1329 ( .A ( copt_net_156 ) , - .X ( copt_net_157 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1330 ( .A ( copt_net_157 ) , - .X ( copt_net_158 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1347 ( .A ( copt_net_158 ) , - .X ( ropt_net_177 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1348 ( .A ( ropt_net_177 ) , - .X ( ropt_net_178 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1349 ( .A ( ropt_net_178 ) , - .X ( ropt_net_179 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1350 ( .A ( ropt_net_179 ) , - .X ( ropt_net_180 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1351 ( .A ( ropt_net_180 ) , - .X ( ropt_net_181 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1340 ( .A ( copt_net_151 ) , + .X ( ropt_net_166 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1341 ( .A ( ropt_net_166 ) , + .X ( ropt_net_167 ) ) ; +sky130_fd_sc_hd__buf_2 ropt_h_inst_1342 ( .A ( ropt_net_167 ) , + .X ( ropt_net_168 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1343 ( .A ( copt_net_152 ) , + .X ( ropt_net_169 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1344 ( .A ( ropt_net_171 ) , + .X ( ropt_net_170 ) ) ; +sky130_fd_sc_hd__buf_4 ropt_h_inst_1345 ( .A ( ropt_net_169 ) , + .X ( ropt_net_171 ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 ropt_h_inst_1346 ( .A ( copt_net_154 ) , + .X ( ropt_net_172 ) ) ; endmodule @@ -36754,6 +36740,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; sb_0__1__const1_5 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -36767,12 +36755,10 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_97 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .X ( out[0] ) ) ; endmodule @@ -36885,8 +36871,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; sb_0__1__const1_2 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -36904,6 +36888,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_91 ( .A ( BUF_net_92 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_92 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .Y ( BUF_net_92 ) ) ; endmodule @@ -36928,6 +36915,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; sb_0__1__const1_1 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -36945,9 +36934,6 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_91 ( .A ( BUF_net_92 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_92 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .Y ( BUF_net_92 ) ) ; endmodule @@ -37026,7 +37012,6 @@ input pReset_E_in ; output pReset_S_out ; input prog_clk_0_E_in ; -wire ropt_net_168 ; wire [0:0] prog_clk ; wire prog_clk_0 ; wire [0:1] mux_tree_tapbuf_size2_0_sram ; @@ -37137,21 +37122,21 @@ sb_0__1__mux_tree_tapbuf_size6_0 mux_top_track_0 ( .sram ( mux_tree_tapbuf_size6_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 } ) , - .out ( chany_top_out[0] ) , .p0 ( optlc_net_151 ) ) ; + .out ( chany_top_out[0] ) , .p0 ( optlc_net_148 ) ) ; sb_0__1__mux_tree_tapbuf_size6_1 mux_top_track_6 ( .in ( { top_left_grid_pin_1_[0] , chanx_right_in[4] , chanx_right_in[15] , chanx_right_in[26] , chany_top_out[9] , chany_top_out[24] } ) , .sram ( mux_tree_tapbuf_size6_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 } ) , - .out ( chany_top_out[3] ) , .p0 ( optlc_net_152 ) ) ; + .out ( chany_top_out[3] ) , .p0 ( optlc_net_146 ) ) ; sb_0__1__mux_tree_tapbuf_size6_2 mux_top_track_12 ( .in ( { top_left_grid_pin_1_[0] , chanx_right_in[6] , chanx_right_in[17] , chanx_right_in[28] , chany_top_out[12] , chany_top_out[27] } ) , .sram ( mux_tree_tapbuf_size6_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 , SYNOPSYS_UNCONNECTED_9 } ) , - .out ( chany_top_out[6] ) , .p0 ( optlc_net_152 ) ) ; + .out ( chany_top_out[6] ) , .p0 ( optlc_net_146 ) ) ; sb_0__1__mux_tree_tapbuf_size6_3 mux_right_track_2 ( .in ( { chany_top_in[0] , chany_bottom_out[7] , right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_40_[0] , @@ -37159,7 +37144,7 @@ sb_0__1__mux_tree_tapbuf_size6_3 mux_right_track_2 ( .sram ( mux_tree_tapbuf_size6_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , - .out ( chanx_right_out[1] ) , .p0 ( optlc_net_149 ) ) ; + .out ( chanx_right_out[1] ) , .p0 ( optlc_net_147 ) ) ; sb_0__1__mux_tree_tapbuf_size6_4 mux_right_track_6 ( .in ( { chany_top_in[2] , chany_bottom_out[9] , right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_39_[0] , @@ -37167,7 +37152,7 @@ sb_0__1__mux_tree_tapbuf_size6_4 mux_right_track_6 ( .sram ( mux_tree_tapbuf_size6_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , SYNOPSYS_UNCONNECTED_15 } ) , - .out ( chanx_right_out[3] ) , .p0 ( optlc_net_151 ) ) ; + .out ( chanx_right_out[3] ) , .p0 ( optlc_net_144 ) ) ; sb_0__1__mux_tree_tapbuf_size6_5 mux_right_track_8 ( .in ( { chany_top_in[4] , chany_bottom_out[11] , right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_40_[0] , @@ -37175,21 +37160,21 @@ sb_0__1__mux_tree_tapbuf_size6_5 mux_right_track_8 ( .sram ( mux_tree_tapbuf_size6_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_16 , SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 } ) , - .out ( chanx_right_out[4] ) , .p0 ( optlc_net_149 ) ) ; + .out ( chanx_right_out[4] ) , .p0 ( optlc_net_147 ) ) ; sb_0__1__mux_tree_tapbuf_size6_6 mux_bottom_track_7 ( .in ( { chany_bottom_out[9] , chany_bottom_out[24] , chanx_right_in[6] , chanx_right_in[17] , chanx_right_in[28] , bottom_left_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size6_6_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 , SYNOPSYS_UNCONNECTED_21 } ) , - .out ( chany_bottom_out[3] ) , .p0 ( optlc_net_152 ) ) ; + .out ( chany_bottom_out[3] ) , .p0 ( optlc_net_145 ) ) ; sb_0__1__mux_tree_tapbuf_size6 mux_bottom_track_13 ( .in ( { chany_bottom_out[12] , chany_bottom_out[27] , chanx_right_in[4] , chanx_right_in[15] , chanx_right_in[26] , bottom_left_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size6_7_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_22 , SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) , - .out ( chany_bottom_out[6] ) , .p0 ( optlc_net_152 ) ) ; + .out ( chany_bottom_out[6] ) , .p0 ( optlc_net_145 ) ) ; sb_0__1__mux_tree_tapbuf_size6_mem_0 mem_top_track_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , @@ -37235,28 +37220,28 @@ sb_0__1__mux_tree_tapbuf_size5_0 mux_top_track_2 ( .sram ( mux_tree_tapbuf_size5_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , SYNOPSYS_UNCONNECTED_27 } ) , - .out ( chany_top_out[1] ) , .p0 ( optlc_net_151 ) ) ; + .out ( chany_top_out[1] ) , .p0 ( optlc_net_148 ) ) ; sb_0__1__mux_tree_tapbuf_size5_1 mux_top_track_4 ( .in ( { chanx_right_in[3] , chanx_right_in[14] , chanx_right_in[25] , - chany_top_out[8] , ropt_net_168 } ) , + chany_top_out[8] , chany_top_out[23] } ) , .sram ( mux_tree_tapbuf_size5_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_28 , SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 } ) , - .out ( chany_top_out[2] ) , .p0 ( optlc_net_152 ) ) ; + .out ( chany_top_out[2] ) , .p0 ( optlc_net_146 ) ) ; sb_0__1__mux_tree_tapbuf_size5_2 mux_top_track_10 ( .in ( { chanx_right_in[5] , chanx_right_in[16] , chanx_right_in[27] , chany_top_out[11] , chany_top_out[25] } ) , .sram ( mux_tree_tapbuf_size5_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 , SYNOPSYS_UNCONNECTED_33 } ) , - .out ( chany_top_out[5] ) , .p0 ( optlc_net_152 ) ) ; + .out ( chany_top_out[5] ) , .p0 ( optlc_net_146 ) ) ; sb_0__1__mux_tree_tapbuf_size5_3 mux_top_track_20 ( .in ( { chanx_right_in[7] , chanx_right_in[18] , chanx_right_in[29] , chany_top_out[13] , chany_top_out[28] } ) , .sram ( mux_tree_tapbuf_size5_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_34 , SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) , - .out ( chany_top_out[10] ) , .p0 ( optlc_net_152 ) ) ; + .out ( chany_top_out[10] ) , .p0 ( optlc_net_148 ) ) ; sb_0__1__mux_tree_tapbuf_size5_4 mux_right_track_0 ( .in ( { chany_bottom_out[4] , right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_39_[0] , right_bottom_grid_pin_42_[0] , @@ -37264,7 +37249,7 @@ sb_0__1__mux_tree_tapbuf_size5_4 mux_right_track_0 ( .sram ( mux_tree_tapbuf_size5_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 , SYNOPSYS_UNCONNECTED_39 } ) , - .out ( chanx_right_out[0] ) , .p0 ( optlc_net_151 ) ) ; + .out ( chanx_right_out[0] ) , .p0 ( optlc_net_148 ) ) ; sb_0__1__mux_tree_tapbuf_size5_5 mux_right_track_4 ( .in ( { chany_top_in[1] , chany_bottom_out[8] , right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_41_[0] , @@ -37272,7 +37257,7 @@ sb_0__1__mux_tree_tapbuf_size5_5 mux_right_track_4 ( .sram ( mux_tree_tapbuf_size5_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_40 , SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 } ) , - .out ( chanx_right_out[2] ) , .p0 ( optlc_net_151 ) ) ; + .out ( chanx_right_out[2] ) , .p0 ( optlc_net_144 ) ) ; sb_0__1__mux_tree_tapbuf_size5_6 mux_right_track_10 ( .in ( { chany_top_in[5] , chany_bottom_out[12] , right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_41_[0] , @@ -37280,42 +37265,42 @@ sb_0__1__mux_tree_tapbuf_size5_6 mux_right_track_10 ( .sram ( mux_tree_tapbuf_size5_6_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 , SYNOPSYS_UNCONNECTED_45 } ) , - .out ( chanx_right_out[5] ) , .p0 ( optlc_net_149 ) ) ; + .out ( chanx_right_out[5] ) , .p0 ( optlc_net_147 ) ) ; sb_0__1__mux_tree_tapbuf_size5_7 mux_bottom_track_1 ( .in ( { chany_bottom_out[4] , chany_bottom_out[20] , chanx_right_in[9] , chanx_right_in[20] , bottom_left_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size5_7_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_46 , SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) , - .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_152 ) ) ; + .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_145 ) ) ; sb_0__1__mux_tree_tapbuf_size5_8 mux_bottom_track_5 ( .in ( { chany_bottom_out[8] , chany_bottom_out[23] , chanx_right_in[7] , chanx_right_in[18] , chanx_right_in[29] } ) , .sram ( mux_tree_tapbuf_size5_8_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 , SYNOPSYS_UNCONNECTED_51 } ) , - .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_152 ) ) ; + .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_145 ) ) ; sb_0__1__mux_tree_tapbuf_size5_9 mux_bottom_track_11 ( .in ( { chany_bottom_out[11] , chany_bottom_out[25] , chanx_right_in[5] , chanx_right_in[16] , chanx_right_in[27] } ) , .sram ( mux_tree_tapbuf_size5_9_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_52 , SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 } ) , - .out ( chany_bottom_out[5] ) , .p0 ( optlc_net_152 ) ) ; + .out ( chany_bottom_out[5] ) , .p0 ( optlc_net_145 ) ) ; sb_0__1__mux_tree_tapbuf_size5_10 mux_bottom_track_21 ( .in ( { chany_bottom_out[13] , chany_bottom_out[28] , chanx_right_in[3] , chanx_right_in[14] , chanx_right_in[25] } ) , .sram ( mux_tree_tapbuf_size5_10_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 , SYNOPSYS_UNCONNECTED_57 } ) , - .out ( chany_bottom_out[10] ) , .p0 ( optlc_net_150 ) ) ; + .out ( chany_bottom_out[10] ) , .p0 ( optlc_net_148 ) ) ; sb_0__1__mux_tree_tapbuf_size5 mux_bottom_track_29 ( .in ( { chany_bottom_out[15] , chany_bottom_out[29] , chanx_right_in[2] , chanx_right_in[13] , chanx_right_in[24] } ) , .sram ( mux_tree_tapbuf_size5_11_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_58 , SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) , - .out ( chany_bottom_out[14] ) , .p0 ( optlc_net_150 ) ) ; + .out ( chany_bottom_out[14] ) , .p0 ( optlc_net_143 ) ) ; sb_0__1__mux_tree_tapbuf_size5_mem_0 mem_top_track_2 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , @@ -37382,84 +37367,84 @@ sb_0__1__mux_tree_tapbuf_size4_0 mux_top_track_28 ( .sram ( mux_tree_tapbuf_size4_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 , SYNOPSYS_UNCONNECTED_63 } ) , - .out ( chany_top_out[14] ) , .p0 ( optlc_net_151 ) ) ; + .out ( chany_top_out[14] ) , .p0 ( optlc_net_148 ) ) ; sb_0__1__mux_tree_tapbuf_size4_1 mux_top_track_52 ( .in ( { chanx_right_in[0] , chanx_right_in[11] , chanx_right_in[22] , chany_top_out[19] } ) , .sram ( mux_tree_tapbuf_size4_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_64 , SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 } ) , - .out ( chany_top_out[26] ) , .p0 ( optlc_net_151 ) ) ; + .out ( chany_top_out[26] ) , .p0 ( optlc_net_148 ) ) ; sb_0__1__mux_tree_tapbuf_size4_2 mux_right_track_12 ( .in ( { chany_top_in[9] , chany_bottom_out[13] , right_bottom_grid_pin_36_[0] , chany_top_out[13] } ) , .sram ( mux_tree_tapbuf_size4_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 , SYNOPSYS_UNCONNECTED_69 } ) , - .out ( chanx_right_out[6] ) , .p0 ( optlc_net_151 ) ) ; + .out ( chanx_right_out[6] ) , .p0 ( optlc_net_147 ) ) ; sb_0__1__mux_tree_tapbuf_size4_3 mux_right_track_14 ( .in ( { chany_top_in[13] , chany_bottom_out[15] , right_bottom_grid_pin_37_[0] , chany_top_out[15] } ) , .sram ( mux_tree_tapbuf_size4_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_70 , SYNOPSYS_UNCONNECTED_71 , SYNOPSYS_UNCONNECTED_72 } ) , - .out ( chanx_right_out[7] ) , .p0 ( optlc_net_151 ) ) ; + .out ( chanx_right_out[7] ) , .p0 ( optlc_net_144 ) ) ; sb_0__1__mux_tree_tapbuf_size4_4 mux_right_track_16 ( .in ( { chany_bottom_out[16] , chany_top_in[17] , right_bottom_grid_pin_38_[0] , chany_top_out[16] } ) , .sram ( mux_tree_tapbuf_size4_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_73 , SYNOPSYS_UNCONNECTED_74 , SYNOPSYS_UNCONNECTED_75 } ) , - .out ( chanx_right_out[8] ) , .p0 ( optlc_net_151 ) ) ; + .out ( chanx_right_out[8] ) , .p0 ( optlc_net_144 ) ) ; sb_0__1__mux_tree_tapbuf_size4_5 mux_right_track_18 ( .in ( { chany_bottom_out[17] , chany_top_in[21] , right_bottom_grid_pin_39_[0] , chany_top_out[17] } ) , .sram ( mux_tree_tapbuf_size4_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_76 , SYNOPSYS_UNCONNECTED_77 , SYNOPSYS_UNCONNECTED_78 } ) , - .out ( chanx_right_out[9] ) , .p0 ( optlc_net_151 ) ) ; + .out ( chanx_right_out[9] ) , .p0 ( optlc_net_144 ) ) ; sb_0__1__mux_tree_tapbuf_size4_6 mux_right_track_20 ( .in ( { chany_bottom_out[19] , chany_top_in[25] , right_bottom_grid_pin_40_[0] , chany_top_out[19] } ) , .sram ( mux_tree_tapbuf_size4_6_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_79 , SYNOPSYS_UNCONNECTED_80 , SYNOPSYS_UNCONNECTED_81 } ) , - .out ( chanx_right_out[10] ) , .p0 ( optlc_net_149 ) ) ; + .out ( chanx_right_out[10] ) , .p0 ( optlc_net_146 ) ) ; sb_0__1__mux_tree_tapbuf_size4_7 mux_right_track_22 ( .in ( { chany_bottom_out[20] , chany_top_in[29] , right_bottom_grid_pin_41_[0] , chany_top_out[20] } ) , .sram ( mux_tree_tapbuf_size4_7_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_82 , SYNOPSYS_UNCONNECTED_83 , SYNOPSYS_UNCONNECTED_84 } ) , - .out ( chanx_right_out[11] ) , .p0 ( optlc_net_149 ) ) ; + .out ( chanx_right_out[11] ) , .p0 ( optlc_net_146 ) ) ; sb_0__1__mux_tree_tapbuf_size4_8 mux_right_track_36 ( .in ( { chany_bottom_out[29] , right_bottom_grid_pin_40_[0] , chany_top_out[29] , chany_bottom_in[29] } ) , .sram ( mux_tree_tapbuf_size4_8_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_85 , SYNOPSYS_UNCONNECTED_86 , SYNOPSYS_UNCONNECTED_87 } ) , - .out ( chanx_right_out[18] ) , .p0 ( optlc_net_150 ) ) ; + .out ( chanx_right_out[18] ) , .p0 ( optlc_net_143 ) ) ; sb_0__1__mux_tree_tapbuf_size4_9 mux_bottom_track_3 ( .in ( { chany_bottom_out[7] , chany_bottom_out[21] , chanx_right_in[8] , chanx_right_in[19] } ) , .sram ( mux_tree_tapbuf_size4_9_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_88 , SYNOPSYS_UNCONNECTED_89 , SYNOPSYS_UNCONNECTED_90 } ) , - .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_150 ) ) ; + .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_143 ) ) ; sb_0__1__mux_tree_tapbuf_size4_10 mux_bottom_track_37 ( .in ( { chany_bottom_out[16] , chanx_right_in[1] , chanx_right_in[12] , chanx_right_in[23] } ) , .sram ( mux_tree_tapbuf_size4_10_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_91 , SYNOPSYS_UNCONNECTED_92 , SYNOPSYS_UNCONNECTED_93 } ) , - .out ( chany_bottom_out[18] ) , .p0 ( optlc_net_150 ) ) ; + .out ( chany_bottom_out[18] ) , .p0 ( optlc_net_143 ) ) ; sb_0__1__mux_tree_tapbuf_size4 mux_bottom_track_45 ( .in ( { chany_bottom_out[17] , chanx_right_in[0] , chanx_right_in[11] , chanx_right_in[22] } ) , .sram ( mux_tree_tapbuf_size4_11_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_94 , SYNOPSYS_UNCONNECTED_95 , SYNOPSYS_UNCONNECTED_96 } ) , - .out ( chany_bottom_out[22] ) , .p0 ( optlc_net_150 ) ) ; + .out ( chany_bottom_out[22] ) , .p0 ( optlc_net_144 ) ) ; sb_0__1__mux_tree_tapbuf_size4_mem_0 mem_top_track_28 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , @@ -37524,59 +37509,59 @@ sb_0__1__mux_tree_tapbuf_size3_0 mux_top_track_36 ( .in ( { chanx_right_in[9] , chanx_right_in[20] , chany_top_out[16] } ) , .sram ( mux_tree_tapbuf_size3_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_97 , SYNOPSYS_UNCONNECTED_98 } ) , - .out ( chany_top_out[18] ) , .p0 ( optlc_net_151 ) ) ; + .out ( chany_top_out[18] ) , .p0 ( optlc_net_144 ) ) ; sb_0__1__mux_tree_tapbuf_size3_1 mux_top_track_44 ( .in ( { chanx_right_in[10] , chanx_right_in[21] , chany_top_out[17] } ) , .sram ( mux_tree_tapbuf_size3_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_99 , SYNOPSYS_UNCONNECTED_100 } ) , - .out ( chany_top_out[22] ) , .p0 ( optlc_net_151 ) ) ; + .out ( chany_top_out[22] ) , .p0 ( optlc_net_144 ) ) ; sb_0__1__mux_tree_tapbuf_size3_2 mux_right_track_24 ( .in ( { chany_bottom_out[21] , right_bottom_grid_pin_42_[0] , chany_top_out[21] } ) , .sram ( mux_tree_tapbuf_size3_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_101 , SYNOPSYS_UNCONNECTED_102 } ) , - .out ( chanx_right_out[12] ) , .p0 ( optlc_net_149 ) ) ; + .out ( chanx_right_out[12] ) , .p0 ( optlc_net_146 ) ) ; sb_0__1__mux_tree_tapbuf_size3_3 mux_right_track_26 ( .in ( { chany_bottom_out[23] , right_bottom_grid_pin_43_[0] , - ropt_net_168 } ) , + chany_top_out[23] } ) , .sram ( mux_tree_tapbuf_size3_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_103 , SYNOPSYS_UNCONNECTED_104 } ) , - .out ( chanx_right_out[13] ) , .p0 ( optlc_net_149 ) ) ; + .out ( chanx_right_out[13] ) , .p0 ( optlc_net_147 ) ) ; sb_0__1__mux_tree_tapbuf_size3_4 mux_right_track_28 ( .in ( { chany_bottom_out[24] , right_bottom_grid_pin_36_[0] , chany_top_out[24] } ) , .sram ( mux_tree_tapbuf_size3_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_105 , SYNOPSYS_UNCONNECTED_106 } ) , - .out ( chanx_right_out[14] ) , .p0 ( optlc_net_149 ) ) ; + .out ( chanx_right_out[14] ) , .p0 ( optlc_net_148 ) ) ; sb_0__1__mux_tree_tapbuf_size3_5 mux_right_track_30 ( .in ( { chany_bottom_out[25] , right_bottom_grid_pin_37_[0] , chany_top_out[25] } ) , .sram ( mux_tree_tapbuf_size3_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_107 , SYNOPSYS_UNCONNECTED_108 } ) , - .out ( chanx_right_out[15] ) , .p0 ( optlc_net_149 ) ) ; + .out ( chanx_right_out[15] ) , .p0 ( optlc_net_148 ) ) ; sb_0__1__mux_tree_tapbuf_size3_6 mux_right_track_32 ( .in ( { chany_bottom_out[27] , right_bottom_grid_pin_38_[0] , chany_top_out[27] } ) , .sram ( mux_tree_tapbuf_size3_6_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_109 , SYNOPSYS_UNCONNECTED_110 } ) , - .out ( chanx_right_out[16] ) , .p0 ( optlc_net_151 ) ) ; + .out ( chanx_right_out[16] ) , .p0 ( optlc_net_147 ) ) ; sb_0__1__mux_tree_tapbuf_size3_7 mux_right_track_34 ( .in ( { chany_bottom_out[28] , right_bottom_grid_pin_39_[0] , chany_top_out[28] } ) , .sram ( mux_tree_tapbuf_size3_7_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_111 , SYNOPSYS_UNCONNECTED_112 } ) , - .out ( chanx_right_out[17] ) , .p0 ( optlc_net_151 ) ) ; + .out ( chanx_right_out[17] ) , .p0 ( optlc_net_144 ) ) ; sb_0__1__mux_tree_tapbuf_size3_8 mux_right_track_50 ( .in ( { right_bottom_grid_pin_39_[0] , right_bottom_grid_pin_43_[0] , chany_bottom_in[4] } ) , .sram ( mux_tree_tapbuf_size3_8_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_113 , SYNOPSYS_UNCONNECTED_114 } ) , - .out ( chanx_right_out[25] ) , .p0 ( optlc_net_150 ) ) ; + .out ( chanx_right_out[25] ) , .p0 ( optlc_net_143 ) ) ; sb_0__1__mux_tree_tapbuf_size3 mux_bottom_track_53 ( .in ( { chany_bottom_out[19] , chanx_right_in[10] , chanx_right_in[21] } ) , .sram ( mux_tree_tapbuf_size3_9_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_115 , SYNOPSYS_UNCONNECTED_116 } ) , - .out ( chany_bottom_out[26] ) , .p0 ( optlc_net_150 ) ) ; + .out ( chany_bottom_out[26] ) , .p0 ( optlc_net_143 ) ) ; sb_0__1__mux_tree_tapbuf_size3_mem_0 mem_top_track_36 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , @@ -37630,42 +37615,42 @@ sb_0__1__mux_tree_tapbuf_size2_0 mux_right_track_38 ( .in ( { right_bottom_grid_pin_41_[0] , chany_bottom_in[25] } ) , .sram ( mux_tree_tapbuf_size2_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_117 , SYNOPSYS_UNCONNECTED_118 } ) , - .out ( chanx_right_out[19] ) , .p0 ( optlc_net_150 ) ) ; + .out ( chanx_right_out[19] ) , .p0 ( optlc_net_143 ) ) ; sb_0__1__mux_tree_tapbuf_size2_1 mux_right_track_40 ( .in ( { right_bottom_grid_pin_42_[0] , chany_bottom_in[21] } ) , .sram ( mux_tree_tapbuf_size2_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_119 , SYNOPSYS_UNCONNECTED_120 } ) , - .out ( chanx_right_out[20] ) , .p0 ( optlc_net_150 ) ) ; + .out ( chanx_right_out[20] ) , .p0 ( optlc_net_143 ) ) ; sb_0__1__mux_tree_tapbuf_size2_2 mux_right_track_44 ( .in ( { right_bottom_grid_pin_36_[0] , chany_bottom_in[13] } ) , .sram ( mux_tree_tapbuf_size2_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_121 , SYNOPSYS_UNCONNECTED_122 } ) , - .out ( chanx_right_out[22] ) , .p0 ( optlc_net_150 ) ) ; + .out ( chanx_right_out[22] ) , .p0 ( optlc_net_143 ) ) ; sb_0__1__mux_tree_tapbuf_size2_3 mux_right_track_46 ( .in ( { right_bottom_grid_pin_37_[0] , chany_bottom_in[9] } ) , .sram ( mux_tree_tapbuf_size2_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_123 , SYNOPSYS_UNCONNECTED_124 } ) , - .out ( chanx_right_out[23] ) , .p0 ( optlc_net_150 ) ) ; + .out ( chanx_right_out[23] ) , .p0 ( optlc_net_143 ) ) ; sb_0__1__mux_tree_tapbuf_size2_4 mux_right_track_48 ( .in ( { right_bottom_grid_pin_38_[0] , chany_bottom_in[5] } ) , .sram ( mux_tree_tapbuf_size2_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_125 , SYNOPSYS_UNCONNECTED_126 } ) , - .out ( chanx_right_out[24] ) , .p0 ( optlc_net_150 ) ) ; + .out ( chanx_right_out[24] ) , .p0 ( optlc_net_143 ) ) ; sb_0__1__mux_tree_tapbuf_size2_5 mux_right_track_52 ( .in ( { right_bottom_grid_pin_40_[0] , chany_bottom_in[2] } ) , .sram ( mux_tree_tapbuf_size2_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_127 , SYNOPSYS_UNCONNECTED_128 } ) , - .out ( chanx_right_out[26] ) , .p0 ( optlc_net_150 ) ) ; + .out ( chanx_right_out[26] ) , .p0 ( optlc_net_143 ) ) ; sb_0__1__mux_tree_tapbuf_size2_6 mux_right_track_54 ( .in ( { right_bottom_grid_pin_41_[0] , chany_bottom_in[1] } ) , .sram ( mux_tree_tapbuf_size2_6_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_129 , SYNOPSYS_UNCONNECTED_130 } ) , - .out ( chanx_right_out[27] ) , .p0 ( optlc_net_150 ) ) ; + .out ( chanx_right_out[27] ) , .p0 ( optlc_net_143 ) ) ; sb_0__1__mux_tree_tapbuf_size2 mux_right_track_56 ( .in ( { right_bottom_grid_pin_42_[0] , chany_bottom_in[0] } ) , .sram ( mux_tree_tapbuf_size2_7_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_131 , SYNOPSYS_UNCONNECTED_132 } ) , - .out ( chanx_right_out[28] ) , .p0 ( optlc_net_150 ) ) ; + .out ( chanx_right_out[28] ) , .p0 ( optlc_net_143 ) ) ; sb_0__1__mux_tree_tapbuf_size2_mem_0 mem_right_track_38 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_8_ccff_tail ) , @@ -37777,8 +37762,8 @@ sky130_fd_sc_hd__buf_8 FTB_82__81 ( .A ( chany_bottom_in[19] ) , .X ( chany_top_out[20] ) ) ; sky130_fd_sc_hd__buf_8 FTB_83__82 ( .A ( chany_bottom_in[20] ) , .X ( chany_top_out[21] ) ) ; -sky130_fd_sc_hd__buf_1 FTB_84__83 ( .A ( chany_bottom_in[22] ) , - .X ( ropt_net_168 ) ) ; +sky130_fd_sc_hd__buf_8 FTB_84__83 ( .A ( chany_bottom_in[22] ) , + .X ( chany_top_out[23] ) ) ; sky130_fd_sc_hd__buf_8 FTB_85__84 ( .A ( chany_bottom_in[23] ) , .X ( chany_top_out[24] ) ) ; sky130_fd_sc_hd__buf_8 FTB_86__85 ( .A ( chany_bottom_in[24] ) , @@ -37789,16 +37774,18 @@ sky130_fd_sc_hd__buf_8 FTB_88__87 ( .A ( chany_bottom_in[27] ) , .X ( chany_top_out[28] ) ) ; sky130_fd_sc_hd__buf_8 FTB_89__88 ( .A ( chany_bottom_in[28] ) , .X ( chany_top_out[29] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_151 ( .LO ( SYNOPSYS_UNCONNECTED_133 ) , - .HI ( optlc_net_149 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_153 ( .LO ( SYNOPSYS_UNCONNECTED_134 ) , - .HI ( optlc_net_150 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_155 ( .LO ( SYNOPSYS_UNCONNECTED_135 ) , - .HI ( optlc_net_151 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_157 ( .LO ( SYNOPSYS_UNCONNECTED_136 ) , - .HI ( optlc_net_152 ) ) ; -sky130_fd_sc_hd__buf_6 ropt_mt_inst_1340 ( .A ( ropt_net_168 ) , - .X ( chany_top_out[23] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_146 ( .LO ( SYNOPSYS_UNCONNECTED_133 ) , + .HI ( optlc_net_143 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_148 ( .LO ( SYNOPSYS_UNCONNECTED_134 ) , + .HI ( optlc_net_144 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_151 ( .LO ( SYNOPSYS_UNCONNECTED_135 ) , + .HI ( optlc_net_145 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_154 ( .LO ( SYNOPSYS_UNCONNECTED_136 ) , + .HI ( optlc_net_146 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_156 ( .LO ( SYNOPSYS_UNCONNECTED_137 ) , + .HI ( optlc_net_147 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_158 ( .LO ( SYNOPSYS_UNCONNECTED_138 ) , + .HI ( optlc_net_148 ) ) ; endmodule @@ -38116,9 +38103,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_95 ( .A ( BUF_net_96 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_96 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .Y ( BUF_net_96 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_88 ( .A ( BUF_net_89 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_89 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_89 ) ) ; endmodule @@ -38152,9 +38139,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_93 ( .A ( BUF_net_94 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_94 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .Y ( BUF_net_94 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_86 ( .A ( BUF_net_87 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_87 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_87 ) ) ; endmodule @@ -38188,9 +38175,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_99 ( .A ( BUF_net_100 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_100 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .Y ( BUF_net_100 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_90 ( .A ( BUF_net_91 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_91 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_91 ) ) ; endmodule @@ -38224,9 +38211,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_91 ( .A ( BUF_net_92 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_92 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .Y ( BUF_net_92 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_84 ( .A ( BUF_net_85 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_85 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_85 ) ) ; endmodule @@ -38277,14 +38264,14 @@ sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__buf_6 FTB_26__25 ( .A ( copt_net_116 ) , +sky130_fd_sc_hd__buf_8 FTB_26__25 ( .A ( copt_net_108 ) , .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1278 ( .A ( mem_out[1] ) , - .X ( copt_net_114 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1279 ( .A ( copt_net_114 ) , - .X ( copt_net_115 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1280 ( .A ( copt_net_115 ) , - .X ( copt_net_116 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1272 ( .A ( mem_out[1] ) , + .X ( copt_net_106 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1273 ( .A ( copt_net_106 ) , + .X ( copt_net_107 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1274 ( .A ( copt_net_107 ) , + .X ( copt_net_108 ) ) ; endmodule @@ -38680,29 +38667,29 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_194 ) , +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_191 ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1271 ( .A ( ccff_head[0] ) , - .X ( copt_net_107 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1272 ( .A ( copt_net_107 ) , - .X ( copt_net_108 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1273 ( .A ( copt_net_108 ) , - .X ( copt_net_109 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1274 ( .A ( copt_net_112 ) , - .X ( copt_net_110 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1275 ( .A ( copt_net_110 ) , - .X ( copt_net_111 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1276 ( .A ( copt_net_109 ) , - .X ( copt_net_112 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1356 ( .A ( copt_net_111 ) , - .X ( ropt_net_192 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1357 ( .A ( ropt_net_192 ) , - .X ( ropt_net_193 ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 ropt_h_inst_1358 ( .A ( ropt_net_193 ) , - .X ( ropt_net_194 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1265 ( .A ( ccff_head[0] ) , + .X ( copt_net_99 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1266 ( .A ( copt_net_99 ) , + .X ( copt_net_100 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1267 ( .A ( copt_net_103 ) , + .X ( copt_net_101 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1268 ( .A ( copt_net_101 ) , + .X ( copt_net_102 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1269 ( .A ( copt_net_100 ) , + .X ( copt_net_103 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1270 ( .A ( copt_net_102 ) , + .X ( copt_net_104 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1355 ( .A ( copt_net_104 ) , + .X ( ropt_net_189 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1356 ( .A ( ropt_net_189 ) , + .X ( ropt_net_190 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1357 ( .A ( ropt_net_190 ) , + .X ( ropt_net_191 ) ) ; endmodule @@ -38752,12 +38739,11 @@ sb_0__0__const1_24 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_89 ( .A ( BUF_net_90 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_90 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_90 ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_83 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) ) ; endmodule @@ -38783,7 +38769,7 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_88 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_82 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -38832,14 +38818,13 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; sb_0__0__const1_21 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_86 ( .A ( BUF_net_87 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_87 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_87 ) ) ; endmodule @@ -38862,12 +38847,11 @@ sb_0__0__const1_20 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_84 ( .A ( BUF_net_85 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_85 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_85 ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_81 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) ) ; endmodule @@ -38892,7 +38876,7 @@ sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; endmodule @@ -38915,13 +38899,13 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; sb_0__0__const1_18 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_83 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .X ( out[0] ) ) ; endmodule @@ -38947,9 +38931,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_81 ( .A ( BUF_net_82 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_82 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_82 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_79 ( .A ( BUF_net_80 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_80 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_80 ) ) ; endmodule @@ -38975,9 +38959,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_79 ( .A ( BUF_net_80 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_80 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_80 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_77 ( .A ( BUF_net_78 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_78 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_78 ) ) ; endmodule @@ -39057,9 +39041,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_77 ( .A ( BUF_net_78 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_78 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_78 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_75 ( .A ( BUF_net_76 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_76 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_76 ) ) ; endmodule @@ -39085,7 +39069,7 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_76 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_74 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -39109,12 +39093,11 @@ sb_0__0__const1_11 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_74 ( .A ( BUF_net_75 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_75 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_75 ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_73 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) ) ; endmodule @@ -39167,9 +39150,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_73 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_73 ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_101 ( .A ( BUF_net_73 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_72 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_72 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_92 ( .A ( BUF_net_72 ) , .Y ( out[0] ) ) ; endmodule @@ -39195,9 +39178,8 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_97 ( .A ( BUF_net_98 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_98 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_98 ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_70 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) ) ; endmodule @@ -39245,14 +39227,13 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; sb_0__0__const1_6 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_70 ( .A ( BUF_net_71 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_71 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_71 ) ) ; endmodule @@ -39450,8 +39431,10 @@ output [0:0] ccff_tail ; input pReset_E_in ; input prog_clk_0_E_in ; -wire ropt_net_139 ; -wire ropt_net_140 ; +wire ropt_net_141 ; +wire ropt_net_133 ; +wire ropt_net_134 ; +wire ropt_net_135 ; wire [0:0] prog_clk ; wire prog_clk_0 ; wire [0:1] mux_tree_tapbuf_size2_0_sram ; @@ -39530,132 +39513,132 @@ sb_0__0__mux_tree_tapbuf_size2_0 mux_top_track_0 ( .in ( { top_left_grid_pin_1_[0] , chanx_right_in[1] } ) , .sram ( mux_tree_tapbuf_size2_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 } ) , - .out ( chany_top_out[0] ) , .p0 ( optlc_net_105 ) ) ; + .out ( chany_top_out[0] ) , .p0 ( optlc_net_95 ) ) ; sb_0__0__mux_tree_tapbuf_size2_1 mux_top_track_6 ( .in ( { top_left_grid_pin_1_[0] , chanx_right_in[4] } ) , .sram ( mux_tree_tapbuf_size2_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , - .out ( chany_top_out[3] ) , .p0 ( optlc_net_105 ) ) ; + .out ( chany_top_out[3] ) , .p0 ( optlc_net_95 ) ) ; sb_0__0__mux_tree_tapbuf_size2_2 mux_top_track_12 ( .in ( { top_left_grid_pin_1_[0] , chanx_right_in[7] } ) , .sram ( mux_tree_tapbuf_size2_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 } ) , - .out ( chany_top_out[6] ) , .p0 ( optlc_net_105 ) ) ; + .out ( chany_top_out[6] ) , .p0 ( optlc_net_95 ) ) ; sb_0__0__mux_tree_tapbuf_size2_3 mux_top_track_28 ( .in ( { top_left_grid_pin_1_[0] , chanx_right_in[15] } ) , .sram ( mux_tree_tapbuf_size2_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) , - .out ( chany_top_out[14] ) , .p0 ( optlc_net_105 ) ) ; + .out ( chany_top_out[14] ) , .p0 ( optlc_net_95 ) ) ; sb_0__0__mux_tree_tapbuf_size2_4 mux_top_track_44 ( .in ( { top_left_grid_pin_1_[0] , chanx_right_in[23] } ) , .sram ( mux_tree_tapbuf_size2_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 } ) , - .out ( chany_top_out[22] ) , .p0 ( optlc_net_105 ) ) ; + .out ( chany_top_out[22] ) , .p0 ( optlc_net_95 ) ) ; sb_0__0__mux_tree_tapbuf_size2_5 mux_right_track_14 ( .in ( { chany_top_in[6] , right_bottom_grid_pin_3_[0] } ) , .sram ( mux_tree_tapbuf_size2_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , - .out ( chanx_right_out[7] ) , .p0 ( optlc_net_105 ) ) ; + .out ( chanx_right_out[7] ) , .p0 ( optlc_net_95 ) ) ; sb_0__0__mux_tree_tapbuf_size2_6 mux_right_track_16 ( .in ( { chany_top_in[7] , right_bottom_grid_pin_5_[0] } ) , .sram ( mux_tree_tapbuf_size2_6_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 } ) , - .out ( chanx_right_out[8] ) , .p0 ( optlc_net_106 ) ) ; + .out ( chanx_right_out[8] ) , .p0 ( optlc_net_94 ) ) ; sb_0__0__mux_tree_tapbuf_size2_7 mux_right_track_18 ( .in ( { chany_top_in[8] , right_bottom_grid_pin_7_[0] } ) , .sram ( mux_tree_tapbuf_size2_7_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) , - .out ( chanx_right_out[9] ) , .p0 ( optlc_net_106 ) ) ; + .out ( chanx_right_out[9] ) , .p0 ( optlc_net_94 ) ) ; sb_0__0__mux_tree_tapbuf_size2_8 mux_right_track_20 ( .in ( { chany_top_in[9] , right_bottom_grid_pin_9_[0] } ) , .sram ( mux_tree_tapbuf_size2_8_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 } ) , - .out ( chanx_right_out[10] ) , .p0 ( optlc_net_106 ) ) ; + .out ( chanx_right_out[10] ) , .p0 ( optlc_net_96 ) ) ; sb_0__0__mux_tree_tapbuf_size2_9 mux_right_track_22 ( .in ( { chany_top_in[10] , right_bottom_grid_pin_11_[0] } ) , .sram ( mux_tree_tapbuf_size2_9_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) , - .out ( chanx_right_out[11] ) , .p0 ( optlc_net_106 ) ) ; + .out ( chanx_right_out[11] ) , .p0 ( optlc_net_96 ) ) ; sb_0__0__mux_tree_tapbuf_size2_10 mux_right_track_24 ( .in ( { chany_top_in[11] , right_bottom_grid_pin_13_[0] } ) , .sram ( mux_tree_tapbuf_size2_10_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 } ) , - .out ( chanx_right_out[12] ) , .p0 ( optlc_net_103 ) ) ; + .out ( chanx_right_out[12] ) , .p0 ( optlc_net_96 ) ) ; sb_0__0__mux_tree_tapbuf_size2_11 mux_right_track_26 ( .in ( { chany_top_in[12] , right_bottom_grid_pin_15_[0] } ) , .sram ( mux_tree_tapbuf_size2_11_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) , - .out ( chanx_right_out[13] ) , .p0 ( optlc_net_103 ) ) ; + .out ( chanx_right_out[13] ) , .p0 ( optlc_net_94 ) ) ; sb_0__0__mux_tree_tapbuf_size2_12 mux_right_track_30 ( .in ( { chany_top_in[14] , right_bottom_grid_pin_3_[0] } ) , .sram ( mux_tree_tapbuf_size2_12_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 } ) , - .out ( chanx_right_out[15] ) , .p0 ( optlc_net_103 ) ) ; + .out ( chanx_right_out[15] ) , .p0 ( optlc_net_98 ) ) ; sb_0__0__mux_tree_tapbuf_size2_13 mux_right_track_32 ( .in ( { chany_top_in[15] , right_bottom_grid_pin_5_[0] } ) , .sram ( mux_tree_tapbuf_size2_13_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) , - .out ( chanx_right_out[16] ) , .p0 ( optlc_net_103 ) ) ; + .out ( chanx_right_out[16] ) , .p0 ( optlc_net_94 ) ) ; sb_0__0__mux_tree_tapbuf_size2_14 mux_right_track_34 ( .in ( { chany_top_in[16] , right_bottom_grid_pin_7_[0] } ) , .sram ( mux_tree_tapbuf_size2_14_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 } ) , - .out ( chanx_right_out[17] ) , .p0 ( optlc_net_106 ) ) ; + .out ( chanx_right_out[17] ) , .p0 ( optlc_net_96 ) ) ; sb_0__0__mux_tree_tapbuf_size2_15 mux_right_track_36 ( .in ( { chany_top_in[17] , right_bottom_grid_pin_9_[0] } ) , .sram ( mux_tree_tapbuf_size2_15_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) , - .out ( chanx_right_out[18] ) , .p0 ( optlc_net_106 ) ) ; + .out ( chanx_right_out[18] ) , .p0 ( optlc_net_94 ) ) ; sb_0__0__mux_tree_tapbuf_size2_16 mux_right_track_38 ( .in ( { chany_top_in[18] , right_bottom_grid_pin_11_[0] } ) , .sram ( mux_tree_tapbuf_size2_16_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 } ) , - .out ( chanx_right_out[19] ) , .p0 ( optlc_net_103 ) ) ; + .out ( chanx_right_out[19] ) , .p0 ( optlc_net_94 ) ) ; sb_0__0__mux_tree_tapbuf_size2_17 mux_right_track_40 ( .in ( { chany_top_in[19] , right_bottom_grid_pin_13_[0] } ) , .sram ( mux_tree_tapbuf_size2_17_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) , - .out ( chanx_right_out[20] ) , .p0 ( optlc_net_103 ) ) ; + .out ( chanx_right_out[20] ) , .p0 ( optlc_net_96 ) ) ; sb_0__0__mux_tree_tapbuf_size2_18 mux_right_track_42 ( .in ( { chany_top_in[20] , right_bottom_grid_pin_15_[0] } ) , .sram ( mux_tree_tapbuf_size2_18_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 } ) , - .out ( chanx_right_out[21] ) , .p0 ( optlc_net_103 ) ) ; + .out ( chanx_right_out[21] ) , .p0 ( optlc_net_96 ) ) ; sb_0__0__mux_tree_tapbuf_size2_19 mux_right_track_46 ( .in ( { chany_top_in[22] , right_bottom_grid_pin_3_[0] } ) , .sram ( mux_tree_tapbuf_size2_19_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) , - .out ( chanx_right_out[23] ) , .p0 ( optlc_net_106 ) ) ; + .out ( chanx_right_out[23] ) , .p0 ( optlc_net_95 ) ) ; sb_0__0__mux_tree_tapbuf_size2_20 mux_right_track_48 ( .in ( { chany_top_in[23] , right_bottom_grid_pin_5_[0] } ) , .sram ( mux_tree_tapbuf_size2_20_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 } ) , - .out ( chanx_right_out[24] ) , .p0 ( optlc_net_105 ) ) ; + .out ( chanx_right_out[24] ) , .p0 ( optlc_net_95 ) ) ; sb_0__0__mux_tree_tapbuf_size2_21 mux_right_track_50 ( .in ( { chany_top_in[24] , right_bottom_grid_pin_7_[0] } ) , .sram ( mux_tree_tapbuf_size2_21_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) , - .out ( chanx_right_out[25] ) , .p0 ( optlc_net_105 ) ) ; + .out ( chanx_right_out[25] ) , .p0 ( optlc_net_95 ) ) ; sb_0__0__mux_tree_tapbuf_size2_22 mux_right_track_52 ( .in ( { chany_top_in[25] , right_bottom_grid_pin_9_[0] } ) , .sram ( mux_tree_tapbuf_size2_22_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 } ) , - .out ( chanx_right_out[26] ) , .p0 ( optlc_net_103 ) ) ; + .out ( chanx_right_out[26] ) , .p0 ( optlc_net_94 ) ) ; sb_0__0__mux_tree_tapbuf_size2_23 mux_right_track_54 ( .in ( { chany_top_in[26] , right_bottom_grid_pin_11_[0] } ) , .sram ( mux_tree_tapbuf_size2_23_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) , - .out ( chanx_right_out[27] ) , .p0 ( optlc_net_103 ) ) ; + .out ( chanx_right_out[27] ) , .p0 ( optlc_net_94 ) ) ; sb_0__0__mux_tree_tapbuf_size2_24 mux_right_track_56 ( .in ( { chany_top_in[27] , right_bottom_grid_pin_13_[0] } ) , .sram ( mux_tree_tapbuf_size2_24_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 } ) , - .out ( chanx_right_out[28] ) , .p0 ( optlc_net_103 ) ) ; + .out ( chanx_right_out[28] ) , .p0 ( optlc_net_98 ) ) ; sb_0__0__mux_tree_tapbuf_size2 mux_right_track_58 ( .in ( { chany_top_in[28] , right_bottom_grid_pin_15_[0] } ) , .sram ( mux_tree_tapbuf_size2_25_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) , - .out ( chanx_right_out[29] ) , .p0 ( optlc_net_103 ) ) ; + .out ( chanx_right_out[29] ) , .p0 ( optlc_net_94 ) ) ; sb_0__0__mux_tree_tapbuf_size2_mem_0 mem_top_track_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , @@ -39790,42 +39773,42 @@ sb_0__0__mux_tree_tapbuf_size4_0 mux_right_track_0 ( .sram ( mux_tree_tapbuf_size4_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 , SYNOPSYS_UNCONNECTED_55 } ) , - .out ( chanx_right_out[0] ) , .p0 ( optlc_net_104 ) ) ; + .out ( chanx_right_out[0] ) , .p0 ( optlc_net_97 ) ) ; sb_0__0__mux_tree_tapbuf_size4_1 mux_right_track_2 ( .in ( { chany_top_in[0] , right_bottom_grid_pin_3_[0] , right_bottom_grid_pin_9_[0] , right_bottom_grid_pin_15_[0] } ) , .sram ( mux_tree_tapbuf_size4_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_56 , SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 } ) , - .out ( chanx_right_out[1] ) , .p0 ( optlc_net_104 ) ) ; + .out ( chanx_right_out[1] ) , .p0 ( optlc_net_97 ) ) ; sb_0__0__mux_tree_tapbuf_size4_2 mux_right_track_4 ( .in ( { chany_top_in[1] , right_bottom_grid_pin_5_[0] , right_bottom_grid_pin_11_[0] , right_bottom_grid_pin_17_[0] } ) , .sram ( mux_tree_tapbuf_size4_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 , SYNOPSYS_UNCONNECTED_61 } ) , - .out ( chanx_right_out[2] ) , .p0 ( optlc_net_104 ) ) ; + .out ( chanx_right_out[2] ) , .p0 ( optlc_net_97 ) ) ; sb_0__0__mux_tree_tapbuf_size4_3 mux_right_track_6 ( .in ( { chany_top_in[2] , right_bottom_grid_pin_1_[0] , right_bottom_grid_pin_7_[0] , right_bottom_grid_pin_13_[0] } ) , .sram ( mux_tree_tapbuf_size4_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_62 , SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) , - .out ( chanx_right_out[3] ) , .p0 ( optlc_net_104 ) ) ; + .out ( chanx_right_out[3] ) , .p0 ( optlc_net_97 ) ) ; sb_0__0__mux_tree_tapbuf_size4_4 mux_right_track_8 ( .in ( { chany_top_in[3] , right_bottom_grid_pin_3_[0] , right_bottom_grid_pin_9_[0] , right_bottom_grid_pin_15_[0] } ) , .sram ( mux_tree_tapbuf_size4_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 , SYNOPSYS_UNCONNECTED_67 } ) , - .out ( chanx_right_out[4] ) , .p0 ( optlc_net_104 ) ) ; + .out ( chanx_right_out[4] ) , .p0 ( optlc_net_97 ) ) ; sb_0__0__mux_tree_tapbuf_size4 mux_right_track_10 ( .in ( { chany_top_in[4] , right_bottom_grid_pin_5_[0] , right_bottom_grid_pin_11_[0] , right_bottom_grid_pin_17_[0] } ) , .sram ( mux_tree_tapbuf_size4_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_68 , SYNOPSYS_UNCONNECTED_69 , SYNOPSYS_UNCONNECTED_70 } ) , - .out ( chanx_right_out[5] ) , .p0 ( optlc_net_104 ) ) ; + .out ( chanx_right_out[5] ) , .p0 ( optlc_net_97 ) ) ; sb_0__0__mux_tree_tapbuf_size4_mem_0 mem_right_track_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , @@ -39861,19 +39844,19 @@ sb_0__0__mux_tree_tapbuf_size3_0 mux_right_track_12 ( right_bottom_grid_pin_17_[0] } ) , .sram ( mux_tree_tapbuf_size3_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_71 , SYNOPSYS_UNCONNECTED_72 } ) , - .out ( chanx_right_out[6] ) , .p0 ( optlc_net_104 ) ) ; + .out ( chanx_right_out[6] ) , .p0 ( optlc_net_98 ) ) ; sb_0__0__mux_tree_tapbuf_size3_1 mux_right_track_28 ( .in ( { chany_top_in[13] , right_bottom_grid_pin_1_[0] , right_bottom_grid_pin_17_[0] } ) , .sram ( mux_tree_tapbuf_size3_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_73 , SYNOPSYS_UNCONNECTED_74 } ) , - .out ( chanx_right_out[14] ) , .p0 ( optlc_net_103 ) ) ; + .out ( chanx_right_out[14] ) , .p0 ( optlc_net_98 ) ) ; sb_0__0__mux_tree_tapbuf_size3 mux_right_track_44 ( .in ( { chany_top_in[21] , right_bottom_grid_pin_1_[0] , right_bottom_grid_pin_17_[0] } ) , .sram ( mux_tree_tapbuf_size3_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_75 , SYNOPSYS_UNCONNECTED_76 } ) , - .out ( chanx_right_out[22] ) , .p0 ( optlc_net_103 ) ) ; + .out ( chanx_right_out[22] ) , .p0 ( optlc_net_98 ) ) ; sb_0__0__mux_tree_tapbuf_size3_mem_0 mem_right_track_12 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) , @@ -39892,39 +39875,39 @@ sb_0__0__mux_tree_tapbuf_size3_mem mem_right_track_44 ( .pReset ( pReset ) , sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_E_in ) , .X ( pReset[0] ) ) ; sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_E_in ) , .X ( prog_clk[0] ) ) ; -sky130_fd_sc_hd__buf_6 FTB_36__35 ( .A ( chanx_right_in[0] ) , - .X ( ropt_net_139 ) ) ; -sky130_fd_sc_hd__buf_8 FTB_37__36 ( .A ( chanx_right_in[2] ) , - .X ( chany_top_out[1] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_36__35 ( .A ( chanx_right_in[0] ) , + .X ( chany_top_out[29] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_37__36 ( .A ( chanx_right_in[2] ) , + .X ( ropt_net_141 ) ) ; sky130_fd_sc_hd__buf_8 FTB_38__37 ( .A ( chanx_right_in[3] ) , .X ( chany_top_out[2] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chanx_right_in[5] ) , - .X ( chany_top_out[4] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_39__38 ( .A ( chanx_right_in[5] ) , + .X ( ropt_net_133 ) ) ; sky130_fd_sc_hd__buf_8 FTB_40__39 ( .A ( chanx_right_in[6] ) , .X ( chany_top_out[5] ) ) ; sky130_fd_sc_hd__buf_8 FTB_41__40 ( .A ( chanx_right_in[8] ) , .X ( chany_top_out[7] ) ) ; sky130_fd_sc_hd__buf_6 FTB_42__41 ( .A ( chanx_right_in[9] ) , .X ( chany_top_out[8] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_43__42 ( .A ( chanx_right_in[10] ) , - .X ( chany_top_out[9] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_43__42 ( .A ( chanx_right_in[10] ) , + .X ( ropt_net_134 ) ) ; sky130_fd_sc_hd__buf_8 FTB_44__43 ( .A ( chanx_right_in[11] ) , .X ( chany_top_out[10] ) ) ; sky130_fd_sc_hd__buf_8 FTB_45__44 ( .A ( chanx_right_in[12] ) , .X ( chany_top_out[11] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_46__45 ( .A ( chanx_right_in[13] ) , - .X ( chany_top_out[12] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_46__45 ( .A ( chanx_right_in[13] ) , + .X ( ropt_net_135 ) ) ; sky130_fd_sc_hd__buf_8 FTB_47__46 ( .A ( chanx_right_in[14] ) , .X ( chany_top_out[13] ) ) ; sky130_fd_sc_hd__buf_8 FTB_48__47 ( .A ( chanx_right_in[16] ) , .X ( chany_top_out[15] ) ) ; -sky130_fd_sc_hd__buf_6 FTB_49__48 ( .A ( chanx_right_in[17] ) , - .X ( ropt_net_140 ) ) ; +sky130_fd_sc_hd__buf_8 FTB_49__48 ( .A ( chanx_right_in[17] ) , + .X ( chany_top_out[16] ) ) ; sky130_fd_sc_hd__buf_8 FTB_50__49 ( .A ( chanx_right_in[18] ) , .X ( chany_top_out[17] ) ) ; sky130_fd_sc_hd__buf_8 FTB_51__50 ( .A ( chanx_right_in[19] ) , .X ( chany_top_out[18] ) ) ; -sky130_fd_sc_hd__buf_6 FTB_52__51 ( .A ( chanx_right_in[20] ) , +sky130_fd_sc_hd__buf_8 FTB_52__51 ( .A ( chanx_right_in[20] ) , .X ( chany_top_out[19] ) ) ; sky130_fd_sc_hd__buf_8 FTB_53__52 ( .A ( chanx_right_in[21] ) , .X ( chany_top_out[20] ) ) ; @@ -39942,18 +39925,24 @@ sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( chanx_right_in[28] ) , .X ( chany_top_out[27] ) ) ; sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( chanx_right_in[29] ) , .X ( chany_top_out[28] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_105 ( .LO ( SYNOPSYS_UNCONNECTED_77 ) , - .HI ( optlc_net_103 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_107 ( .LO ( SYNOPSYS_UNCONNECTED_78 ) , - .HI ( optlc_net_104 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_109 ( .LO ( SYNOPSYS_UNCONNECTED_79 ) , - .HI ( optlc_net_105 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_111 ( .LO ( SYNOPSYS_UNCONNECTED_80 ) , - .HI ( optlc_net_106 ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1303 ( .A ( ropt_net_139 ) , - .X ( chany_top_out[29] ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1304 ( .A ( ropt_net_140 ) , - .X ( chany_top_out[16] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_96 ( .LO ( SYNOPSYS_UNCONNECTED_77 ) , + .HI ( optlc_net_94 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_99 ( .LO ( SYNOPSYS_UNCONNECTED_78 ) , + .HI ( optlc_net_95 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_101 ( .LO ( SYNOPSYS_UNCONNECTED_79 ) , + .HI ( optlc_net_96 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_103 ( .LO ( SYNOPSYS_UNCONNECTED_80 ) , + .HI ( optlc_net_97 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_105 ( .LO ( SYNOPSYS_UNCONNECTED_81 ) , + .HI ( optlc_net_98 ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1299 ( .A ( ropt_net_133 ) , + .X ( chany_top_out[4] ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1300 ( .A ( ropt_net_134 ) , + .X ( chany_top_out[9] ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1301 ( .A ( ropt_net_135 ) , + .X ( chany_top_out[12] ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1307 ( .A ( ropt_net_141 ) , + .X ( chany_top_out[1] ) ) ; endmodule @@ -39971,16 +39960,16 @@ sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__buf_6 FTB_63__62 ( .A ( copt_net_196 ) , .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1614 ( .A ( copt_net_198 ) , - .X ( copt_net_195 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1615 ( .A ( copt_net_195 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1637 ( .A ( copt_net_200 ) , .X ( copt_net_196 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1616 ( .A ( copt_net_199 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1638 ( .A ( copt_net_199 ) , .X ( copt_net_197 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1617 ( .A ( copt_net_197 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1639 ( .A ( mem_out[1] ) , .X ( copt_net_198 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1618 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1640 ( .A ( copt_net_198 ) , .X ( copt_net_199 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1641 ( .A ( copt_net_197 ) , + .X ( copt_net_200 ) ) ; endmodule @@ -40101,10 +40090,10 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( aps_rename_521_ ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_129 ( .A ( BUF_net_131 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_130 ( .A ( BUF_net_131 ) , .Y ( p_abuf0 ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_131 ( .A ( aps_rename_521_ ) , - .Y ( BUF_net_131 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_130 ( .A ( BUF_net_132 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_131 ( .A ( BUF_net_132 ) , .Y ( p_abuf0 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_132 ( .A ( aps_rename_521_ ) , + .Y ( BUF_net_132 ) ) ; endmodule @@ -40131,10 +40120,10 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( aps_rename_520_ ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_126 ( .A ( BUF_net_128 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_127 ( .A ( BUF_net_128 ) , .Y ( p_abuf0 ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_128 ( .A ( aps_rename_520_ ) , - .Y ( BUF_net_128 ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_127 ( .A ( BUF_net_129 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_128 ( .A ( BUF_net_129 ) , .Y ( p_abuf0 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_129 ( .A ( aps_rename_520_ ) , + .Y ( BUF_net_129 ) ) ; endmodule @@ -40151,10 +40140,12 @@ output p_abuf1 ; sky130_fd_sc_hd__sdfrtp_1 sky130_fd_sc_hd__sdfrtp_1_0_ ( .D ( ff_D[0] ) , .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( ff_clk[0] ) , - .RESET_B ( ff_reset[0] ) , .Q ( p_abuf1 ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_81 ( .A ( BUF_net_83 ) , .Y ( ff_Q[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_82 ( .A ( BUF_net_83 ) , .Y ( p_abuf0 ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_83 ( .A ( p_abuf1 ) , .Y ( BUF_net_83 ) ) ; + .RESET_B ( ff_reset[0] ) , .Q ( aps_rename_519_ ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_81 ( .A ( BUF_net_84 ) , .Y ( ff_Q[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_82 ( .A ( BUF_net_84 ) , .Y ( p_abuf0 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_83 ( .A ( BUF_net_84 ) , .Y ( p_abuf1 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_84 ( .A ( aps_rename_519_ ) , + .Y ( BUF_net_84 ) ) ; endmodule @@ -40530,7 +40521,7 @@ module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric ( pReset , prog_clk , Test_en , fabric_in , fabric_reg_in , fabric_sc_in , fabric_cin , fabric_reset , fabric_clk , ccff_head , fabric_out , fabric_reg_out , fabric_sc_out , fabric_cout , ccff_tail , p_abuf0 , - p_abuf2 , p_abuf3 , p0 ) ; + p_abuf2 , p_abuf3 , p0 , p1 ) ; input [0:0] pReset ; input [0:0] prog_clk ; input [0:0] Test_en ; @@ -40550,6 +40541,7 @@ output p_abuf0 ; output p_abuf2 ; output p_abuf3 ; input p0 ; +input p1 ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ; @@ -40574,7 +40566,7 @@ grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ .frac_logic_cout ( { SYNOPSYS_UNCONNECTED_1 } ) , .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , - .p0 ( p0 ) ) ; + .p0 ( p1 ) ) ; grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_14 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( .Test_en ( Test_en ) , .ff_D ( mux_tree_size2_2_out ) , .ff_DI ( fabric_sc_in ) , .ff_reset ( fabric_reset ) , @@ -40592,14 +40584,14 @@ grid_clb_mux_tree_size2_44 mux_fabric_out_0 ( } ) , .sram ( mux_tree_size2_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 } ) , - .out ( fabric_out[0] ) , .p_abuf0 ( p_abuf2 ) , .p0 ( p0 ) ) ; + .out ( fabric_out[0] ) , .p_abuf0 ( p_abuf2 ) , .p0 ( p1 ) ) ; grid_clb_mux_tree_size2_45 mux_fabric_out_1 ( - .in ( { fabric_sc_out[0] , + .in ( { p_abuf1 , logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] } ) , .sram ( mux_tree_size2_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 } ) , - .out ( fabric_out[1] ) , .p_abuf0 ( p_abuf3 ) , .p0 ( p0 ) ) ; + .out ( fabric_out[1] ) , .p_abuf0 ( p_abuf3 ) , .p0 ( p1 ) ) ; grid_clb_mux_tree_size2_46 mux_ff_0_D_0 ( .in ( { logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] , @@ -40614,7 +40606,7 @@ grid_clb_mux_tree_size2 mux_ff_1_D_0 ( } ) , .sram ( mux_tree_size2_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_8 , SYNOPSYS_UNCONNECTED_9 } ) , - .out ( mux_tree_size2_3_out ) , .p0 ( p0 ) ) ; + .out ( mux_tree_size2_3_out ) , .p0 ( p1 ) ) ; grid_clb_mux_tree_size2_mem_44 mem_fabric_out_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , @@ -40639,7 +40631,7 @@ endmodule module grid_clb_logical_tile_clb_mode_default__fle ( pReset , prog_clk , Test_en , fle_in , fle_reg_in , fle_sc_in , fle_cin , fle_reset , fle_clk , ccff_head , fle_out , fle_reg_out , fle_sc_out , fle_cout , - ccff_tail , p_abuf0 , p_abuf1 , p_abuf2 , p1 ) ; + ccff_tail , p_abuf0 , p_abuf1 , p_abuf2 , p0 , p1 ) ; input [0:0] pReset ; input [0:0] prog_clk ; input [0:0] Test_en ; @@ -40658,6 +40650,7 @@ output [0:0] ccff_tail ; output p_abuf0 ; output p_abuf1 ; output p_abuf2 ; +input p0 ; input p1 ; grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( @@ -40670,7 +40663,7 @@ grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric logical_tile_c .fabric_reg_out ( fle_reg_out ) , .fabric_sc_out ( fle_sc_out ) , .fabric_cout ( fle_cout ) , .ccff_tail ( ccff_tail ) , .p_abuf0 ( p_abuf0 ) , .p_abuf2 ( p_abuf1 ) , .p_abuf3 ( p_abuf2 ) , - .p0 ( p1 ) ) ; + .p0 ( p0 ) , .p1 ( p1 ) ) ; endmodule @@ -40807,10 +40800,10 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( aps_rename_518_ ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_123 ( .A ( BUF_net_125 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_124 ( .A ( BUF_net_125 ) , .Y ( p_abuf0 ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_125 ( .A ( aps_rename_518_ ) , - .Y ( BUF_net_125 ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_124 ( .A ( BUF_net_126 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_125 ( .A ( BUF_net_126 ) , .Y ( p_abuf0 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_126 ( .A ( aps_rename_518_ ) , + .Y ( BUF_net_126 ) ) ; endmodule @@ -40820,13 +40813,13 @@ endmodule module grid_clb_mux_tree_size2_38 ( in , sram , sram_inv , out , p_abuf0 , - p3 ) ; + p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; output p_abuf0 ; -input p3 ; +input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; @@ -40834,13 +40827,13 @@ grid_clb_const1_38 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p3 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( aps_rename_517_ ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_120 ( .A ( BUF_net_122 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_121 ( .A ( BUF_net_122 ) , .Y ( p_abuf0 ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_122 ( .A ( aps_rename_517_ ) , - .Y ( BUF_net_122 ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_121 ( .A ( BUF_net_123 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_122 ( .A ( BUF_net_123 ) , .Y ( p_abuf0 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_123 ( .A ( aps_rename_517_ ) , + .Y ( BUF_net_123 ) ) ; endmodule @@ -40911,12 +40904,12 @@ output [0:0] const1 ; endmodule -module grid_clb_mux_tree_size2_37 ( in , sram , sram_inv , out , p3 ) ; +module grid_clb_mux_tree_size2_37 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; -input p3 ; +input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; @@ -40924,7 +40917,7 @@ grid_clb_const1_37 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p3 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; endmodule @@ -41165,7 +41158,7 @@ endmodule module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_6 ( pReset , prog_clk , frac_logic_in , frac_logic_cin , ccff_head , - frac_logic_out , frac_logic_cout , ccff_tail , p3 ) ; + frac_logic_out , frac_logic_cout , ccff_tail , p0 , p3 ) ; input [0:0] pReset ; input [0:0] prog_clk ; input [0:3] frac_logic_in ; @@ -41174,6 +41167,7 @@ input [0:0] ccff_head ; output [0:1] frac_logic_out ; output [0:0] frac_logic_cout ; output [0:0] ccff_tail ; +input p0 ; input p3 ; wire [0:0] direct_interc_5_out ; @@ -41215,7 +41209,7 @@ grid_clb_mux_tree_size2_37 mux_frac_lut4_0_in_2 ( .in ( { frac_logic_cin[0] , frac_logic_in[2] } ) , .sram ( mux_tree_size2_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 } ) , - .out ( mux_tree_size2_1_out ) , .p3 ( p3 ) ) ; + .out ( mux_tree_size2_1_out ) , .p0 ( p0 ) ) ; grid_clb_mux_tree_size2_mem_36 mem_frac_logic_out_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , @@ -41276,7 +41270,7 @@ grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ .frac_logic_cout ( { SYNOPSYS_UNCONNECTED_1 } ) , .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , - .p3 ( p3 ) ) ; + .p0 ( p1 ) , .p3 ( p3 ) ) ; grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_12 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( .Test_en ( Test_en ) , .ff_D ( mux_tree_size2_2_out ) , .ff_DI ( fabric_sc_in ) , .ff_reset ( fabric_reset ) , @@ -41294,7 +41288,7 @@ grid_clb_mux_tree_size2_38 mux_fabric_out_0 ( } ) , .sram ( mux_tree_size2_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 } ) , - .out ( fabric_out[0] ) , .p_abuf0 ( p_abuf0 ) , .p3 ( p3 ) ) ; + .out ( fabric_out[0] ) , .p_abuf0 ( p_abuf0 ) , .p0 ( p1 ) ) ; grid_clb_mux_tree_size2_39 mux_fabric_out_1 ( .in ( { fabric_sc_out[0] , logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] @@ -41316,7 +41310,7 @@ grid_clb_mux_tree_size2_41 mux_ff_1_D_0 ( } ) , .sram ( mux_tree_size2_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_8 , SYNOPSYS_UNCONNECTED_9 } ) , - .out ( mux_tree_size2_3_out ) , .p0 ( p1 ) ) ; + .out ( mux_tree_size2_3_out ) , .p0 ( p0 ) ) ; grid_clb_mux_tree_size2_mem_38 mem_fabric_out_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , @@ -41469,12 +41463,12 @@ output [0:0] const1 ; endmodule -module grid_clb_mux_tree_size2_34 ( in , sram , sram_inv , out , p0 ) ; +module grid_clb_mux_tree_size2_34 ( in , sram , sram_inv , out , p3 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; -input p0 ; +input p3 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; @@ -41482,7 +41476,7 @@ grid_clb_const1_34 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p3 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; endmodule @@ -41510,10 +41504,10 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p3 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( aps_rename_516_ ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_117 ( .A ( BUF_net_119 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_118 ( .A ( BUF_net_119 ) , .Y ( p_abuf0 ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_119 ( .A ( aps_rename_516_ ) , - .Y ( BUF_net_119 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_118 ( .A ( BUF_net_120 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_119 ( .A ( BUF_net_120 ) , .Y ( p_abuf0 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_120 ( .A ( aps_rename_516_ ) , + .Y ( BUF_net_120 ) ) ; endmodule @@ -41540,10 +41534,10 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p3 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( aps_rename_515_ ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_114 ( .A ( BUF_net_116 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_115 ( .A ( BUF_net_116 ) , .Y ( p_abuf0 ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_116 ( .A ( aps_rename_515_ ) , - .Y ( BUF_net_116 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_115 ( .A ( BUF_net_117 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_116 ( .A ( BUF_net_117 ) , .Y ( p_abuf0 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_117 ( .A ( aps_rename_515_ ) , + .Y ( BUF_net_117 ) ) ; endmodule @@ -41934,7 +41928,7 @@ module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_5 ( pReset , prog_clk , Test_en , fabric_in , fabric_reg_in , fabric_sc_in , fabric_cin , fabric_reset , fabric_clk , ccff_head , fabric_out , fabric_reg_out , fabric_sc_out , fabric_cout , ccff_tail , p_abuf0 , - p_abuf1 , p0 , p3 ) ; + p_abuf1 , p3 ) ; input [0:0] pReset ; input [0:0] prog_clk ; input [0:0] Test_en ; @@ -41952,7 +41946,6 @@ output [0:0] fabric_cout ; output [0:0] ccff_tail ; output p_abuf0 ; output p_abuf1 ; -input p0 ; input p3 ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ; @@ -42010,7 +42003,7 @@ grid_clb_mux_tree_size2_34 mux_ff_0_D_0 ( fabric_reg_in[0] } ) , .sram ( mux_tree_size2_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_6 , SYNOPSYS_UNCONNECTED_7 } ) , - .out ( mux_tree_size2_2_out ) , .p0 ( p0 ) ) ; + .out ( mux_tree_size2_2_out ) , .p3 ( p3 ) ) ; grid_clb_mux_tree_size2_35 mux_ff_1_D_0 ( .in ( { logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] , @@ -42043,7 +42036,7 @@ endmodule module grid_clb_logical_tile_clb_mode_default__fle_5 ( pReset , prog_clk , Test_en , fle_in , fle_reg_in , fle_sc_in , fle_cin , fle_reset , fle_clk , ccff_head , fle_out , fle_reg_out , fle_sc_out , fle_cout , - ccff_tail , p_abuf0 , p_abuf1 , p0 , p3 ) ; + ccff_tail , p_abuf0 , p_abuf1 , p3 ) ; input [0:0] pReset ; input [0:0] prog_clk ; input [0:0] Test_en ; @@ -42061,7 +42054,6 @@ output [0:0] fle_cout ; output [0:0] ccff_tail ; output p_abuf0 ; output p_abuf1 ; -input p0 ; input p3 ; grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_5 logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( @@ -42074,7 +42066,7 @@ grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_5 logical_tile .fabric_reg_out ( fle_reg_out ) , .fabric_sc_out ( fle_sc_out ) , .fabric_cout ( { SYNOPSYS_UNCONNECTED_2 } ) , .ccff_tail ( ccff_tail ) , .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , - .p0 ( p0 ) , .p3 ( p3 ) ) ; + .p3 ( p3 ) ) ; endmodule @@ -42147,12 +42139,12 @@ output [0:0] const1 ; endmodule -module grid_clb_mux_tree_size2_29 ( in , sram , sram_inv , out , p0 ) ; +module grid_clb_mux_tree_size2_29 ( in , sram , sram_inv , out , p3 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; -input p0 ; +input p3 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; @@ -42160,7 +42152,7 @@ grid_clb_const1_29 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p3 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; endmodule @@ -42170,12 +42162,12 @@ output [0:0] const1 ; endmodule -module grid_clb_mux_tree_size2_28 ( in , sram , sram_inv , out , p0 ) ; +module grid_clb_mux_tree_size2_28 ( in , sram , sram_inv , out , p2 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; -input p0 ; +input p2 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; @@ -42183,7 +42175,7 @@ grid_clb_const1_28 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; endmodule @@ -42211,10 +42203,10 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p3 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( aps_rename_514_ ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_111 ( .A ( BUF_net_113 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_112 ( .A ( BUF_net_113 ) , .Y ( p_abuf0 ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_113 ( .A ( aps_rename_514_ ) , - .Y ( BUF_net_113 ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_112 ( .A ( BUF_net_114 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_113 ( .A ( BUF_net_114 ) , .Y ( p_abuf0 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_114 ( .A ( aps_rename_514_ ) , + .Y ( BUF_net_114 ) ) ; endmodule @@ -42224,13 +42216,13 @@ endmodule module grid_clb_mux_tree_size2_26 ( in , sram , sram_inv , out , p_abuf0 , - p0 ) ; + p3 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; output p_abuf0 ; -input p0 ; +input p3 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; @@ -42238,13 +42230,13 @@ grid_clb_const1_26 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p3 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( aps_rename_513_ ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_108 ( .A ( BUF_net_110 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_109 ( .A ( BUF_net_110 ) , .Y ( p_abuf0 ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_110 ( .A ( aps_rename_513_ ) , - .Y ( BUF_net_110 ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_109 ( .A ( BUF_net_111 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_110 ( .A ( BUF_net_111 ) , .Y ( p_abuf0 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_111 ( .A ( aps_rename_513_ ) , + .Y ( BUF_net_111 ) ) ; endmodule @@ -42338,12 +42330,12 @@ output [0:0] const1 ; endmodule -module grid_clb_mux_tree_size2_24 ( in , sram , sram_inv , out , p0 ) ; +module grid_clb_mux_tree_size2_24 ( in , sram , sram_inv , out , p2 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; -input p0 ; +input p2 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; @@ -42351,7 +42343,7 @@ grid_clb_const1_24 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; endmodule @@ -42569,7 +42561,7 @@ endmodule module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_4 ( pReset , prog_clk , frac_logic_in , frac_logic_cin , ccff_head , - frac_logic_out , frac_logic_cout , ccff_tail , p0 , p2 ) ; + frac_logic_out , frac_logic_cout , ccff_tail , p2 ) ; input [0:0] pReset ; input [0:0] prog_clk ; input [0:3] frac_logic_in ; @@ -42578,7 +42570,6 @@ input [0:0] ccff_head ; output [0:1] frac_logic_out ; output [0:0] frac_logic_cout ; output [0:0] ccff_tail ; -input p0 ; input p2 ; wire [0:0] direct_interc_5_out ; @@ -42615,7 +42606,7 @@ grid_clb_mux_tree_size2_24 mux_frac_logic_out_0 ( } ) , .sram ( mux_tree_size2_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 } ) , - .out ( frac_logic_out[0] ) , .p0 ( p0 ) ) ; + .out ( frac_logic_out[0] ) , .p2 ( p2 ) ) ; grid_clb_mux_tree_size2_25 mux_frac_lut4_0_in_2 ( .in ( { frac_logic_cin[0] , frac_logic_in[2] } ) , .sram ( mux_tree_size2_1_sram ) , @@ -42636,7 +42627,7 @@ module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_4 ( pReset , prog_clk , Test_en , fabric_in , fabric_reg_in , fabric_sc_in , fabric_cin , fabric_reset , fabric_clk , ccff_head , fabric_out , fabric_reg_out , fabric_sc_out , fabric_cout , ccff_tail , p_abuf0 , - p_abuf1 , p0 , p2 , p3 ) ; + p_abuf1 , p2 , p3 ) ; input [0:0] pReset ; input [0:0] prog_clk ; input [0:0] Test_en ; @@ -42654,7 +42645,6 @@ output [0:0] fabric_cout ; output [0:0] ccff_tail ; output p_abuf0 ; output p_abuf1 ; -input p0 ; input p2 ; input p3 ; @@ -42681,7 +42671,7 @@ grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ .frac_logic_cout ( { SYNOPSYS_UNCONNECTED_1 } ) , .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , - .p0 ( p0 ) , .p2 ( p2 ) ) ; + .p2 ( p2 ) ) ; grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_8 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( .Test_en ( Test_en ) , .ff_D ( mux_tree_size2_2_out ) , .ff_DI ( fabric_sc_in ) , .ff_reset ( fabric_reset ) , @@ -42699,7 +42689,7 @@ grid_clb_mux_tree_size2_26 mux_fabric_out_0 ( } ) , .sram ( mux_tree_size2_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 } ) , - .out ( fabric_out[0] ) , .p_abuf0 ( p_abuf0 ) , .p0 ( p0 ) ) ; + .out ( fabric_out[0] ) , .p_abuf0 ( p_abuf0 ) , .p3 ( p3 ) ) ; grid_clb_mux_tree_size2_27 mux_fabric_out_1 ( .in ( { fabric_sc_out[0] , logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] @@ -42713,7 +42703,7 @@ grid_clb_mux_tree_size2_28 mux_ff_0_D_0 ( fabric_reg_in[0] } ) , .sram ( mux_tree_size2_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_6 , SYNOPSYS_UNCONNECTED_7 } ) , - .out ( mux_tree_size2_2_out ) , .p0 ( p0 ) ) ; + .out ( mux_tree_size2_2_out ) , .p2 ( p2 ) ) ; grid_clb_mux_tree_size2_29 mux_ff_1_D_0 ( .in ( { logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] , @@ -42721,7 +42711,7 @@ grid_clb_mux_tree_size2_29 mux_ff_1_D_0 ( } ) , .sram ( mux_tree_size2_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_8 , SYNOPSYS_UNCONNECTED_9 } ) , - .out ( mux_tree_size2_3_out ) , .p0 ( p0 ) ) ; + .out ( mux_tree_size2_3_out ) , .p3 ( p3 ) ) ; grid_clb_mux_tree_size2_mem_26 mem_fabric_out_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , @@ -42746,7 +42736,7 @@ endmodule module grid_clb_logical_tile_clb_mode_default__fle_4 ( pReset , prog_clk , Test_en , fle_in , fle_reg_in , fle_sc_in , fle_cin , fle_reset , fle_clk , ccff_head , fle_out , fle_reg_out , fle_sc_out , fle_cout , - ccff_tail , p_abuf0 , p_abuf1 , p0 , p2 , p3 ) ; + ccff_tail , p_abuf0 , p_abuf1 , p2 , p3 ) ; input [0:0] pReset ; input [0:0] prog_clk ; input [0:0] Test_en ; @@ -42764,7 +42754,6 @@ output [0:0] fle_cout ; output [0:0] ccff_tail ; output p_abuf0 ; output p_abuf1 ; -input p0 ; input p2 ; input p3 ; @@ -42778,7 +42767,7 @@ grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_4 logical_tile .fabric_reg_out ( fle_reg_out ) , .fabric_sc_out ( fle_sc_out ) , .fabric_cout ( { SYNOPSYS_UNCONNECTED_2 } ) , .ccff_tail ( ccff_tail ) , .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , - .p0 ( p0 ) , .p2 ( p2 ) , .p3 ( p3 ) ) ; + .p2 ( p2 ) , .p3 ( p3 ) ) ; endmodule @@ -42915,10 +42904,10 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( aps_rename_512_ ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_105 ( .A ( BUF_net_107 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_106 ( .A ( BUF_net_107 ) , .Y ( p_abuf0 ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_107 ( .A ( aps_rename_512_ ) , - .Y ( BUF_net_107 ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_106 ( .A ( BUF_net_108 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_107 ( .A ( BUF_net_108 ) , .Y ( p_abuf0 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_108 ( .A ( aps_rename_512_ ) , + .Y ( BUF_net_108 ) ) ; endmodule @@ -42945,10 +42934,10 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( aps_rename_511_ ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_102 ( .A ( BUF_net_104 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_103 ( .A ( BUF_net_104 ) , .Y ( p_abuf0 ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_104 ( .A ( aps_rename_511_ ) , - .Y ( BUF_net_104 ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_103 ( .A ( BUF_net_105 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_104 ( .A ( BUF_net_105 ) , .Y ( p_abuf0 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_105 ( .A ( aps_rename_511_ ) , + .Y ( BUF_net_105 ) ) ; endmodule @@ -43597,13 +43586,13 @@ endmodule module grid_clb_mux_tree_size2_15 ( in , sram , sram_inv , out , p_abuf0 , - p1 ) ; + p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; output p_abuf0 ; -input p1 ; +input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; @@ -43611,13 +43600,13 @@ grid_clb_const1_15 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p1 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( aps_rename_510_ ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_99 ( .A ( BUF_net_101 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_100 ( .A ( BUF_net_101 ) , .Y ( p_abuf0 ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_101 ( .A ( aps_rename_510_ ) , - .Y ( BUF_net_101 ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_100 ( .A ( BUF_net_102 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_101 ( .A ( BUF_net_102 ) , .Y ( p_abuf0 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_102 ( .A ( aps_rename_510_ ) , + .Y ( BUF_net_102 ) ) ; endmodule @@ -43644,10 +43633,10 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p4 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( aps_rename_509_ ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_96 ( .A ( BUF_net_98 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_97 ( .A ( BUF_net_98 ) , .Y ( p_abuf0 ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_98 ( .A ( aps_rename_509_ ) , - .Y ( BUF_net_98 ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_97 ( .A ( BUF_net_99 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_98 ( .A ( BUF_net_99 ) , .Y ( p_abuf0 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_99 ( .A ( aps_rename_509_ ) , + .Y ( BUF_net_99 ) ) ; endmodule @@ -43741,12 +43730,12 @@ output [0:0] const1 ; endmodule -module grid_clb_mux_tree_size2_12 ( in , sram , sram_inv , out , p2 ) ; +module grid_clb_mux_tree_size2_12 ( in , sram , sram_inv , out , p4 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; -input p2 ; +input p4 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; @@ -43754,7 +43743,7 @@ grid_clb_const1_12 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p4 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; endmodule @@ -43972,7 +43961,7 @@ endmodule module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_2 ( pReset , prog_clk , frac_logic_in , frac_logic_cin , ccff_head , - frac_logic_out , frac_logic_cout , ccff_tail , p2 , p4 ) ; + frac_logic_out , frac_logic_cout , ccff_tail , p4 ) ; input [0:0] pReset ; input [0:0] prog_clk ; input [0:3] frac_logic_in ; @@ -43981,7 +43970,6 @@ input [0:0] ccff_head ; output [0:1] frac_logic_out ; output [0:0] frac_logic_cout ; output [0:0] ccff_tail ; -input p2 ; input p4 ; wire [0:0] direct_interc_5_out ; @@ -44018,7 +44006,7 @@ grid_clb_mux_tree_size2_12 mux_frac_logic_out_0 ( } ) , .sram ( mux_tree_size2_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 } ) , - .out ( frac_logic_out[0] ) , .p2 ( p2 ) ) ; + .out ( frac_logic_out[0] ) , .p4 ( p4 ) ) ; grid_clb_mux_tree_size2_13 mux_frac_lut4_0_in_2 ( .in ( { frac_logic_cin[0] , frac_logic_in[2] } ) , .sram ( mux_tree_size2_1_sram ) , @@ -44039,7 +44027,7 @@ module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_2 ( pReset , prog_clk , Test_en , fabric_in , fabric_reg_in , fabric_sc_in , fabric_cin , fabric_reset , fabric_clk , ccff_head , fabric_out , fabric_reg_out , fabric_sc_out , fabric_cout , ccff_tail , p_abuf0 , - p_abuf1 , p1 , p2 , p4 ) ; + p_abuf1 , p0 , p2 , p4 ) ; input [0:0] pReset ; input [0:0] prog_clk ; input [0:0] Test_en ; @@ -44057,7 +44045,7 @@ output [0:0] fabric_cout ; output [0:0] ccff_tail ; output p_abuf0 ; output p_abuf1 ; -input p1 ; +input p0 ; input p2 ; input p4 ; @@ -44084,7 +44072,7 @@ grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ .frac_logic_cout ( { SYNOPSYS_UNCONNECTED_1 } ) , .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , - .p2 ( p2 ) , .p4 ( p4 ) ) ; + .p4 ( p4 ) ) ; grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_4 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( .Test_en ( Test_en ) , .ff_D ( mux_tree_size2_2_out ) , .ff_DI ( fabric_sc_in ) , .ff_reset ( fabric_reset ) , @@ -44109,7 +44097,7 @@ grid_clb_mux_tree_size2_15 mux_fabric_out_1 ( } ) , .sram ( mux_tree_size2_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 } ) , - .out ( fabric_out[1] ) , .p_abuf0 ( p_abuf1 ) , .p1 ( p1 ) ) ; + .out ( fabric_out[1] ) , .p_abuf0 ( p_abuf1 ) , .p0 ( p0 ) ) ; grid_clb_mux_tree_size2_16 mux_ff_0_D_0 ( .in ( { logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] , @@ -44149,7 +44137,7 @@ endmodule module grid_clb_logical_tile_clb_mode_default__fle_2 ( pReset , prog_clk , Test_en , fle_in , fle_reg_in , fle_sc_in , fle_cin , fle_reset , fle_clk , ccff_head , fle_out , fle_reg_out , fle_sc_out , fle_cout , - ccff_tail , p_abuf0 , p_abuf1 , p1 , p2 , p4 ) ; + ccff_tail , p_abuf0 , p_abuf1 , p0 , p2 , p4 ) ; input [0:0] pReset ; input [0:0] prog_clk ; input [0:0] Test_en ; @@ -44167,7 +44155,7 @@ output [0:0] fle_cout ; output [0:0] ccff_tail ; output p_abuf0 ; output p_abuf1 ; -input p1 ; +input p0 ; input p2 ; input p4 ; @@ -44181,7 +44169,7 @@ grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_2 logical_tile .fabric_reg_out ( fle_reg_out ) , .fabric_sc_out ( fle_sc_out ) , .fabric_cout ( { SYNOPSYS_UNCONNECTED_2 } ) , .ccff_tail ( ccff_tail ) , .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , - .p1 ( p1 ) , .p2 ( p2 ) , .p4 ( p4 ) ) ; + .p0 ( p0 ) , .p2 ( p2 ) , .p4 ( p4 ) ) ; endmodule @@ -44277,12 +44265,12 @@ output [0:0] const1 ; endmodule -module grid_clb_mux_tree_size2_10 ( in , sram , sram_inv , out , p1 ) ; +module grid_clb_mux_tree_size2_10 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; -input p1 ; +input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; @@ -44290,7 +44278,7 @@ grid_clb_const1_10 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p1 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; endmodule @@ -44317,10 +44305,10 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( aps_rename_508_ ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_93 ( .A ( BUF_net_95 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_94 ( .A ( BUF_net_95 ) , .Y ( p_abuf0 ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_95 ( .A ( aps_rename_508_ ) , - .Y ( BUF_net_95 ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_94 ( .A ( BUF_net_96 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_95 ( .A ( BUF_net_96 ) , .Y ( p_abuf0 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_96 ( .A ( aps_rename_508_ ) , + .Y ( BUF_net_96 ) ) ; endmodule @@ -44329,13 +44317,13 @@ output [0:0] const1 ; endmodule -module grid_clb_mux_tree_size2_8 ( in , sram , sram_inv , out , p_abuf0 , p1 ) ; +module grid_clb_mux_tree_size2_8 ( in , sram , sram_inv , out , p_abuf0 , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; output p_abuf0 ; -input p1 ; +input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; @@ -44343,13 +44331,13 @@ grid_clb_const1_8 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p1 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( aps_rename_507_ ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_90 ( .A ( BUF_net_92 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_91 ( .A ( BUF_net_92 ) , .Y ( p_abuf0 ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_92 ( .A ( aps_rename_507_ ) , - .Y ( BUF_net_92 ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_91 ( .A ( BUF_net_93 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_92 ( .A ( BUF_net_93 ) , .Y ( p_abuf0 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_93 ( .A ( aps_rename_507_ ) , + .Y ( BUF_net_93 ) ) ; endmodule @@ -44802,7 +44790,7 @@ grid_clb_mux_tree_size2_8 mux_fabric_out_0 ( } ) , .sram ( mux_tree_size2_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 } ) , - .out ( fabric_out[0] ) , .p_abuf0 ( p_abuf0 ) , .p1 ( p1 ) ) ; + .out ( fabric_out[0] ) , .p_abuf0 ( p_abuf0 ) , .p0 ( p0 ) ) ; grid_clb_mux_tree_size2_9 mux_fabric_out_1 ( .in ( { fabric_sc_out[0] , logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] @@ -44816,7 +44804,7 @@ grid_clb_mux_tree_size2_10 mux_ff_0_D_0 ( fabric_reg_in[0] } ) , .sram ( mux_tree_size2_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_6 , SYNOPSYS_UNCONNECTED_7 } ) , - .out ( mux_tree_size2_2_out ) , .p1 ( p1 ) ) ; + .out ( mux_tree_size2_2_out ) , .p0 ( p0 ) ) ; grid_clb_mux_tree_size2_11 mux_ff_1_D_0 ( .in ( { logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] , @@ -45016,10 +45004,10 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p1 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( aps_rename_506_ ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_87 ( .A ( BUF_net_89 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_88 ( .A ( BUF_net_89 ) , .Y ( p_abuf0 ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_89 ( .A ( aps_rename_506_ ) , - .Y ( BUF_net_89 ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_88 ( .A ( BUF_net_90 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_89 ( .A ( BUF_net_90 ) , .Y ( p_abuf0 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_90 ( .A ( aps_rename_506_ ) , + .Y ( BUF_net_90 ) ) ; endmodule @@ -45045,10 +45033,10 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p1 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( aps_rename_505_ ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_84 ( .A ( BUF_net_86 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_85 ( .A ( BUF_net_86 ) , .Y ( p_abuf0 ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_86 ( .A ( aps_rename_505_ ) , - .Y ( BUF_net_86 ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_85 ( .A ( BUF_net_87 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_86 ( .A ( BUF_net_87 ) , .Y ( p_abuf0 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_87 ( .A ( aps_rename_505_ ) , + .Y ( BUF_net_87 ) ) ; endmodule @@ -45193,7 +45181,7 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:16] mem_out ; -sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_200 ) , +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_201 ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; @@ -45228,20 +45216,20 @@ sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_15_ ( .D ( mem_out[14] ) , sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_16_ ( .D ( mem_out[15] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[16] ) ) ; sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[16] ) , .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1607 ( .A ( ccff_head[0] ) , - .X ( copt_net_188 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1608 ( .A ( copt_net_191 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1630 ( .A ( ccff_head[0] ) , .X ( copt_net_189 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1609 ( .A ( copt_net_192 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1631 ( .A ( copt_net_194 ) , .X ( copt_net_190 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1610 ( .A ( copt_net_190 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1632 ( .A ( copt_net_190 ) , .X ( copt_net_191 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1611 ( .A ( copt_net_188 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1633 ( .A ( copt_net_189 ) , .X ( copt_net_192 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1612 ( .A ( copt_net_189 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1634 ( .A ( copt_net_192 ) , .X ( copt_net_193 ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 ropt_h_inst_1619 ( .A ( copt_net_193 ) , - .X ( ropt_net_200 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1635 ( .A ( copt_net_193 ) , + .X ( copt_net_194 ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 ropt_h_inst_1642 ( .A ( copt_net_191 ) , + .X ( ropt_net_201 ) ) ; endmodule @@ -45722,7 +45710,7 @@ grid_clb_logical_tile_clb_mode_default__fle_2 logical_tile_clb_mode_default__fle .fle_sc_out ( logical_tile_clb_mode_default__fle_2_fle_sc_out ) , .fle_cout ( { SYNOPSYS_UNCONNECTED_6 } ) , .ccff_tail ( logical_tile_clb_mode_default__fle_2_ccff_tail ) , - .p_abuf0 ( p_abuf5 ) , .p_abuf1 ( p_abuf6 ) , .p1 ( p2 ) , .p2 ( p3 ) , + .p_abuf0 ( p_abuf5 ) , .p_abuf1 ( p_abuf6 ) , .p0 ( p0 ) , .p2 ( p3 ) , .p4 ( p5 ) ) ; grid_clb_logical_tile_clb_mode_default__fle_3 logical_tile_clb_mode_default__fle_3 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , @@ -45751,8 +45739,7 @@ grid_clb_logical_tile_clb_mode_default__fle_4 logical_tile_clb_mode_default__fle .fle_sc_out ( logical_tile_clb_mode_default__fle_4_fle_sc_out ) , .fle_cout ( { SYNOPSYS_UNCONNECTED_10 } ) , .ccff_tail ( logical_tile_clb_mode_default__fle_4_ccff_tail ) , - .p_abuf0 ( p_abuf9 ) , .p_abuf1 ( p_abuf10 ) , .p0 ( p0 ) , .p2 ( p3 ) , - .p3 ( p4 ) ) ; + .p_abuf0 ( p_abuf9 ) , .p_abuf1 ( p_abuf10 ) , .p2 ( p3 ) , .p3 ( p4 ) ) ; grid_clb_logical_tile_clb_mode_default__fle_5 logical_tile_clb_mode_default__fle_5 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .fle_in ( { clb_I5[0] , clb_I5[1] , clb_I5i[0] , clb_I5i[1] } ) , @@ -45766,7 +45753,7 @@ grid_clb_logical_tile_clb_mode_default__fle_5 logical_tile_clb_mode_default__fle .fle_sc_out ( logical_tile_clb_mode_default__fle_5_fle_sc_out ) , .fle_cout ( { SYNOPSYS_UNCONNECTED_12 } ) , .ccff_tail ( logical_tile_clb_mode_default__fle_5_ccff_tail ) , - .p_abuf0 ( p_abuf11 ) , .p_abuf1 ( p_abuf12 ) , .p0 ( p0 ) , .p3 ( p4 ) ) ; + .p_abuf0 ( p_abuf11 ) , .p_abuf1 ( p_abuf12 ) , .p3 ( p4 ) ) ; grid_clb_logical_tile_clb_mode_default__fle_6 logical_tile_clb_mode_default__fle_6 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .fle_in ( { clb_I6[0] , clb_I6[1] , clb_I6i[0] , clb_I6i[1] } ) , @@ -45793,7 +45780,7 @@ grid_clb_logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_7 .fle_out ( { clb_O[15] , clb_O[14] } ) , .fle_reg_out ( clb_reg_out ) , .fle_sc_out ( clb_sc_out ) , .fle_cout ( clb_cout ) , .ccff_tail ( ccff_tail ) , .p_abuf0 ( p_abuf0 ) , - .p_abuf1 ( p_abuf15 ) , .p_abuf2 ( p_abuf16 ) , .p1 ( p1 ) ) ; + .p_abuf1 ( p_abuf15 ) , .p_abuf2 ( p_abuf16 ) , .p0 ( p0 ) , .p1 ( p1 ) ) ; endmodule @@ -46024,9 +46011,9 @@ grid_clb_logical_tile_clb_mode_clb_ logical_tile_clb_mode_clb__0 ( .p_abuf13 ( right_width_0_height_0__pin_49_lower[0] ) , .p_abuf14 ( right_width_0_height_0__pin_48_lower[0] ) , .p_abuf15 ( right_width_0_height_0__pin_51_lower[0] ) , - .p_abuf16 ( p_abuf16 ) , .p0 ( optlc_net_178 ) , .p1 ( optlc_net_179 ) , - .p2 ( optlc_net_180 ) , .p3 ( optlc_net_181 ) , .p4 ( optlc_net_182 ) , - .p5 ( optlc_net_183 ) ) ; + .p_abuf16 ( p_abuf16 ) , .p0 ( optlc_net_179 ) , .p1 ( optlc_net_180 ) , + .p2 ( optlc_net_181 ) , .p3 ( optlc_net_182 ) , .p4 ( optlc_net_183 ) , + .p5 ( optlc_net_184 ) ) ; sky130_fd_sc_hd__buf_2 Test_en_FTB00 ( .A ( Test_en_W_in ) , .X ( Test_en[0] ) ) ; sky130_fd_sc_hd__buf_1 Test_en_W_FTB01 ( .A ( Test_en_W_in ) , @@ -46042,13 +46029,13 @@ sky130_fd_sc_hd__buf_1 Reset_E_FTB01 ( .A ( Reset_W_in ) , sky130_fd_sc_hd__buf_6 prog_clk_0_FTB00 ( .A ( prog_clk_0_S_in ) , .X ( prog_clk_0 ) ) ; sky130_fd_sc_hd__clkbuf_1 prog_clk_0_S_FTB01 ( .A ( prog_clk_0_S_in ) , - .X ( ctsbuf_net_1184 ) ) ; -sky130_fd_sc_hd__clkbuf_1 prog_clk_0_E_FTB01 ( .A ( prog_clk_0_S_in ) , - .X ( ctsbuf_net_2185 ) ) ; -sky130_fd_sc_hd__clkbuf_1 prog_clk_0_W_FTB01 ( .A ( prog_clk_0_S_in ) , - .X ( ctsbuf_net_3186 ) ) ; + .X ( ctsbuf_net_1185 ) ) ; +sky130_fd_sc_hd__buf_4 prog_clk_0_E_FTB01 ( .A ( prog_clk_0_S_in ) , + .X ( ctsbuf_net_2186 ) ) ; +sky130_fd_sc_hd__buf_4 prog_clk_0_W_FTB01 ( .A ( prog_clk_0_S_in ) , + .X ( ctsbuf_net_3187 ) ) ; sky130_fd_sc_hd__clkbuf_1 prog_clk_0_N_FTB01 ( .A ( prog_clk_0_S_in ) , - .X ( ctsbuf_net_4187 ) ) ; + .X ( ctsbuf_net_4188 ) ) ; sky130_fd_sc_hd__buf_1 clk_0_FTB00 ( .A ( clk_0_S_in ) , .X ( clk[0] ) ) ; sky130_fd_sc_hd__buf_6 FTB_65__64 ( .A ( aps_rename_522_ ) , .X ( top_width_0_height_0__pin_36_upper[0] ) ) ; @@ -46084,38 +46071,38 @@ sky130_fd_sc_hd__buf_6 FTB_80__79 ( .A ( aps_rename_537_ ) , .X ( right_width_0_height_0__pin_51_upper[0] ) ) ; sky130_fd_sc_hd__buf_6 FTB_81__80 ( .A ( aps_rename_538_ ) , .X ( SC_OUT_TOP ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_132 ( .A ( BUF_net_133 ) , +sky130_fd_sc_hd__inv_8 BINV_R_133 ( .A ( BUF_net_134 ) , .Y ( Test_en_W_out ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_133 ( .A ( aps_rename_539_ ) , - .Y ( BUF_net_133 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_134 ( .A ( BUF_net_135 ) , +sky130_fd_sc_hd__inv_1 BINV_R_134 ( .A ( aps_rename_539_ ) , + .Y ( BUF_net_134 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_135 ( .A ( BUF_net_136 ) , .Y ( Test_en_E_out ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_135 ( .A ( aps_rename_540_ ) , - .Y ( BUF_net_135 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_136 ( .A ( BUF_net_137 ) , .Y ( Reset_W_out ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_137 ( .A ( aps_rename_541_ ) , - .Y ( BUF_net_137 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_140 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_178 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_142 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , +sky130_fd_sc_hd__inv_1 BINV_R_136 ( .A ( aps_rename_540_ ) , + .Y ( BUF_net_136 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_137 ( .A ( BUF_net_138 ) , .Y ( Reset_W_out ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_138 ( .A ( aps_rename_541_ ) , + .Y ( BUF_net_138 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_141 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , .HI ( optlc_net_179 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_144 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , +sky130_fd_sc_hd__conb_1 optlc_143 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , .HI ( optlc_net_180 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_146 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , +sky130_fd_sc_hd__conb_1 optlc_145 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , .HI ( optlc_net_181 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_148 ( .LO ( SYNOPSYS_UNCONNECTED_6 ) , +sky130_fd_sc_hd__conb_1 optlc_147 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , .HI ( optlc_net_182 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_150 ( .LO ( SYNOPSYS_UNCONNECTED_7 ) , +sky130_fd_sc_hd__conb_1 optlc_149 ( .LO ( SYNOPSYS_UNCONNECTED_6 ) , .HI ( optlc_net_183 ) ) ; -sky130_fd_sc_hd__buf_6 ZBUF_6_f_inst_151 ( .A ( aps_rename_542_ ) , +sky130_fd_sc_hd__conb_1 optlc_151 ( .LO ( SYNOPSYS_UNCONNECTED_7 ) , + .HI ( optlc_net_184 ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_6_f_inst_152 ( .A ( aps_rename_542_ ) , .X ( Reset_E_out ) ) ; -sky130_fd_sc_hd__buf_6 cts_buf_3981324 ( .A ( ctsbuf_net_1184 ) , +sky130_fd_sc_hd__buf_6 cts_buf_3981325 ( .A ( ctsbuf_net_1185 ) , .X ( prog_clk_0_S_out ) ) ; -sky130_fd_sc_hd__clkbuf_8 cts_buf_4031329 ( .A ( ctsbuf_net_2185 ) , +sky130_fd_sc_hd__bufbuf_16 cts_buf_4031330 ( .A ( ctsbuf_net_2186 ) , .X ( prog_clk_0_E_out ) ) ; -sky130_fd_sc_hd__buf_6 cts_buf_4081334 ( .A ( ctsbuf_net_3186 ) , +sky130_fd_sc_hd__buf_6 cts_buf_4081335 ( .A ( ctsbuf_net_3187 ) , .X ( prog_clk_0_W_out ) ) ; -sky130_fd_sc_hd__buf_6 cts_buf_4131339 ( .A ( ctsbuf_net_4187 ) , +sky130_fd_sc_hd__buf_6 cts_buf_4131340 ( .A ( ctsbuf_net_4188 ) , .X ( prog_clk_0_N_out ) ) ; endmodule diff --git a/FPGA1212_QLSOFA_HD_PNR/fpga_top/fpga_top_icv_in_design.gds.gz b/FPGA1212_QLSOFA_HD_PNR/fpga_top/fpga_top_icv_in_design.gds.gz index 7923500..67ca78b 100644 Binary files a/FPGA1212_QLSOFA_HD_PNR/fpga_top/fpga_top_icv_in_design.gds.gz and b/FPGA1212_QLSOFA_HD_PNR/fpga_top/fpga_top_icv_in_design.gds.gz differ diff --git a/FPGA1212_QLSOFA_HD_PNR/fpga_top/fpga_top_icv_in_design.lvs.v b/FPGA1212_QLSOFA_HD_PNR/fpga_top/fpga_top_icv_in_design.lvs.v index 16d0f64..87c2891 100644 --- a/FPGA1212_QLSOFA_HD_PNR/fpga_top/fpga_top_icv_in_design.lvs.v +++ b/FPGA1212_QLSOFA_HD_PNR/fpga_top/fpga_top_icv_in_design.lvs.v @@ -14,23 +14,21 @@ output [0:0] mem_out ; input VDD ; input VSS ; -wire copt_net_103 ; +wire copt_net_102 ; supply1 VDD ; supply0 VSS ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( copt_net_103 ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( copt_net_102 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 FTB_18__17 ( .A ( mem_out[0] ) , .X ( ccff_tail[0] ) , +sky130_fd_sc_hd__buf_1 FTB_18__17 ( .A ( mem_out[0] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_1 ropt_h_inst_1347 ( .A ( ropt_net_114 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1338 ( .A ( copt_net_105 ) , .X ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1338 ( .A ( copt_net_106 ) , - .X ( copt_net_104 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1340 ( .A ( copt_net_103 ) , - .X ( copt_net_106 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1341 ( .A ( copt_net_104 ) , - .X ( ropt_net_114 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1339 ( .A ( copt_net_107 ) , + .X ( copt_net_105 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1341 ( .A ( copt_net_102 ) , + .X ( copt_net_107 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -396,6 +394,9 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -430,8 +431,6 @@ sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_89 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , - .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -1129,7 +1128,7 @@ input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_113 ) , +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_110 ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , @@ -1143,23 +1142,25 @@ sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1330 ( .A ( ccff_head[0] ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1329 ( .A ( ccff_head[0] ) , + .X ( copt_net_95 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1330 ( .A ( ropt_net_113 ) , .X ( copt_net_96 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1331 ( .A ( copt_net_96 ) , +sky130_fd_sc_hd__dlygate4sd2_1 copt_h_inst_1331 ( .A ( copt_net_99 ) , .X ( copt_net_97 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1332 ( .A ( copt_net_97 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1332 ( .A ( ropt_net_111 ) , .X ( copt_net_98 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1333 ( .A ( copt_net_98 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1333 ( .A ( copt_net_96 ) , .X ( copt_net_99 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1334 ( .A ( copt_net_99 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1334 ( .A ( copt_net_97 ) , .X ( copt_net_100 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 copt_h_inst_1335 ( .A ( copt_net_100 ) , - .X ( copt_net_101 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1344 ( .A ( copt_net_101 ) , +sky130_fd_sc_hd__buf_1 ropt_h_inst_1343 ( .A ( copt_net_98 ) , + .X ( ropt_net_110 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1344 ( .A ( ropt_net_112 ) , .X ( ropt_net_111 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 ropt_h_inst_1345 ( .A ( ropt_net_111 ) , +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1345 ( .A ( copt_net_100 ) , .X ( ropt_net_112 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1346 ( .A ( ropt_net_112 ) , +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1346 ( .A ( copt_net_95 ) , .X ( ropt_net_113 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -1913,7 +1914,7 @@ cby_2__1__mux_tree_tapbuf_size12_0 mux_left_ipin_0 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , .out ( right_grid_pin_0_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_91 ) ) ; + .p0 ( optlc_net_90 ) ) ; cby_2__1__mux_tree_tapbuf_size12_1 mux_right_ipin_0 ( .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[4] , chany_bottom_out[4] , chany_top_out[7] , chany_bottom_out[7] , @@ -1923,7 +1924,7 @@ cby_2__1__mux_tree_tapbuf_size12_1 mux_right_ipin_0 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) , .out ( left_grid_pin_16_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_92 ) ) ; + .p0 ( optlc_net_91 ) ) ; cby_2__1__mux_tree_tapbuf_size12_2 mux_right_ipin_2 ( .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[3] , chany_bottom_out[3] , chany_top_out[9] , chany_bottom_out[9] , @@ -1933,7 +1934,7 @@ cby_2__1__mux_tree_tapbuf_size12_2 mux_right_ipin_2 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , .out ( left_grid_pin_18_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_93 ) ) ; + .p0 ( optlc_net_92 ) ) ; cby_2__1__mux_tree_tapbuf_size12_3 mux_right_ipin_4 ( .in ( { chany_top_out[2] , chany_bottom_out[2] , chany_top_out[5] , chany_bottom_out[5] , chany_top_out[11] , chany_bottom_out[11] , @@ -1943,7 +1944,7 @@ cby_2__1__mux_tree_tapbuf_size12_3 mux_right_ipin_4 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) , .out ( left_grid_pin_20_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_90 ) ) ; + .p0 ( optlc_net_89 ) ) ; cby_2__1__mux_tree_tapbuf_size12_4 mux_right_ipin_6 ( .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[4] , chany_bottom_out[4] , chany_top_out[7] , chany_bottom_out[7] , @@ -1953,7 +1954,7 @@ cby_2__1__mux_tree_tapbuf_size12_4 mux_right_ipin_6 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 , SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) , .out ( left_grid_pin_22_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_92 ) ) ; + .p0 ( optlc_net_91 ) ) ; cby_2__1__mux_tree_tapbuf_size12_5 mux_right_ipin_8 ( .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[3] , chany_bottom_out[3] , chany_top_out[9] , chany_bottom_out[9] , @@ -1963,7 +1964,7 @@ cby_2__1__mux_tree_tapbuf_size12_5 mux_right_ipin_8 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 , SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) , .out ( left_grid_pin_24_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_93 ) ) ; + .p0 ( optlc_net_92 ) ) ; cby_2__1__mux_tree_tapbuf_size12_6 mux_right_ipin_10 ( .in ( { chany_top_out[2] , chany_bottom_out[2] , chany_top_out[5] , chany_bottom_out[5] , chany_top_out[11] , chany_bottom_out[11] , @@ -1973,7 +1974,7 @@ cby_2__1__mux_tree_tapbuf_size12_6 mux_right_ipin_10 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) , .out ( left_grid_pin_26_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_90 ) ) ; + .p0 ( optlc_net_89 ) ) ; cby_2__1__mux_tree_tapbuf_size12_7 mux_right_ipin_12 ( .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[4] , chany_bottom_out[4] , chany_top_out[7] , chany_bottom_out[7] , @@ -1983,7 +1984,7 @@ cby_2__1__mux_tree_tapbuf_size12_7 mux_right_ipin_12 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 , SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) , .out ( left_grid_pin_28_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_93 ) ) ; + .p0 ( optlc_net_92 ) ) ; cby_2__1__mux_tree_tapbuf_size12 mux_right_ipin_14 ( .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[3] , chany_bottom_out[3] , chany_top_out[9] , chany_bottom_out[9] , @@ -1993,7 +1994,7 @@ cby_2__1__mux_tree_tapbuf_size12 mux_right_ipin_14 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 , SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) , .out ( left_grid_pin_30_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_93 ) ) ; + .p0 ( optlc_net_92 ) ) ; cby_2__1__mux_tree_tapbuf_size12_mem_0 mem_left_ipin_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size12_mem_0_ccff_tail ) , @@ -2047,7 +2048,7 @@ cby_2__1__mux_tree_tapbuf_size10_0 mux_right_ipin_1 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 , SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) , .out ( left_grid_pin_17_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_91 ) ) ; + .p0 ( optlc_net_90 ) ) ; cby_2__1__mux_tree_tapbuf_size10_1 mux_right_ipin_3 ( .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[4] , chany_bottom_out[4] , chany_top_out[10] , chany_bottom_out[10] , @@ -2057,7 +2058,7 @@ cby_2__1__mux_tree_tapbuf_size10_1 mux_right_ipin_3 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 , SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) , .out ( left_grid_pin_19_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_91 ) ) ; + .p0 ( optlc_net_90 ) ) ; cby_2__1__mux_tree_tapbuf_size10_2 mux_right_ipin_5 ( .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[3] , chany_bottom_out[3] , chany_top_out[6] , chany_bottom_out[6] , @@ -2067,7 +2068,7 @@ cby_2__1__mux_tree_tapbuf_size10_2 mux_right_ipin_5 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 , SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) , .out ( left_grid_pin_21_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_92 ) ) ; + .p0 ( optlc_net_91 ) ) ; cby_2__1__mux_tree_tapbuf_size10_3 mux_right_ipin_7 ( .in ( { chany_top_out[2] , chany_bottom_out[2] , chany_top_out[5] , chany_bottom_out[5] , chany_top_out[8] , chany_bottom_out[8] , @@ -2077,7 +2078,7 @@ cby_2__1__mux_tree_tapbuf_size10_3 mux_right_ipin_7 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 , SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) , .out ( left_grid_pin_23_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_92 ) ) ; + .p0 ( optlc_net_91 ) ) ; cby_2__1__mux_tree_tapbuf_size10_4 mux_right_ipin_9 ( .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[4] , chany_bottom_out[4] , chany_top_out[10] , chany_bottom_out[10] , @@ -2087,7 +2088,7 @@ cby_2__1__mux_tree_tapbuf_size10_4 mux_right_ipin_9 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 , SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) , .out ( left_grid_pin_25_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_92 ) ) ; + .p0 ( optlc_net_91 ) ) ; cby_2__1__mux_tree_tapbuf_size10_5 mux_right_ipin_11 ( .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[3] , chany_bottom_out[3] , chany_top_out[12] , chany_bottom_out[12] , @@ -2097,7 +2098,7 @@ cby_2__1__mux_tree_tapbuf_size10_5 mux_right_ipin_11 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 , SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) , .out ( left_grid_pin_27_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_92 ) ) ; + .p0 ( optlc_net_91 ) ) ; cby_2__1__mux_tree_tapbuf_size10_6 mux_right_ipin_13 ( .in ( { chany_top_out[2] , chany_bottom_out[2] , chany_top_out[5] , chany_bottom_out[5] , chany_top_out[14] , chany_bottom_out[14] , @@ -2107,7 +2108,7 @@ cby_2__1__mux_tree_tapbuf_size10_6 mux_right_ipin_13 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 , SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) , .out ( left_grid_pin_29_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_91 ) ) ; + .p0 ( optlc_net_90 ) ) ; cby_2__1__mux_tree_tapbuf_size10 mux_right_ipin_15 ( .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[4] , chany_bottom_out[4] , chany_top_out[7] , chany_bottom_out[7] , @@ -2117,7 +2118,7 @@ cby_2__1__mux_tree_tapbuf_size10 mux_right_ipin_15 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 , SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 } ) , .out ( left_grid_pin_31_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_93 ) ) ; + .p0 ( optlc_net_92 ) ) ; cby_2__1__mux_tree_tapbuf_size10_mem_0 mem_right_ipin_1 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size12_mem_1_ccff_tail ) , @@ -2165,16 +2166,17 @@ cby_2__1__logical_tile_io_mode_io_ logical_tile_io_mode_io__0 ( .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) , .io_outpad ( left_width_0_height_0__pin_0_ ) , .ccff_head ( { ccff_tail_mid } ) , - .io_inpad ( left_width_0_height_0__pin_1_lower ) , - .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; + .io_inpad ( left_width_0_height_0__pin_1_lower ) , + .ccff_tail ( { ropt_net_108 } ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_S_in ) , .X ( pReset[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_W_in ) , .X ( prog_clk[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__clkbuf_1 prog_clk_0_S_FTB01 ( .A ( prog_clk_0_W_in ) , - .X ( ctsbuf_net_194 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .X ( ctsbuf_net_193 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__clkbuf_1 prog_clk_0_N_FTB01 ( .A ( prog_clk_0_W_in ) , - .X ( ctsbuf_net_295 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .X ( ctsbuf_net_294 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_19__18 ( .A ( chany_bottom_in[0] ) , .X ( chany_top_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_20__19 ( .A ( chany_bottom_in[1] ) , @@ -2299,17 +2301,19 @@ sky130_fd_sc_hd__buf_6 FTB_79__78 ( .A ( left_width_0_height_0__pin_1_lower[0] ) , .X ( left_width_0_height_0__pin_1_upper[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_92 ( .LO ( SYNOPSYS_UNCONNECTED_69 ) , +sky130_fd_sc_hd__conb_1 optlc_91 ( .LO ( SYNOPSYS_UNCONNECTED_69 ) , + .HI ( optlc_net_89 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_93 ( .LO ( SYNOPSYS_UNCONNECTED_70 ) , .HI ( optlc_net_90 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_94 ( .LO ( SYNOPSYS_UNCONNECTED_70 ) , +sky130_fd_sc_hd__conb_1 optlc_95 ( .LO ( SYNOPSYS_UNCONNECTED_71 ) , .HI ( optlc_net_91 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_96 ( .LO ( SYNOPSYS_UNCONNECTED_71 ) , +sky130_fd_sc_hd__conb_1 optlc_97 ( .LO ( SYNOPSYS_UNCONNECTED_72 ) , .HI ( optlc_net_92 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_98 ( .LO ( SYNOPSYS_UNCONNECTED_72 ) , - .HI ( optlc_net_93 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 cts_buf_3591232 ( .A ( ctsbuf_net_194 ) , +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1342 ( .A ( ropt_net_108 ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 cts_buf_3591231 ( .A ( ctsbuf_net_193 ) , .X ( prog_clk_0_S_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 cts_buf_3641237 ( .A ( ctsbuf_net_295 ) , +sky130_fd_sc_hd__clkbuf_8 cts_buf_3641236 ( .A ( ctsbuf_net_294 ) , .X ( prog_clk_0_N_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -2324,6 +2328,7 @@ output [0:3] mem_out ; input VDD ; input VSS ; +wire copt_net_115 ; supply1 VDD ; supply0 VSS ; @@ -2337,15 +2342,15 @@ sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( copt_net_115 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_6 FTB_16__15 ( .A ( copt_net_118 ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1352 ( .A ( mem_out[3] ) , - .X ( copt_net_115 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1352 ( .A ( copt_net_115 ) , + .X ( mem_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1355 ( .A ( copt_net_120 ) , .X ( copt_net_118 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1356 ( .A ( copt_net_115 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1356 ( .A ( mem_out[3] ) , .X ( copt_net_119 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1357 ( .A ( copt_net_119 ) , .X ( copt_net_120 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -3287,7 +3292,7 @@ input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_130 ) , +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_129 ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , @@ -3313,10 +3318,12 @@ sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1359 ( .A ( copt_net_117 ) , .X ( copt_net_122 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1360 ( .A ( copt_net_122 ) , .X ( copt_net_123 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1367 ( .A ( ropt_net_131 ) , +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1365 ( .A ( copt_net_123 ) , + .X ( ropt_net_128 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 ropt_h_inst_1366 ( .A ( ropt_net_130 ) , + .X ( ropt_net_129 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 ropt_h_inst_1367 ( .A ( ropt_net_128 ) , .X ( ropt_net_130 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 ropt_h_inst_1368 ( .A ( copt_net_123 ) , - .X ( ropt_net_131 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -4303,7 +4310,7 @@ sky130_fd_sc_hd__buf_8 FTB_19__18 ( .A ( chany_bottom_in[2] ) , .X ( chany_top_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_20__19 ( .A ( chany_bottom_in[3] ) , .X ( chany_top_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_12 FTB_21__20 ( .A ( chany_bottom_in[4] ) , +sky130_fd_sc_hd__buf_8 FTB_21__20 ( .A ( chany_bottom_in[4] ) , .X ( chany_top_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_22__21 ( .A ( chany_bottom_in[5] ) , .X ( chany_top_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -4470,27 +4477,27 @@ output [0:0] mem_out ; input VDD ; input VSS ; -wire copt_net_78 ; +wire copt_net_74 ; supply1 VDD ; supply0 VSS ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( copt_net_78 ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( copt_net_74 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_6 FTB_2__1 ( .A ( mem_out[0] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1217 ( .A ( copt_net_78 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1217 ( .A ( copt_net_75 ) , .X ( copt_net_73 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1218 ( .A ( copt_net_73 ) , - .X ( copt_net_74 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1218 ( .A ( copt_net_78 ) , + .X ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1219 ( .A ( copt_net_74 ) , .X ( copt_net_75 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1220 ( .A ( copt_net_75 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1220 ( .A ( copt_net_73 ) , .X ( copt_net_76 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1221 ( .A ( copt_net_76 ) , .X ( copt_net_77 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1222 ( .A ( copt_net_77 ) , - .X ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .X ( copt_net_78 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -4606,7 +4613,7 @@ input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( copt_net_72 ) , +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( copt_net_71 ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , @@ -4628,9 +4635,9 @@ sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1213 ( .A ( copt_net_68 ) , .X ( copt_net_69 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1214 ( .A ( copt_net_69 ) , .X ( copt_net_70 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1215 ( .A ( copt_net_70 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1215 ( .A ( copt_net_72 ) , .X ( copt_net_71 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1216 ( .A ( copt_net_71 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1216 ( .A ( copt_net_70 ) , .X ( copt_net_72 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -4734,20 +4741,20 @@ input prog_clk_0_E_in ; input VDD ; input VSS ; -wire ropt_net_134 ; -wire ropt_net_128 ; -wire ropt_net_129 ; -wire ropt_net_133 ; -wire ropt_net_127 ; -wire ropt_net_122 ; -wire ropt_net_124 ; -wire ropt_net_132 ; -wire ropt_net_123 ; wire ropt_net_120 ; -wire ropt_net_138 ; -wire ropt_net_125 ; -wire ropt_net_137 ; +wire ropt_net_118 ; +wire ropt_net_136 ; +wire ropt_net_117 ; wire ropt_net_121 ; +wire ropt_net_125 ; +wire ropt_net_124 ; +wire ropt_net_122 ; +wire ropt_net_115 ; +wire ropt_net_116 ; +wire ropt_net_126 ; +wire ropt_net_119 ; +wire ropt_net_123 ; +wire ropt_net_114 ; wire [0:0] prog_clk ; wire prog_clk_0 ; wire [0:3] mux_tree_tapbuf_size12_0_sram ; @@ -4786,21 +4793,21 @@ sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_E_in ) , sky130_fd_sc_hd__buf_8 FTB_3__2 ( .A ( chany_bottom_in[0] ) , .X ( chany_top_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_6 FTB_4__3 ( .A ( chany_bottom_in[1] ) , - .X ( ropt_net_134 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 FTB_5__4 ( .A ( chany_bottom_in[2] ) , - .X ( chany_top_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .X ( chany_top_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_5__4 ( .A ( chany_bottom_in[2] ) , + .X ( ropt_net_120 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_6__5 ( .A ( chany_bottom_in[3] ) , .X ( chany_top_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 FTB_7__6 ( .A ( chany_bottom_in[4] ) , +sky130_fd_sc_hd__buf_6 FTB_7__6 ( .A ( chany_bottom_in[4] ) , .X ( chany_top_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 FTB_8__7 ( .A ( chany_bottom_in[5] ) , - .X ( chany_top_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_8__7 ( .A ( chany_bottom_in[5] ) , + .X ( ropt_net_118 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_9__8 ( .A ( chany_bottom_in[6] ) , .X ( chany_top_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_10__9 ( .A ( chany_bottom_in[7] ) , .X ( chany_top_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_6 FTB_11__10 ( .A ( chany_bottom_in[8] ) , - .X ( ropt_net_128 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .X ( ropt_net_136 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_12__11 ( .A ( chany_bottom_in[9] ) , .X ( chany_top_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_13__12 ( .A ( chany_bottom_in[10] ) , @@ -4809,50 +4816,50 @@ sky130_fd_sc_hd__buf_6 FTB_14__13 ( .A ( chany_bottom_in[11] ) , .X ( chany_top_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_15__14 ( .A ( chany_bottom_in[12] ) , .X ( chany_top_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 FTB_16__15 ( .A ( chany_bottom_in[13] ) , - .X ( chany_top_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 FTB_17__16 ( .A ( chany_bottom_in[14] ) , - .X ( ropt_net_129 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_16__15 ( .A ( chany_bottom_in[13] ) , + .X ( ropt_net_117 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_17__16 ( .A ( chany_bottom_in[14] ) , + .X ( chany_top_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_6 FTB_18__17 ( .A ( chany_bottom_in[15] ) , - .X ( ropt_net_133 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 FTB_19__18 ( .A ( chany_bottom_in[16] ) , - .X ( chany_top_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .X ( ropt_net_121 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_19__18 ( .A ( chany_bottom_in[16] ) , + .X ( ropt_net_125 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_6 FTB_20__19 ( .A ( chany_bottom_in[17] ) , .X ( chany_top_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_21__20 ( .A ( chany_bottom_in[18] ) , .X ( chany_top_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_6 FTB_22__21 ( .A ( chany_bottom_in[19] ) , - .X ( ropt_net_127 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .X ( chany_top_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_6 FTB_23__22 ( .A ( chany_bottom_in[20] ) , - .X ( chany_top_out[20] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .X ( ropt_net_124 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_24__23 ( .A ( chany_bottom_in[21] ) , .X ( chany_top_out[21] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 FTB_25__24 ( .A ( chany_bottom_in[22] ) , - .X ( ropt_net_122 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_25__24 ( .A ( chany_bottom_in[22] ) , + .X ( chany_top_out[22] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_6 FTB_26__25 ( .A ( chany_bottom_in[23] ) , - .X ( ropt_net_124 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .X ( ropt_net_122 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_27__26 ( .A ( chany_bottom_in[24] ) , .X ( chany_top_out[24] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_28__27 ( .A ( chany_bottom_in[25] ) , .X ( chany_top_out[25] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 FTB_29__28 ( .A ( chany_bottom_in[26] ) , +sky130_fd_sc_hd__buf_6 FTB_29__28 ( .A ( chany_bottom_in[26] ) , .X ( chany_top_out[26] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 FTB_30__29 ( .A ( chany_bottom_in[27] ) , - .X ( chany_top_out[27] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_30__29 ( .A ( chany_bottom_in[27] ) , + .X ( ropt_net_115 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_31__30 ( .A ( chany_bottom_in[28] ) , .X ( chany_top_out[28] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 FTB_32__31 ( .A ( chany_bottom_in[29] ) , +sky130_fd_sc_hd__buf_6 FTB_32__31 ( .A ( chany_bottom_in[29] ) , .X ( chany_top_out[29] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_33__32 ( .A ( chany_top_in[0] ) , .X ( chany_bottom_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_6 FTB_34__33 ( .A ( chany_top_in[1] ) , .X ( chany_bottom_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 FTB_35__34 ( .A ( chany_top_in[2] ) , - .X ( ropt_net_132 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_35__34 ( .A ( chany_top_in[2] ) , + .X ( chany_bottom_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_36__35 ( .A ( chany_top_in[3] ) , .X ( chany_bottom_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 FTB_37__36 ( .A ( chany_top_in[4] ) , - .X ( ropt_net_123 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_37__36 ( .A ( chany_top_in[4] ) , + .X ( chany_bottom_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_38__37 ( .A ( chany_top_in[5] ) , .X ( chany_bottom_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chany_top_in[6] ) , @@ -4870,37 +4877,37 @@ sky130_fd_sc_hd__buf_6 FTB_44__43 ( .A ( chany_top_in[11] ) , sky130_fd_sc_hd__buf_8 FTB_45__44 ( .A ( chany_top_in[12] ) , .X ( chany_bottom_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_6 FTB_46__45 ( .A ( chany_top_in[13] ) , - .X ( ropt_net_120 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .X ( ropt_net_116 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_6 FTB_47__46 ( .A ( chany_top_in[14] ) , - .X ( ropt_net_138 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .X ( ropt_net_126 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_48__47 ( .A ( chany_top_in[15] ) , .X ( chany_bottom_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_49__48 ( .A ( chany_top_in[16] ) , .X ( chany_bottom_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_6 FTB_50__49 ( .A ( chany_top_in[17] ) , - .X ( ropt_net_125 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .X ( ropt_net_119 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_51__50 ( .A ( chany_top_in[18] ) , .X ( chany_bottom_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 FTB_52__51 ( .A ( chany_top_in[19] ) , +sky130_fd_sc_hd__buf_6 FTB_52__51 ( .A ( chany_top_in[19] ) , .X ( chany_bottom_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 FTB_53__52 ( .A ( chany_top_in[20] ) , - .X ( chany_bottom_out[20] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_53__52 ( .A ( chany_top_in[20] ) , + .X ( ropt_net_123 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chany_top_in[21] ) , .X ( chany_bottom_out[21] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_6 FTB_55__54 ( .A ( chany_top_in[22] ) , - .X ( ropt_net_137 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .X ( chany_bottom_out[22] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chany_top_in[23] ) , .X ( chany_bottom_out[23] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chany_top_in[24] ) , .X ( chany_bottom_out[24] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 FTB_58__57 ( .A ( chany_top_in[25] ) , +sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chany_top_in[25] ) , .X ( chany_bottom_out[25] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_6 FTB_59__58 ( .A ( chany_top_in[26] ) , .X ( chany_bottom_out[26] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( chany_top_in[27] ) , .X ( chany_bottom_out[27] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_6 FTB_61__60 ( .A ( chany_top_in[28] ) , - .X ( ropt_net_121 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .X ( ropt_net_114 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_62__61 ( .A ( chany_top_in[29] ) , .X ( chany_bottom_out[29] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_6 FTB_63__62 ( @@ -4909,34 +4916,34 @@ sky130_fd_sc_hd__buf_6 FTB_63__62 ( .VGND ( VSS ) ) ; sky130_fd_sc_hd__conb_1 optlc_67 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , .HI ( optlc_net_66 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1263 ( .A ( ropt_net_120 ) , - .X ( chany_bottom_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1264 ( .A ( ropt_net_121 ) , +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1258 ( .A ( ropt_net_114 ) , .X ( chany_bottom_out[28] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1265 ( .A ( ropt_net_122 ) , - .X ( chany_top_out[22] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1266 ( .A ( ropt_net_123 ) , - .X ( chany_bottom_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1267 ( .A ( ropt_net_124 ) , - .X ( chany_top_out[23] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1268 ( .A ( ropt_net_125 ) , +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1259 ( .A ( ropt_net_115 ) , + .X ( chany_top_out[27] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1260 ( .A ( ropt_net_116 ) , + .X ( chany_bottom_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1261 ( .A ( ropt_net_117 ) , + .X ( chany_top_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1262 ( .A ( ropt_net_118 ) , + .X ( chany_top_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1263 ( .A ( ropt_net_119 ) , .X ( chany_bottom_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1270 ( .A ( ropt_net_127 ) , - .X ( chany_top_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1271 ( .A ( ropt_net_128 ) , - .X ( chany_top_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1272 ( .A ( ropt_net_129 ) , - .X ( chany_top_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1275 ( .A ( ropt_net_132 ) , - .X ( chany_bottom_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1276 ( .A ( ropt_net_133 ) , +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1264 ( .A ( ropt_net_120 ) , + .X ( chany_top_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1265 ( .A ( ropt_net_121 ) , .X ( chany_top_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1277 ( .A ( ropt_net_134 ) , - .X ( chany_top_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1280 ( .A ( ropt_net_137 ) , - .X ( chany_bottom_out[22] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1281 ( .A ( ropt_net_138 ) , +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1266 ( .A ( ropt_net_122 ) , + .X ( chany_top_out[23] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1267 ( .A ( ropt_net_123 ) , + .X ( chany_bottom_out[20] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1268 ( .A ( ropt_net_124 ) , + .X ( chany_top_out[20] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1269 ( .A ( ropt_net_125 ) , + .X ( chany_top_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1270 ( .A ( ropt_net_126 ) , .X ( chany_bottom_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1280 ( .A ( ropt_net_136 ) , + .X ( chany_top_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -7605,7 +7612,7 @@ sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_87 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_88 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -7633,7 +7640,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , @@ -7696,9 +7703,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -7733,6 +7737,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_87 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -7759,7 +7765,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , @@ -7822,6 +7828,70 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_85 ( .A ( BUF_net_86 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_86 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .Y ( BUF_net_86 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size10_1 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -7862,68 +7932,6 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module cbx_1__1__mux_tree_tapbuf_size10_1 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_86 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , - .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - module cbx_1__1__mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; input [0:9] in ; @@ -8210,7 +8218,7 @@ input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( copt_net_107 ) , +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( copt_net_101 ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , @@ -8224,22 +8232,16 @@ sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1326 ( .A ( copt_net_101 ) , - .X ( copt_net_100 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_2 copt_h_inst_1327 ( .A ( ccff_head[0] ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1323 ( .A ( ccff_head[0] ) , + .X ( copt_net_95 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1324 ( .A ( copt_net_95 ) , + .X ( copt_net_96 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1325 ( .A ( copt_net_96 ) , + .X ( copt_net_97 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1326 ( .A ( copt_net_97 ) , + .X ( copt_net_98 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1329 ( .A ( copt_net_98 ) , .X ( copt_net_101 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1328 ( .A ( copt_net_100 ) , - .X ( copt_net_102 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 copt_h_inst_1329 ( .A ( copt_net_102 ) , - .X ( copt_net_103 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_1 copt_h_inst_1333 ( .A ( copt_net_103 ) , - .X ( copt_net_104 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1334 ( .A ( copt_net_106 ) , - .X ( copt_net_105 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 copt_h_inst_1335 ( .A ( copt_net_104 ) , - .X ( copt_net_106 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1346 ( .A ( copt_net_105 ) , - .X ( copt_net_107 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -8309,10 +8311,10 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_84 ( .A ( BUF_net_85 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_83 ( .A ( BUF_net_84 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_85 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , - .Y ( BUF_net_85 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_84 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , + .Y ( BUF_net_84 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -8382,7 +8384,7 @@ sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_83 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_82 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -8412,7 +8414,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , @@ -8525,7 +8527,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_82 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_81 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -8740,10 +8742,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_91 ( .A ( BUF_net_92 ) , .Y ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_4 BINV_R_92 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , - .Y ( BUF_net_92 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_80 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -8772,7 +8772,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , @@ -8901,11 +8901,6 @@ output clk_3_W_out ; input VDD ; input VSS ; -wire ropt_net_130 ; -wire ropt_net_121 ; -wire ropt_net_132 ; -wire ropt_net_124 ; -wire ropt_net_125 ; wire [0:0] prog_clk ; wire prog_clk_0 ; wire [0:3] mux_tree_tapbuf_size10_0_sram ; @@ -8960,7 +8955,7 @@ cbx_1__1__mux_tree_tapbuf_size12_0 mux_top_ipin_0 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , .out ( bottom_grid_pin_0_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_96 ) ) ; + .p0 ( optlc_net_92 ) ) ; cbx_1__1__mux_tree_tapbuf_size12_1 mux_top_ipin_2 ( .in ( { chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[5] , chanx_left_out[5] , chanx_right_out[8] , chanx_left_out[8] , @@ -8970,7 +8965,7 @@ cbx_1__1__mux_tree_tapbuf_size12_1 mux_top_ipin_2 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) , .out ( bottom_grid_pin_2_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_95 ) ) ; + .p0 ( optlc_net_91 ) ) ; cbx_1__1__mux_tree_tapbuf_size12_2 mux_top_ipin_4 ( .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[4] , chanx_left_out[4] , chanx_right_out[10] , chanx_left_out[10] , @@ -8980,7 +8975,7 @@ cbx_1__1__mux_tree_tapbuf_size12_2 mux_top_ipin_4 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , .out ( bottom_grid_pin_4_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_93 ) ) ; + .p0 ( optlc_net_89 ) ) ; cbx_1__1__mux_tree_tapbuf_size12_3 mux_top_ipin_6 ( .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] , chanx_left_out[3] , chanx_right_out[6] , chanx_left_out[6] , @@ -8990,7 +8985,7 @@ cbx_1__1__mux_tree_tapbuf_size12_3 mux_top_ipin_6 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) , .out ( bottom_grid_pin_6_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_97 ) ) ; + .p0 ( optlc_net_92 ) ) ; cbx_1__1__mux_tree_tapbuf_size12_4 mux_top_ipin_8 ( .in ( { chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[5] , chanx_left_out[5] , chanx_right_out[8] , chanx_left_out[8] , @@ -9000,7 +8995,7 @@ cbx_1__1__mux_tree_tapbuf_size12_4 mux_top_ipin_8 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 , SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) , .out ( bottom_grid_pin_8_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_95 ) ) ; + .p0 ( optlc_net_89 ) ) ; cbx_1__1__mux_tree_tapbuf_size12_5 mux_top_ipin_10 ( .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[4] , chanx_left_out[4] , chanx_right_out[10] , chanx_left_out[10] , @@ -9010,7 +9005,7 @@ cbx_1__1__mux_tree_tapbuf_size12_5 mux_top_ipin_10 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 , SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) , .out ( bottom_grid_pin_10_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_93 ) ) ; + .p0 ( optlc_net_89 ) ) ; cbx_1__1__mux_tree_tapbuf_size12_6 mux_top_ipin_12 ( .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] , chanx_left_out[3] , chanx_right_out[6] , chanx_left_out[6] , @@ -9020,7 +9015,7 @@ cbx_1__1__mux_tree_tapbuf_size12_6 mux_top_ipin_12 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) , .out ( bottom_grid_pin_12_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_97 ) ) ; + .p0 ( optlc_net_92 ) ) ; cbx_1__1__mux_tree_tapbuf_size12 mux_top_ipin_14 ( .in ( { chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[5] , chanx_left_out[5] , chanx_right_out[8] , chanx_left_out[8] , @@ -9030,7 +9025,7 @@ cbx_1__1__mux_tree_tapbuf_size12 mux_top_ipin_14 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 , SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) , .out ( bottom_grid_pin_14_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_93 ) ) ; + .p0 ( optlc_net_91 ) ) ; cbx_1__1__mux_tree_tapbuf_size12_mem_0 mem_top_ipin_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size12_mem_0_ccff_tail ) , @@ -9079,7 +9074,7 @@ cbx_1__1__mux_tree_tapbuf_size10_0 mux_top_ipin_1 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 , SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) , .out ( bottom_grid_pin_1_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_93 ) ) ; + .p0 ( optlc_net_89 ) ) ; cbx_1__1__mux_tree_tapbuf_size10_1 mux_top_ipin_3 ( .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] , chanx_left_out[3] , chanx_right_out[9] , chanx_left_out[9] , @@ -9089,7 +9084,7 @@ cbx_1__1__mux_tree_tapbuf_size10_1 mux_top_ipin_3 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 , SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) , .out ( bottom_grid_pin_3_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_93 ) ) ; + .p0 ( optlc_net_92 ) ) ; cbx_1__1__mux_tree_tapbuf_size10_2 mux_top_ipin_5 ( .in ( { chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[5] , chanx_left_out[5] , chanx_right_out[11] , chanx_left_out[11] , @@ -9099,7 +9094,7 @@ cbx_1__1__mux_tree_tapbuf_size10_2 mux_top_ipin_5 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 , SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) , .out ( bottom_grid_pin_5_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_95 ) ) ; + .p0 ( optlc_net_91 ) ) ; cbx_1__1__mux_tree_tapbuf_size10_3 mux_top_ipin_7 ( .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[4] , chanx_left_out[4] , chanx_right_out[7] , chanx_left_out[7] , @@ -9109,7 +9104,7 @@ cbx_1__1__mux_tree_tapbuf_size10_3 mux_top_ipin_7 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 , SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) , .out ( bottom_grid_pin_7_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_93 ) ) ; + .p0 ( optlc_net_91 ) ) ; cbx_1__1__mux_tree_tapbuf_size10_4 mux_top_ipin_9 ( .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] , chanx_left_out[3] , chanx_right_out[9] , chanx_left_out[9] , @@ -9119,7 +9114,7 @@ cbx_1__1__mux_tree_tapbuf_size10_4 mux_top_ipin_9 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 , SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) , .out ( bottom_grid_pin_9_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_96 ) ) ; + .p0 ( optlc_net_92 ) ) ; cbx_1__1__mux_tree_tapbuf_size10_5 mux_top_ipin_11 ( .in ( { chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[5] , chanx_left_out[5] , chanx_right_out[11] , chanx_left_out[11] , @@ -9129,7 +9124,7 @@ cbx_1__1__mux_tree_tapbuf_size10_5 mux_top_ipin_11 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 , SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) , .out ( bottom_grid_pin_11_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_94 ) ) ; + .p0 ( optlc_net_90 ) ) ; cbx_1__1__mux_tree_tapbuf_size10_6 mux_top_ipin_13 ( .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[4] , chanx_left_out[4] , chanx_right_out[13] , chanx_left_out[13] , @@ -9139,7 +9134,7 @@ cbx_1__1__mux_tree_tapbuf_size10_6 mux_top_ipin_13 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 , SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) , .out ( bottom_grid_pin_13_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_94 ) ) ; + .p0 ( optlc_net_90 ) ) ; cbx_1__1__mux_tree_tapbuf_size10 mux_top_ipin_15 ( .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] , chanx_left_out[3] , chanx_right_out[6] , chanx_left_out[6] , @@ -9149,7 +9144,7 @@ cbx_1__1__mux_tree_tapbuf_size10 mux_top_ipin_15 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 , SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) , .out ( bottom_grid_pin_15_ ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_97 ) ) ; + .p0 ( optlc_net_92 ) ) ; cbx_1__1__mux_tree_tapbuf_size10_mem_0 mem_top_ipin_1 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size12_mem_0_ccff_tail ) , @@ -9188,20 +9183,20 @@ cbx_1__1__mux_tree_tapbuf_size10_mem_6 mem_top_ipin_13 ( .pReset ( pReset ) , cbx_1__1__mux_tree_tapbuf_size10_mem mem_top_ipin_15 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size12_mem_7_ccff_tail ) , - .ccff_tail ( { copt_net_108 } ) , + .ccff_tail ( { copt_net_100 } ) , .mem_out ( mux_tree_tapbuf_size10_7_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_W_in ) , .X ( pReset[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_4 pReset_W_FTB01 ( .A ( pReset_W_in ) , .X ( pReset_W_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__bufbuf_16 pReset_S_FTB01 ( .A ( pReset_W_in ) , +sky130_fd_sc_hd__buf_4 pReset_S_FTB01 ( .A ( pReset_W_in ) , .X ( pReset_S_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_4 pReset_E_FTB01 ( .A ( pReset_W_in ) , .X ( pReset_E_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_2 prog_clk_0_FTB00 ( .A ( prog_clk_0_N_in ) , .X ( prog_clk[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__clkbuf_1 prog_clk_0_W_FTB01 ( .A ( prog_clk_0_N_in ) , - .X ( ctsbuf_net_198 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .X ( ctsbuf_net_193 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__bufbuf_16 prog_clk_1_N_FTB01 ( .A ( prog_clk_1_E_in ) , .X ( prog_clk_1_N_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_4 prog_clk_1_S_FTB01 ( .A ( prog_clk_1_E_in ) , @@ -9209,23 +9204,23 @@ sky130_fd_sc_hd__buf_4 prog_clk_1_S_FTB01 ( .A ( prog_clk_1_E_in ) , sky130_fd_sc_hd__buf_4 prog_clk_2_W_FTB01 ( .A ( prog_clk_2_W_in ) , .X ( prog_clk_2_W_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_4 prog_clk_2_E_FTB01 ( .A ( prog_clk_2_W_in ) , - .X ( prog_clk_2_E_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .X ( aps_rename_505_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_4 prog_clk_3_E_FTB01 ( .A ( prog_clk_3_E_in ) , - .X ( prog_clk_3_E_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .X ( aps_rename_506_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_4 prog_clk_3_W_FTB01 ( .A ( prog_clk_3_E_in ) , .X ( prog_clk_3_W_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__bufbuf_16 clk_1_N_FTB01 ( .A ( clk_1_E_in ) , .X ( clk_1_N_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_1 clk_1_S_FTB01 ( .A ( clk_1_E_in ) , .X ( net_net_88 ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_4 clk_1_S_FTB01 ( .A ( clk_1_E_in ) , + .X ( clk_1_S_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_4 clk_2_W_FTB01 ( .A ( clk_2_W_in ) , .X ( clk_2_W_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_4 clk_2_E_FTB01 ( .A ( clk_2_W_in ) , - .X ( clk_2_E_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .X ( aps_rename_507_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_4 clk_3_E_FTB01 ( .A ( clk_3_E_in ) , - .X ( clk_3_E_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_4 clk_3_W_FTB01 ( .A ( clk_3_E_in ) , .X ( ZBUF_39_0 ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .X ( aps_rename_508_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_4 clk_3_W_FTB01 ( .A ( clk_3_E_in ) , + .X ( clk_3_W_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_17__16 ( .A ( chanx_left_in[0] ) , .X ( chanx_right_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_18__17 ( .A ( chanx_left_in[1] ) , @@ -9244,8 +9239,8 @@ sky130_fd_sc_hd__buf_8 FTB_24__23 ( .A ( chanx_left_in[7] ) , .X ( chanx_right_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_25__24 ( .A ( chanx_left_in[8] ) , .X ( chanx_right_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 FTB_26__25 ( .A ( chanx_left_in[9] ) , - .X ( ropt_net_130 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_26__25 ( .A ( chanx_left_in[9] ) , + .X ( chanx_right_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_27__26 ( .A ( chanx_left_in[10] ) , .X ( chanx_right_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_28__27 ( .A ( chanx_left_in[11] ) , @@ -9272,8 +9267,8 @@ sky130_fd_sc_hd__buf_8 FTB_38__37 ( .A ( chanx_left_in[21] ) , .X ( chanx_right_out[21] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chanx_left_in[22] ) , .X ( chanx_right_out[22] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_1 FTB_40__39 ( .A ( chanx_left_in[23] ) , - .X ( ropt_net_121 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_40__39 ( .A ( chanx_left_in[23] ) , + .X ( chanx_right_out[23] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_41__40 ( .A ( chanx_left_in[24] ) , .X ( chanx_right_out[24] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_42__41 ( .A ( chanx_left_in[25] ) , @@ -9332,8 +9327,8 @@ sky130_fd_sc_hd__buf_8 FTB_68__67 ( .A ( chanx_right_in[21] ) , .X ( chanx_left_out[21] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_69__68 ( .A ( chanx_right_in[22] ) , .X ( chanx_left_out[22] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_1 FTB_70__69 ( .A ( chanx_right_in[23] ) , - .X ( ropt_net_132 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_70__69 ( .A ( chanx_right_in[23] ) , + .X ( chanx_left_out[23] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_71__70 ( .A ( chanx_right_in[24] ) , .X ( chanx_left_out[24] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_72__71 ( .A ( chanx_right_in[25] ) , @@ -9346,58 +9341,36 @@ sky130_fd_sc_hd__buf_8 FTB_75__74 ( .A ( chanx_right_in[28] ) , .X ( chanx_left_out[28] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_76__75 ( .A ( chanx_right_in[29] ) , .X ( chanx_left_out[29] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_1 FTB_77__76 ( .A ( SC_IN_TOP ) , .X ( ropt_net_124 ) , +sky130_fd_sc_hd__buf_8 FTB_77__76 ( .A ( SC_IN_TOP ) , .X ( SC_OUT_BOT ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_6 FTB_78__77 ( .A ( SC_IN_BOT ) , .X ( SC_OUT_TOP ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_6 FTB_79__78 ( .A ( REGIN_FEEDTHROUGH ) , .X ( REGOUT_FEEDTHROUGH ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_1 FTB_80__79 ( .A ( CIN_FEEDTHROUGH ) , - .X ( ropt_net_125 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_88 ( .A ( net_net_88 ) , .X ( clk_1_S_out ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_95 ( .LO ( SYNOPSYS_UNCONNECTED_65 ) , - .HI ( optlc_net_93 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_97 ( .LO ( SYNOPSYS_UNCONNECTED_66 ) , - .HI ( optlc_net_94 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_100 ( .LO ( SYNOPSYS_UNCONNECTED_67 ) , - .HI ( optlc_net_95 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_102 ( .LO ( SYNOPSYS_UNCONNECTED_68 ) , - .HI ( optlc_net_96 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_104 ( .LO ( SYNOPSYS_UNCONNECTED_69 ) , - .HI ( optlc_net_97 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 ZBUF_39_inst_1345 ( .A ( ZBUF_39_0 ) , - .X ( clk_3_W_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 cts_buf_3531232 ( .A ( ctsbuf_net_198 ) , - .X ( prog_clk_0_W_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__bufbuf_8 copt_h_inst_1353 ( .A ( copt_net_109 ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1354 ( .A ( ropt_net_133 ) , - .X ( copt_net_109 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1355 ( .A ( copt_net_111 ) , - .X ( copt_net_110 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_2 copt_h_inst_1356 ( .A ( copt_net_108 ) , - .X ( copt_net_111 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1357 ( .A ( copt_net_110 ) , - .X ( copt_net_112 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1358 ( .A ( ropt_net_135 ) , - .X ( copt_net_113 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 ropt_mt_inst_1371 ( .A ( ropt_net_124 ) , - .X ( SC_OUT_BOT ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 ropt_mt_inst_1372 ( .A ( ropt_net_125 ) , +sky130_fd_sc_hd__buf_6 FTB_80__79 ( .A ( CIN_FEEDTHROUGH ) , .X ( COUT_FEEDTHROUGH ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1377 ( .A ( ropt_net_130 ) , - .X ( chanx_right_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 ropt_mt_inst_1379 ( .A ( ropt_net_132 ) , - .X ( chanx_left_out[23] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_1 ropt_h_inst_1380 ( .A ( copt_net_113 ) , - .X ( ropt_net_133 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_1 ropt_h_inst_1381 ( .A ( copt_net_112 ) , - .X ( ropt_net_134 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 ropt_mt_inst_1367 ( .A ( ropt_net_121 ) , - .X ( chanx_right_out[23] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_1 ropt_h_inst_1382 ( .A ( ropt_net_134 ) , - .X ( ropt_net_135 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_91 ( .LO ( SYNOPSYS_UNCONNECTED_65 ) , + .HI ( optlc_net_89 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_93 ( .LO ( SYNOPSYS_UNCONNECTED_66 ) , + .HI ( optlc_net_90 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_95 ( .LO ( SYNOPSYS_UNCONNECTED_67 ) , + .HI ( optlc_net_91 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_97 ( .LO ( SYNOPSYS_UNCONNECTED_68 ) , + .HI ( optlc_net_92 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_6_f_inst_602 ( .A ( aps_rename_507_ ) , + .X ( clk_2_E_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_6_f_inst_603 ( .A ( aps_rename_505_ ) , + .X ( prog_clk_2_E_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_240_f_inst_604 ( .A ( aps_rename_508_ ) , + .X ( clk_3_E_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_39_inst_605 ( .A ( aps_rename_506_ ) , + .X ( prog_clk_3_E_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 copt_h_inst_1328 ( .A ( copt_net_102 ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 cts_buf_3531229 ( .A ( ctsbuf_net_193 ) , + .X ( prog_clk_0_W_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1330 ( .A ( copt_net_100 ) , + .X ( copt_net_102 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -10385,7 +10358,7 @@ sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , .TE_B ( SOC_DIR ) , .Z ( SOC_OUT ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_89 ( .A ( net_net_89 ) , .X ( SOC_DIR ) , +sky130_fd_sc_hd__buf_8 BUFT_RR_89 ( .A ( net_net_89 ) , .X ( SOC_DIR ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -11777,7 +11750,7 @@ sky130_fd_sc_hd__buf_8 FTB_37__36 ( .A ( chanx_left_in[18] ) , .X ( chanx_right_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_38__37 ( .A ( chanx_left_in[19] ) , .X ( chanx_right_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_12 FTB_39__38 ( .A ( chanx_left_in[20] ) , +sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chanx_left_in[20] ) , .X ( chanx_right_out[20] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_40__39 ( .A ( chanx_left_in[21] ) , .X ( chanx_right_out[21] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -12041,10 +12014,10 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_131 ( .A ( BUF_net_132 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_139 ( .A ( BUF_net_140 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_132 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .Y ( BUF_net_132 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_140 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .Y ( BUF_net_140 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -12096,9 +12069,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -12109,6 +12079,10 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_137 ( .A ( BUF_net_138 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_138 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .Y ( BUF_net_138 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -12138,10 +12112,10 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_129 ( .A ( BUF_net_130 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_135 ( .A ( BUF_net_136 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_130 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .Y ( BUF_net_130 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_136 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .Y ( BUF_net_136 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -12155,7 +12129,6 @@ output [0:1] mem_out ; input VDD ; input VSS ; -wire copt_net_172 ; supply1 VDD ; supply0 VSS ; @@ -12163,12 +12136,12 @@ sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( copt_net_172 ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 FTB_49__48 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1348 ( .A ( copt_net_172 ) , - .X ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_49__48 ( .A ( copt_net_165 ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1335 ( .A ( mem_out[1] ) , + .X ( copt_net_165 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -13051,15 +13024,16 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_134 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_134 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_149 ( .A ( BUF_net_134 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -13111,10 +13085,10 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_128 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_128 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_151 ( .A ( BUF_net_128 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_131 ( .A ( BUF_net_132 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_132 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_132 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -13139,10 +13113,10 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_149 ( .A ( BUF_net_150 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_129 ( .A ( BUF_net_130 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_150 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_150 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_130 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_130 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -13167,10 +13141,10 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_147 ( .A ( BUF_net_148 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_127 ( .A ( BUF_net_128 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_148 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_148 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_128 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_128 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -13189,6 +13163,62 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_125 ( .A ( BUF_net_126 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_126 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_126 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_30 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_123 ( .A ( BUF_net_124 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_124 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_124 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_29 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -13202,7 +13232,7 @@ sky130_fd_sc_hd__inv_1 BINV_R_122 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , endmodule -module sb_2__2__mux_tree_tapbuf_size2_30 ( in , sram , sram_inv , out , VDD , +module sb_2__2__mux_tree_tapbuf_size2_28 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; input [0:1] in ; input [0:1] sram ; @@ -13230,62 +13260,6 @@ sky130_fd_sc_hd__inv_1 BINV_R_120 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , endmodule -module sb_2__2__mux_tree_tapbuf_size2_29 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_117 ( .A ( BUF_net_118 ) , .Y ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_118 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_118 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_28 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_145 ( .A ( BUF_net_146 ) , .Y ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_146 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_146 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - module sb_2__2__mux_tree_tapbuf_size2_27 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; input [0:1] in ; @@ -13334,10 +13308,10 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_113 ( .A ( BUF_net_114 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_117 ( .A ( BUF_net_118 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_114 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_114 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_118 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_118 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -13362,10 +13336,10 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_111 ( .A ( BUF_net_112 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_115 ( .A ( BUF_net_116 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_112 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_112 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_116 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_116 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -13390,10 +13364,10 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_109 ( .A ( BUF_net_110 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_113 ( .A ( BUF_net_114 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_110 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_110 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_114 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_114 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -13412,15 +13386,16 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_147 ( .A ( BUF_net_148 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_148 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_148 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -13439,14 +13414,15 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_108 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -13465,6 +13441,32 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_110 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_20 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -13477,32 +13479,6 @@ sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module sb_2__2__mux_tree_tapbuf_size2_20 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_107 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - module sb_2__2__mux_tree_tapbuf_size2_19 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; input [0:1] in ; @@ -13524,10 +13500,10 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_105 ( .A ( BUF_net_106 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_108 ( .A ( BUF_net_109 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_106 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_106 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_109 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_109 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -13552,10 +13528,10 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_103 ( .A ( BUF_net_104 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_106 ( .A ( BUF_net_107 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_104 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_104 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_107 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_107 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -13580,10 +13556,10 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_101 ( .A ( BUF_net_102 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_104 ( .A ( BUF_net_105 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_102 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_102 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_105 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_105 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -13629,15 +13605,16 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_102 ( .A ( BUF_net_103 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_103 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_103 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -13662,10 +13639,10 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_99 ( .A ( BUF_net_100 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_100 ( .A ( BUF_net_101 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_100 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_100 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_101 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_101 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -13690,10 +13667,10 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_97 ( .A ( BUF_net_98 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_98 ( .A ( BUF_net_99 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_98 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_98 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_99 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_99 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -13718,10 +13695,10 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_95 ( .A ( BUF_net_96 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_96 ( .A ( BUF_net_97 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_96 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_96 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_97 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_97 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -13740,15 +13717,16 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_94 ( .A ( BUF_net_95 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_95 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_95 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -13767,16 +13745,15 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_93 ( .A ( BUF_net_94 ) , .Y ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_94 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_94 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -13795,15 +13772,14 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_93 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -13828,10 +13804,8 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_91 ( .A ( BUF_net_92 ) , .Y ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_92 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_92 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_92 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -13856,10 +13830,10 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_89 ( .A ( BUF_net_90 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_90 ( .A ( BUF_net_91 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_90 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_90 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_91 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_91 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -13884,10 +13858,10 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_87 ( .A ( BUF_net_88 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_88 ( .A ( BUF_net_89 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_88 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_88 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_89 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_89 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -13912,10 +13886,10 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_85 ( .A ( BUF_net_86 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_86 ( .A ( BUF_net_87 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_86 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_86 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_87 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_87 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -13940,10 +13914,10 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_83 ( .A ( BUF_net_84 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_84 ( .A ( BUF_net_85 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_84 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_84 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_85 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_85 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -13968,10 +13942,10 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_81 ( .A ( BUF_net_82 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_82 ( .A ( BUF_net_83 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_82 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_82 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_83 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_83 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -13996,10 +13970,10 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_79 ( .A ( BUF_net_80 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_80 ( .A ( BUF_net_81 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_80 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_80 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_81 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_81 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -14024,7 +13998,7 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_78 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_79 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -14044,14 +14018,15 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_77 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -14365,7 +14340,7 @@ input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_207 ) , +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_195 ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , @@ -14376,28 +14351,28 @@ sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1339 ( .A ( copt_net_166 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1326 ( .A ( ccff_head[0] ) , + .X ( copt_net_156 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1327 ( .A ( copt_net_156 ) , + .X ( copt_net_157 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1328 ( .A ( copt_net_157 ) , + .X ( copt_net_158 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1329 ( .A ( copt_net_158 ) , + .X ( copt_net_159 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1330 ( .A ( ropt_net_198 ) , + .X ( copt_net_160 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1331 ( .A ( copt_net_160 ) , .X ( copt_net_161 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1340 ( .A ( ccff_head[0] ) , - .X ( copt_net_162 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1341 ( .A ( copt_net_161 ) , - .X ( copt_net_163 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1342 ( .A ( copt_net_162 ) , - .X ( copt_net_164 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1343 ( .A ( copt_net_163 ) , - .X ( copt_net_165 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1344 ( .A ( copt_net_164 ) , - .X ( copt_net_166 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1378 ( .A ( copt_net_165 ) , - .X ( ropt_net_203 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1379 ( .A ( ropt_net_205 ) , - .X ( ropt_net_204 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1380 ( .A ( ropt_net_203 ) , - .X ( ropt_net_205 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1381 ( .A ( ropt_net_204 ) , - .X ( ropt_net_206 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 ropt_h_inst_1382 ( .A ( ropt_net_206 ) , - .X ( ropt_net_207 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1365 ( .A ( copt_net_161 ) , + .X ( ropt_net_195 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1366 ( .A ( copt_net_159 ) , + .X ( ropt_net_196 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1367 ( .A ( ropt_net_196 ) , + .X ( ropt_net_197 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1368 ( .A ( ropt_net_199 ) , + .X ( ropt_net_198 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 ropt_h_inst_1369 ( .A ( ropt_net_197 ) , + .X ( ropt_net_199 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -14467,10 +14442,10 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_143 ( .A ( BUF_net_144 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_77 ( .A ( BUF_net_78 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_144 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .Y ( BUF_net_144 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_78 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_78 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -14504,10 +14479,10 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_73 ( .A ( BUF_net_74 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_75 ( .A ( BUF_net_76 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_74 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .Y ( BUF_net_74 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_76 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_76 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -14528,9 +14503,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -14540,10 +14512,14 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_74 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_74 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_141 ( .A ( BUF_net_74 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -14685,8 +14661,10 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_69 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_68 ( .A ( BUF_net_69 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_69 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_69 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -14720,10 +14698,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_67 ( .A ( BUF_net_68 ) , .Y ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_68 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .Y ( BUF_net_68 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_67 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -14882,7 +14858,7 @@ input prog_clk_0_S_in ; input VDD ; input VSS ; -wire ropt_net_182 ; +wire ropt_net_177 ; wire [0:0] prog_clk ; wire prog_clk_0 ; wire [0:1] mux_tree_tapbuf_size2_0_sram ; @@ -15002,7 +14978,7 @@ sb_2__2__mux_tree_tapbuf_size4_0 mux_bottom_track_1 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 } ) , .out ( chany_bottom_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_153 ) ) ; + .p0 ( optlc_net_154 ) ) ; sb_2__2__mux_tree_tapbuf_size4_1 mux_bottom_track_3 ( .in ( { bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_47_[0] , bottom_left_grid_pin_50_[0] , chanx_left_in[2] } ) , @@ -15010,7 +14986,7 @@ sb_2__2__mux_tree_tapbuf_size4_1 mux_bottom_track_3 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 } ) , .out ( chany_bottom_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_153 ) ) ; + .p0 ( optlc_net_154 ) ) ; sb_2__2__mux_tree_tapbuf_size4_2 mux_bottom_track_5 ( .in ( { bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_48_[0] , bottom_left_grid_pin_51_[0] , chanx_left_in[3] } ) , @@ -15018,7 +14994,7 @@ sb_2__2__mux_tree_tapbuf_size4_2 mux_bottom_track_5 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 , SYNOPSYS_UNCONNECTED_9 } ) , .out ( chany_bottom_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_153 ) ) ; + .p0 ( optlc_net_154 ) ) ; sb_2__2__mux_tree_tapbuf_size4_3 mux_bottom_track_7 ( .in ( { bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_46_[0] , bottom_left_grid_pin_49_[0] , chanx_left_in[4] } ) , @@ -15026,7 +15002,7 @@ sb_2__2__mux_tree_tapbuf_size4_3 mux_bottom_track_7 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , .out ( chany_bottom_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_153 ) ) ; + .p0 ( optlc_net_154 ) ) ; sb_2__2__mux_tree_tapbuf_size4_4 mux_bottom_track_9 ( .in ( { bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_47_[0] , bottom_left_grid_pin_50_[0] , chanx_left_in[5] } ) , @@ -15034,7 +15010,7 @@ sb_2__2__mux_tree_tapbuf_size4_4 mux_bottom_track_9 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , SYNOPSYS_UNCONNECTED_15 } ) , .out ( chany_bottom_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_158 ) ) ; + .p0 ( optlc_net_155 ) ) ; sb_2__2__mux_tree_tapbuf_size4_5 mux_bottom_track_11 ( .in ( { bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_48_[0] , bottom_left_grid_pin_51_[0] , chanx_left_in[6] } ) , @@ -15042,7 +15018,7 @@ sb_2__2__mux_tree_tapbuf_size4_5 mux_bottom_track_11 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_16 , SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 } ) , .out ( chany_bottom_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_153 ) ) ; + .p0 ( optlc_net_155 ) ) ; sb_2__2__mux_tree_tapbuf_size4_6 mux_left_track_1 ( .in ( { chany_bottom_in[29] , left_top_grid_pin_1_[0] , left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_41_[0] } ) , @@ -15050,7 +15026,7 @@ sb_2__2__mux_tree_tapbuf_size4_6 mux_left_track_1 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 , SYNOPSYS_UNCONNECTED_21 } ) , .out ( chanx_left_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_154 ) ) ; + .p0 ( optlc_net_151 ) ) ; sb_2__2__mux_tree_tapbuf_size4_7 mux_left_track_3 ( .in ( { chany_bottom_in[0] , left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_42_[0] } ) , @@ -15058,7 +15034,7 @@ sb_2__2__mux_tree_tapbuf_size4_7 mux_left_track_3 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_22 , SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) , .out ( chanx_left_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_156 ) ) ; + .p0 ( optlc_net_151 ) ) ; sb_2__2__mux_tree_tapbuf_size4_8 mux_left_track_5 ( .in ( { chany_bottom_in[1] , left_bottom_grid_pin_37_[0] , left_bottom_grid_pin_40_[0] , left_bottom_grid_pin_43_[0] } ) , @@ -15066,7 +15042,7 @@ sb_2__2__mux_tree_tapbuf_size4_8 mux_left_track_5 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , SYNOPSYS_UNCONNECTED_27 } ) , .out ( chanx_left_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_159 ) ) ; + .p0 ( optlc_net_151 ) ) ; sb_2__2__mux_tree_tapbuf_size4_9 mux_left_track_7 ( .in ( { chany_bottom_in[2] , left_top_grid_pin_1_[0] , left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_41_[0] } ) , @@ -15074,7 +15050,7 @@ sb_2__2__mux_tree_tapbuf_size4_9 mux_left_track_7 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_28 , SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 } ) , .out ( chanx_left_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_155 ) ) ; + .p0 ( optlc_net_151 ) ) ; sb_2__2__mux_tree_tapbuf_size4_10 mux_left_track_9 ( .in ( { chany_bottom_in[3] , left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_42_[0] } ) , @@ -15082,7 +15058,7 @@ sb_2__2__mux_tree_tapbuf_size4_10 mux_left_track_9 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 , SYNOPSYS_UNCONNECTED_33 } ) , .out ( chanx_left_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_156 ) ) ; + .p0 ( optlc_net_151 ) ) ; sb_2__2__mux_tree_tapbuf_size4 mux_left_track_11 ( .in ( { chany_bottom_in[4] , left_bottom_grid_pin_37_[0] , left_bottom_grid_pin_40_[0] , left_bottom_grid_pin_43_[0] } ) , @@ -15090,7 +15066,7 @@ sb_2__2__mux_tree_tapbuf_size4 mux_left_track_11 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_34 , SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) , .out ( chanx_left_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_159 ) ) ; + .p0 ( optlc_net_151 ) ) ; sb_2__2__mux_tree_tapbuf_size4_mem_0 mem_bottom_track_1 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , @@ -15155,223 +15131,223 @@ sb_2__2__mux_tree_tapbuf_size2_0 mux_bottom_track_13 ( .sram ( mux_tree_tapbuf_size2_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 } ) , .out ( chany_bottom_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_157 ) ) ; + .p0 ( optlc_net_152 ) ) ; sb_2__2__mux_tree_tapbuf_size2_1 mux_bottom_track_15 ( .in ( { bottom_left_grid_pin_44_[0] , chanx_left_in[8] } ) , .sram ( mux_tree_tapbuf_size2_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) , .out ( chany_bottom_out[7] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_158 ) ) ; + .p0 ( optlc_net_152 ) ) ; sb_2__2__mux_tree_tapbuf_size2_2 mux_bottom_track_17 ( .in ( { bottom_left_grid_pin_45_[0] , chanx_left_in[9] } ) , .sram ( mux_tree_tapbuf_size2_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 } ) , .out ( chany_bottom_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_155 ) ) ; + .p0 ( optlc_net_151 ) ) ; sb_2__2__mux_tree_tapbuf_size2_3 mux_bottom_track_19 ( .in ( { bottom_left_grid_pin_46_[0] , chanx_left_in[10] } ) , .sram ( mux_tree_tapbuf_size2_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) , .out ( chany_bottom_out[9] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_155 ) ) ; + .p0 ( optlc_net_151 ) ) ; sb_2__2__mux_tree_tapbuf_size2_4 mux_bottom_track_21 ( .in ( { bottom_left_grid_pin_47_[0] , chanx_left_in[11] } ) , .sram ( mux_tree_tapbuf_size2_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 } ) , .out ( chany_bottom_out[10] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_154 ) ) ; + .p0 ( optlc_net_151 ) ) ; sb_2__2__mux_tree_tapbuf_size2_5 mux_bottom_track_23 ( .in ( { bottom_left_grid_pin_48_[0] , chanx_left_in[12] } ) , .sram ( mux_tree_tapbuf_size2_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) , .out ( chany_bottom_out[11] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_153 ) ) ; + .p0 ( optlc_net_154 ) ) ; sb_2__2__mux_tree_tapbuf_size2_6 mux_bottom_track_25 ( .in ( { bottom_left_grid_pin_49_[0] , chanx_left_in[13] } ) , .sram ( mux_tree_tapbuf_size2_6_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 } ) , .out ( chany_bottom_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_153 ) ) ; + .p0 ( optlc_net_151 ) ) ; sb_2__2__mux_tree_tapbuf_size2_7 mux_bottom_track_27 ( .in ( { bottom_left_grid_pin_50_[0] , chanx_left_in[14] } ) , .sram ( mux_tree_tapbuf_size2_7_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) , .out ( chany_bottom_out[13] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_155 ) ) ; + .p0 ( optlc_net_151 ) ) ; sb_2__2__mux_tree_tapbuf_size2_8 mux_bottom_track_39 ( .in ( { bottom_left_grid_pin_44_[0] , chanx_left_in[20] } ) , .sram ( mux_tree_tapbuf_size2_8_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 } ) , .out ( chany_bottom_out[19] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_154 ) ) ; + .p0 ( optlc_net_152 ) ) ; sb_2__2__mux_tree_tapbuf_size2_9 mux_bottom_track_41 ( .in ( { bottom_left_grid_pin_45_[0] , chanx_left_in[21] } ) , .sram ( mux_tree_tapbuf_size2_9_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) , .out ( chany_bottom_out[20] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_153 ) ) ; + .p0 ( optlc_net_152 ) ) ; sb_2__2__mux_tree_tapbuf_size2_10 mux_bottom_track_43 ( .in ( { bottom_left_grid_pin_46_[0] , chanx_left_in[22] } ) , .sram ( mux_tree_tapbuf_size2_10_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 } ) , .out ( chany_bottom_out[21] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_157 ) ) ; + .p0 ( optlc_net_152 ) ) ; sb_2__2__mux_tree_tapbuf_size2_11 mux_bottom_track_47 ( .in ( { bottom_left_grid_pin_48_[0] , chanx_left_in[24] } ) , .sram ( mux_tree_tapbuf_size2_11_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) , .out ( chany_bottom_out[23] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_153 ) ) ; + .p0 ( optlc_net_155 ) ) ; sb_2__2__mux_tree_tapbuf_size2_12 mux_bottom_track_49 ( .in ( { bottom_left_grid_pin_49_[0] , chanx_left_in[25] } ) , .sram ( mux_tree_tapbuf_size2_12_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 } ) , .out ( chany_bottom_out[24] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_153 ) ) ; + .p0 ( optlc_net_154 ) ) ; sb_2__2__mux_tree_tapbuf_size2_13 mux_bottom_track_51 ( .in ( { bottom_left_grid_pin_50_[0] , chanx_left_in[26] } ) , .sram ( mux_tree_tapbuf_size2_13_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) , .out ( chany_bottom_out[25] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_155 ) ) ; + .p0 ( optlc_net_151 ) ) ; sb_2__2__mux_tree_tapbuf_size2_14 mux_bottom_track_53 ( .in ( { bottom_left_grid_pin_51_[0] , chanx_left_in[27] } ) , .sram ( mux_tree_tapbuf_size2_14_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 } ) , .out ( chany_bottom_out[26] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_155 ) ) ; + .p0 ( optlc_net_151 ) ) ; sb_2__2__mux_tree_tapbuf_size2_15 mux_left_track_13 ( .in ( { chany_bottom_in[5] , left_top_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size2_15_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 } ) , .out ( chanx_left_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_160 ) ) ; + .p0 ( optlc_net_153 ) ) ; sb_2__2__mux_tree_tapbuf_size2_16 mux_left_track_15 ( .in ( { chany_bottom_in[6] , left_bottom_grid_pin_36_[0] } ) , .sram ( mux_tree_tapbuf_size2_16_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_69 , SYNOPSYS_UNCONNECTED_70 } ) , .out ( chanx_left_out[7] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_156 ) ) ; + .p0 ( optlc_net_152 ) ) ; sb_2__2__mux_tree_tapbuf_size2_17 mux_left_track_17 ( .in ( { chany_bottom_in[7] , left_bottom_grid_pin_37_[0] } ) , .sram ( mux_tree_tapbuf_size2_17_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_71 , SYNOPSYS_UNCONNECTED_72 } ) , .out ( chanx_left_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_156 ) ) ; + .p0 ( optlc_net_153 ) ) ; sb_2__2__mux_tree_tapbuf_size2_18 mux_left_track_19 ( .in ( { chany_bottom_in[8] , left_bottom_grid_pin_38_[0] } ) , .sram ( mux_tree_tapbuf_size2_18_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_73 , SYNOPSYS_UNCONNECTED_74 } ) , .out ( chanx_left_out[9] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_157 ) ) ; + .p0 ( optlc_net_152 ) ) ; sb_2__2__mux_tree_tapbuf_size2_19 mux_left_track_21 ( .in ( { chany_bottom_in[9] , left_bottom_grid_pin_39_[0] } ) , .sram ( mux_tree_tapbuf_size2_19_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_75 , SYNOPSYS_UNCONNECTED_76 } ) , .out ( chanx_left_out[10] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_157 ) ) ; + .p0 ( optlc_net_152 ) ) ; sb_2__2__mux_tree_tapbuf_size2_20 mux_left_track_23 ( .in ( { chany_bottom_in[10] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_tree_tapbuf_size2_20_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_77 , SYNOPSYS_UNCONNECTED_78 } ) , .out ( chanx_left_out[11] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_157 ) ) ; + .p0 ( optlc_net_152 ) ) ; sb_2__2__mux_tree_tapbuf_size2_21 mux_left_track_25 ( .in ( { chany_bottom_in[11] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size2_21_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_79 , SYNOPSYS_UNCONNECTED_80 } ) , .out ( chanx_left_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_158 ) ) ; + .p0 ( optlc_net_152 ) ) ; sb_2__2__mux_tree_tapbuf_size2_22 mux_left_track_27 ( .in ( { chany_bottom_in[12] , left_bottom_grid_pin_42_[0] } ) , .sram ( mux_tree_tapbuf_size2_22_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_81 , SYNOPSYS_UNCONNECTED_82 } ) , .out ( chanx_left_out[13] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_157 ) ) ; + .p0 ( optlc_net_152 ) ) ; sb_2__2__mux_tree_tapbuf_size2_23 mux_left_track_31 ( .in ( { chany_bottom_in[14] , left_bottom_grid_pin_36_[0] } ) , .sram ( mux_tree_tapbuf_size2_23_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_83 , SYNOPSYS_UNCONNECTED_84 } ) , .out ( chanx_left_out[15] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_157 ) ) ; + .p0 ( optlc_net_152 ) ) ; sb_2__2__mux_tree_tapbuf_size2_24 mux_left_track_33 ( .in ( { chany_bottom_in[15] , left_bottom_grid_pin_37_[0] } ) , .sram ( mux_tree_tapbuf_size2_24_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_85 , SYNOPSYS_UNCONNECTED_86 } ) , .out ( chanx_left_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_160 ) ) ; + .p0 ( optlc_net_153 ) ) ; sb_2__2__mux_tree_tapbuf_size2_25 mux_left_track_35 ( .in ( { chany_bottom_in[16] , left_bottom_grid_pin_38_[0] } ) , .sram ( mux_tree_tapbuf_size2_25_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_87 , SYNOPSYS_UNCONNECTED_88 } ) , .out ( chanx_left_out[17] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_160 ) ) ; + .p0 ( optlc_net_153 ) ) ; sb_2__2__mux_tree_tapbuf_size2_26 mux_left_track_37 ( .in ( { chany_bottom_in[17] , left_bottom_grid_pin_39_[0] } ) , .sram ( mux_tree_tapbuf_size2_26_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_89 , SYNOPSYS_UNCONNECTED_90 } ) , .out ( chanx_left_out[18] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_160 ) ) ; + .p0 ( optlc_net_153 ) ) ; sb_2__2__mux_tree_tapbuf_size2_27 mux_left_track_39 ( .in ( { chany_bottom_in[18] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_tree_tapbuf_size2_27_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_91 , SYNOPSYS_UNCONNECTED_92 } ) , .out ( chanx_left_out[19] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_157 ) ) ; + .p0 ( optlc_net_152 ) ) ; sb_2__2__mux_tree_tapbuf_size2_28 mux_left_track_41 ( .in ( { chany_bottom_in[19] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size2_28_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_93 , SYNOPSYS_UNCONNECTED_94 } ) , .out ( chanx_left_out[20] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_154 ) ) ; + .p0 ( optlc_net_152 ) ) ; sb_2__2__mux_tree_tapbuf_size2_29 mux_left_track_43 ( .in ( { chany_bottom_in[20] , left_bottom_grid_pin_42_[0] } ) , .sram ( mux_tree_tapbuf_size2_29_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_95 , SYNOPSYS_UNCONNECTED_96 } ) , .out ( chanx_left_out[21] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_154 ) ) ; + .p0 ( optlc_net_152 ) ) ; sb_2__2__mux_tree_tapbuf_size2_30 mux_left_track_45 ( .in ( { chany_bottom_in[21] , left_top_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size2_30_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_97 , SYNOPSYS_UNCONNECTED_98 } ) , .out ( chanx_left_out[22] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_154 ) ) ; + .p0 ( optlc_net_153 ) ) ; sb_2__2__mux_tree_tapbuf_size2_31 mux_left_track_47 ( .in ( { chany_bottom_in[22] , left_bottom_grid_pin_36_[0] } ) , .sram ( mux_tree_tapbuf_size2_31_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_99 , SYNOPSYS_UNCONNECTED_100 } ) , .out ( chanx_left_out[23] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_156 ) ) ; + .p0 ( optlc_net_153 ) ) ; sb_2__2__mux_tree_tapbuf_size2_32 mux_left_track_49 ( .in ( { chany_bottom_in[23] , left_bottom_grid_pin_37_[0] } ) , .sram ( mux_tree_tapbuf_size2_32_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_101 , SYNOPSYS_UNCONNECTED_102 } ) , .out ( chanx_left_out[24] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_156 ) ) ; + .p0 ( optlc_net_151 ) ) ; sb_2__2__mux_tree_tapbuf_size2_33 mux_left_track_51 ( .in ( { chany_bottom_in[24] , left_bottom_grid_pin_38_[0] } ) , .sram ( mux_tree_tapbuf_size2_33_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_103 , SYNOPSYS_UNCONNECTED_104 } ) , .out ( chanx_left_out[25] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_154 ) ) ; + .p0 ( optlc_net_151 ) ) ; sb_2__2__mux_tree_tapbuf_size2_34 mux_left_track_55 ( .in ( { chany_bottom_in[26] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_tree_tapbuf_size2_34_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_105 , SYNOPSYS_UNCONNECTED_106 } ) , .out ( chanx_left_out[27] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_154 ) ) ; + .p0 ( optlc_net_151 ) ) ; sb_2__2__mux_tree_tapbuf_size2_35 mux_left_track_57 ( .in ( { chany_bottom_in[27] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size2_35_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_107 , SYNOPSYS_UNCONNECTED_108 } ) , .out ( chanx_left_out[28] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_158 ) ) ; + .p0 ( optlc_net_155 ) ) ; sb_2__2__mux_tree_tapbuf_size2 mux_left_track_59 ( .in ( { chany_bottom_in[28] , left_bottom_grid_pin_42_[0] } ) , .sram ( mux_tree_tapbuf_size2_36_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_109 , SYNOPSYS_UNCONNECTED_110 } ) , .out ( chanx_left_out[29] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_158 ) ) ; + .p0 ( optlc_net_155 ) ) ; sb_2__2__mux_tree_tapbuf_size2_mem_0 mem_bottom_track_13 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) , @@ -15563,28 +15539,28 @@ sb_2__2__mux_tree_tapbuf_size3_0 mux_bottom_track_29 ( .sram ( mux_tree_tapbuf_size3_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_111 , SYNOPSYS_UNCONNECTED_112 } ) , .out ( chany_bottom_out[14] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_155 ) ) ; + .p0 ( optlc_net_154 ) ) ; sb_2__2__mux_tree_tapbuf_size3_1 mux_bottom_track_45 ( .in ( { bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_47_[0] , chanx_left_in[23] } ) , .sram ( mux_tree_tapbuf_size3_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_113 , SYNOPSYS_UNCONNECTED_114 } ) , .out ( chany_bottom_out[22] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_153 ) ) ; + .p0 ( optlc_net_155 ) ) ; sb_2__2__mux_tree_tapbuf_size3_2 mux_left_track_29 ( .in ( { chany_bottom_in[13] , left_top_grid_pin_1_[0] , left_bottom_grid_pin_43_[0] } ) , .sram ( mux_tree_tapbuf_size3_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_115 , SYNOPSYS_UNCONNECTED_116 } ) , .out ( chanx_left_out[14] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_154 ) ) ; + .p0 ( optlc_net_153 ) ) ; sb_2__2__mux_tree_tapbuf_size3 mux_left_track_53 ( .in ( { chany_bottom_in[25] , left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_43_[0] } ) , .sram ( mux_tree_tapbuf_size3_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_117 , SYNOPSYS_UNCONNECTED_118 } ) , .out ( chanx_left_out[26] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_156 ) ) ; + .p0 ( optlc_net_151 ) ) ; sb_2__2__mux_tree_tapbuf_size3_mem_0 mem_bottom_track_29 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , @@ -15609,10 +15585,10 @@ sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_W_in ) , .X ( pReset[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_S_in ) , .X ( prog_clk[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 FTB_54__53 ( .A ( chanx_left_in[0] ) , - .X ( ropt_net_182 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chanx_left_in[16] ) , - .X ( chany_bottom_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chanx_left_in[0] ) , + .X ( chany_bottom_out[29] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_55__54 ( .A ( chanx_left_in[16] ) , + .X ( ropt_net_177 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chanx_left_in[17] ) , .X ( chany_bottom_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chanx_left_in[18] ) , @@ -15625,24 +15601,18 @@ sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( chanx_left_in[29] ) , .X ( chany_bottom_out[28] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_6 FTB_61__60 ( .A ( SC_IN_BOT ) , .X ( SC_OUT_BOT ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_157 ( .LO ( SYNOPSYS_UNCONNECTED_119 ) , +sky130_fd_sc_hd__conb_1 optlc_153 ( .LO ( SYNOPSYS_UNCONNECTED_119 ) , + .HI ( optlc_net_151 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_158 ( .LO ( SYNOPSYS_UNCONNECTED_120 ) , + .HI ( optlc_net_152 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_160 ( .LO ( SYNOPSYS_UNCONNECTED_121 ) , .HI ( optlc_net_153 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_161 ( .LO ( SYNOPSYS_UNCONNECTED_120 ) , +sky130_fd_sc_hd__conb_1 optlc_162 ( .LO ( SYNOPSYS_UNCONNECTED_122 ) , .HI ( optlc_net_154 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_164 ( .LO ( SYNOPSYS_UNCONNECTED_121 ) , +sky130_fd_sc_hd__conb_1 optlc_164 ( .LO ( SYNOPSYS_UNCONNECTED_123 ) , .HI ( optlc_net_155 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_168 ( .LO ( SYNOPSYS_UNCONNECTED_122 ) , - .HI ( optlc_net_156 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_170 ( .LO ( SYNOPSYS_UNCONNECTED_123 ) , - .HI ( optlc_net_157 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_173 ( .LO ( SYNOPSYS_UNCONNECTED_124 ) , - .HI ( optlc_net_158 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_175 ( .LO ( SYNOPSYS_UNCONNECTED_125 ) , - .HI ( optlc_net_159 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_177 ( .LO ( SYNOPSYS_UNCONNECTED_126 ) , - .HI ( optlc_net_160 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1359 ( .A ( ropt_net_182 ) , - .X ( chany_bottom_out[29] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1347 ( .A ( ropt_net_177 ) , + .X ( chany_bottom_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -18736,7 +18706,7 @@ input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_166 ) , +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_172 ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , @@ -18760,16 +18730,16 @@ sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1322 ( .A ( copt_net_145 ) , .X ( copt_net_148 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1323 ( .A ( ccff_head[0] ) , .X ( copt_net_149 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1324 ( .A ( ropt_net_168 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1324 ( .A ( ropt_net_174 ) , .X ( copt_net_150 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1332 ( .A ( copt_net_147 ) , .X ( copt_net_158 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 ropt_h_inst_1337 ( .A ( copt_net_150 ) , - .X ( ropt_net_166 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1338 ( .A ( copt_net_158 ) , - .X ( ropt_net_167 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1339 ( .A ( ropt_net_167 ) , - .X ( ropt_net_168 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 ropt_h_inst_1343 ( .A ( copt_net_150 ) , + .X ( ropt_net_172 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1344 ( .A ( copt_net_158 ) , + .X ( ropt_net_173 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1345 ( .A ( ropt_net_173 ) , + .X ( ropt_net_174 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -19047,6 +19017,7 @@ input prog_clk_0_N_in ; input VDD ; input VSS ; +wire ropt_net_162 ; wire [0:0] prog_clk ; wire prog_clk_0 ; wire [0:3] mux_tree_tapbuf_size10_0_sram ; @@ -19328,7 +19299,7 @@ sb_2__1__mux_tree_tapbuf_size9_1 mux_top_track_10 ( .out ( chany_top_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_142 ) ) ; sb_2__1__mux_tree_tapbuf_size9 mux_bottom_track_11 ( - .in ( { chany_bottom_out[11] , chany_bottom_out[25] , + .in ( { ropt_net_162 , chany_bottom_out[25] , bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_46_[0] , bottom_left_grid_pin_48_[0] , bottom_left_grid_pin_50_[0] , chanx_left_in[5] , chanx_left_in[16] , chanx_left_in[27] } ) , @@ -19483,7 +19454,7 @@ sb_2__1__mux_tree_tapbuf_size6_3 mux_left_track_7 ( .out ( chanx_left_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_143 ) ) ; sb_2__1__mux_tree_tapbuf_size6 mux_left_track_9 ( - .in ( { chany_bottom_out[11] , chany_bottom_in[4] , chany_top_out[11] , + .in ( { ropt_net_162 , chany_bottom_in[4] , chany_top_out[11] , left_bottom_grid_pin_37_[0] , left_bottom_grid_pin_40_[0] , left_bottom_grid_pin_43_[0] } ) , .sram ( mux_tree_tapbuf_size6_4_sram ) , @@ -19809,8 +19780,8 @@ sky130_fd_sc_hd__buf_8 FTB_53__52 ( .A ( chany_top_in[7] ) , .X ( chany_bottom_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chany_top_in[8] ) , .X ( chany_bottom_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chany_top_in[10] ) , - .X ( chany_bottom_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_55__54 ( .A ( chany_top_in[10] ) , + .X ( ropt_net_162 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chany_top_in[11] ) , .X ( chany_bottom_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chany_top_in[12] ) , @@ -19891,6 +19862,8 @@ sky130_fd_sc_hd__conb_1 optlc_149 ( .LO ( SYNOPSYS_UNCONNECTED_144 ) , .HI ( optlc_net_143 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__conb_1 optlc_151 ( .LO ( SYNOPSYS_UNCONNECTED_145 ) , .HI ( optlc_net_144 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1336 ( .A ( ropt_net_162 ) , + .X ( chany_bottom_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -19904,7 +19877,7 @@ output [0:1] mem_out ; input VDD ; input VSS ; -wire copt_net_164 ; +wire copt_net_181 ; supply1 VDD ; supply0 VSS ; @@ -19912,11 +19885,11 @@ sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( copt_net_164 ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( copt_net_181 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_6 FTB_53__52 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1327 ( .A ( copt_net_164 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1345 ( .A ( copt_net_181 ) , .X ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -20782,9 +20755,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_119 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_119 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_142 ( .A ( BUF_net_119 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_2 BINV_R_124 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_124 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_159 ( .A ( BUF_net_124 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -20810,10 +20783,10 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_117 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_117 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_148 ( .A ( BUF_net_117 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_121 ( .A ( BUF_net_122 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_122 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_122 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -20838,7 +20811,7 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_115 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_120 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -20864,10 +20837,10 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_113 ( .A ( BUF_net_114 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_6 BINV_R_118 ( .A ( BUF_net_119 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_114 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_114 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_119 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_119 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -20889,13 +20862,11 @@ supply0 VSS ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_111 ( .A ( BUF_net_112 ) , .Y ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_112 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_112 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_117 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -20947,7 +20918,7 @@ sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -20974,10 +20945,10 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_109 ( .A ( BUF_net_110 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_2 BINV_R_116 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_116 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_157 ( .A ( BUF_net_116 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_110 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_110 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -20996,15 +20967,14 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_114 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -21029,9 +20999,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_108 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_108 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_140 ( .A ( BUF_net_108 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_2 BINV_R_113 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_113 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_155 ( .A ( BUF_net_113 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -21081,11 +21051,13 @@ supply0 VSS ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_106 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_111 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_111 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_153 ( .A ( BUF_net_111 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -21110,7 +21082,7 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_105 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_109 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -21160,11 +21132,13 @@ supply0 VSS ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_104 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_108 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_108 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_151 ( .A ( BUF_net_108 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -21189,10 +21163,10 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_102 ( .A ( BUF_net_103 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_6 BINV_R_105 ( .A ( BUF_net_106 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_103 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_103 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_106 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_106 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -21211,15 +21185,14 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_104 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -21244,9 +21217,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_101 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_101 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_138 ( .A ( BUF_net_101 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_2 BINV_R_103 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_103 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_149 ( .A ( BUF_net_103 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -21296,11 +21269,13 @@ supply0 VSS ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_99 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_100 ( .A ( BUF_net_101 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_101 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_101 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -21325,9 +21300,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_98 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_98 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_136 ( .A ( BUF_net_98 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_2 BINV_R_99 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_99 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_147 ( .A ( BUF_net_99 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -21347,15 +21322,16 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_97 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_97 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_145 ( .A ( BUF_net_97 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -21428,16 +21404,15 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_96 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_96 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_134 ( .A ( BUF_net_96 ) , .Y ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -21462,9 +21437,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_94 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_94 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_146 ( .A ( BUF_net_94 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_2 BINV_R_95 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_95 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_143 ( .A ( BUF_net_95 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -21490,10 +21465,10 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_91 ( .A ( BUF_net_92 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_6 BINV_R_92 ( .A ( BUF_net_93 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_92 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_92 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_93 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_93 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -21545,10 +21520,8 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_89 ( .A ( BUF_net_90 ) , .Y ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_90 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_90 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_91 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -21627,8 +21600,10 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_88 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_90 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_90 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_141 ( .A ( BUF_net_90 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -21647,15 +21622,16 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_87 ( .A ( BUF_net_88 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_88 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_88 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -21680,9 +21656,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_87 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_87 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_132 ( .A ( BUF_net_87 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_2 BINV_R_86 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_86 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_139 ( .A ( BUF_net_86 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -21708,9 +21684,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_85 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_85 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_130 ( .A ( BUF_net_85 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_2 BINV_R_84 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_84 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_137 ( .A ( BUF_net_84 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -21736,9 +21712,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_83 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_83 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_128 ( .A ( BUF_net_83 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_2 BINV_R_82 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_82 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_135 ( .A ( BUF_net_82 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -21889,10 +21865,10 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_81 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .Y ( BUF_net_81 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_126 ( .A ( BUF_net_81 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_79 ( .A ( BUF_net_80 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_80 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .Y ( BUF_net_80 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -21912,6 +21888,9 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -21922,8 +21901,6 @@ sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_79 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -21955,7 +21932,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__inv_2 BINV_R_78 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .Y ( BUF_net_78 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_124 ( .A ( BUF_net_78 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_6 BINV_R_133 ( .A ( BUF_net_78 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -22008,9 +21985,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -22021,6 +21995,10 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_76 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .Y ( BUF_net_76 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_131 ( .A ( BUF_net_76 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -22334,7 +22312,7 @@ input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( copt_net_156 ) , +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_201 ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , @@ -22345,28 +22323,28 @@ sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1318 ( .A ( copt_net_158 ) , - .X ( copt_net_154 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1319 ( .A ( copt_net_154 ) , - .X ( copt_net_155 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1320 ( .A ( copt_net_155 ) , - .X ( copt_net_156 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1321 ( .A ( ccff_head[0] ) , - .X ( copt_net_157 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1322 ( .A ( ropt_net_192 ) , - .X ( copt_net_158 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1323 ( .A ( copt_net_157 ) , - .X ( copt_net_159 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1393 ( .A ( ropt_net_196 ) , - .X ( ropt_net_192 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1394 ( .A ( copt_net_159 ) , - .X ( ropt_net_193 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1395 ( .A ( ropt_net_193 ) , - .X ( ropt_net_194 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1396 ( .A ( ropt_net_194 ) , - .X ( ropt_net_195 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_1 ropt_h_inst_1397 ( .A ( ropt_net_195 ) , - .X ( ropt_net_196 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1336 ( .A ( ccff_head[0] ) , + .X ( copt_net_170 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1337 ( .A ( copt_net_172 ) , + .X ( copt_net_171 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1338 ( .A ( copt_net_170 ) , + .X ( copt_net_172 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1339 ( .A ( copt_net_175 ) , + .X ( copt_net_173 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1340 ( .A ( copt_net_173 ) , + .X ( copt_net_174 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1341 ( .A ( copt_net_171 ) , + .X ( copt_net_175 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1361 ( .A ( copt_net_174 ) , + .X ( ropt_net_197 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1362 ( .A ( ropt_net_197 ) , + .X ( ropt_net_198 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1363 ( .A ( ropt_net_198 ) , + .X ( ropt_net_199 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1364 ( .A ( ropt_net_199 ) , + .X ( ropt_net_200 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 ropt_h_inst_1365 ( .A ( ropt_net_200 ) , + .X ( ropt_net_201 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -22400,9 +22378,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_76 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .Y ( BUF_net_76 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_122 ( .A ( BUF_net_76 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_2 BINV_R_74 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_74 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_129 ( .A ( BUF_net_74 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -22433,14 +22411,12 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_73 ( .A ( BUF_net_74 ) , .Y ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_74 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .Y ( BUF_net_74 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_72 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -22474,10 +22450,10 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_71 ( .A ( BUF_net_72 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_6 BINV_R_163 ( .A ( BUF_net_164 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_72 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .Y ( BUF_net_72 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_164 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_164 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -22511,10 +22487,10 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_69 ( .A ( BUF_net_70 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_68 ( .A ( BUF_net_69 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_70 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .Y ( BUF_net_70 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_69 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_69 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -22548,10 +22524,10 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_67 ( .A ( BUF_net_68 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_6 BINV_R_66 ( .A ( BUF_net_67 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_68 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .Y ( BUF_net_68 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_67 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_67 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -22572,6 +22548,9 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -22581,14 +22560,10 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_65 ( .A ( BUF_net_66 ) , .Y ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_66 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .Y ( BUF_net_66 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -22622,7 +22597,7 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_64 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_65 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -22657,8 +22632,10 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_63 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_63 ( .A ( BUF_net_64 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_64 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_64 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -22728,10 +22705,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_62 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .Y ( BUF_net_62 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_144 ( .A ( BUF_net_62 ) , .Y ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_62 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -22765,8 +22740,10 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_60 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_61 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_61 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_161 ( .A ( BUF_net_61 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -22847,7 +22824,6 @@ input prog_clk_0_N_in ; input VDD ; input VSS ; -wire ropt_net_174 ; wire [0:0] prog_clk ; wire prog_clk_0 ; wire [0:1] mux_tree_tapbuf_size2_0_sram ; @@ -22967,7 +22943,7 @@ sb_2__0__mux_tree_tapbuf_size4_0 mux_top_track_0 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 } ) , .out ( chany_top_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_152 ) ) ; + .p0 ( optlc_net_166 ) ) ; sb_2__0__mux_tree_tapbuf_size4_1 mux_top_track_2 ( .in ( { top_left_grid_pin_45_[0] , top_left_grid_pin_48_[0] , top_left_grid_pin_51_[0] , chanx_left_in[29] } ) , @@ -22975,7 +22951,7 @@ sb_2__0__mux_tree_tapbuf_size4_1 mux_top_track_2 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 } ) , .out ( chany_top_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_151 ) ) ; + .p0 ( optlc_net_169 ) ) ; sb_2__0__mux_tree_tapbuf_size4_2 mux_top_track_4 ( .in ( { top_left_grid_pin_46_[0] , top_left_grid_pin_49_[0] , top_right_grid_pin_1_[0] , chanx_left_in[28] } ) , @@ -22983,7 +22959,7 @@ sb_2__0__mux_tree_tapbuf_size4_2 mux_top_track_4 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 , SYNOPSYS_UNCONNECTED_9 } ) , .out ( chany_top_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_152 ) ) ; + .p0 ( optlc_net_166 ) ) ; sb_2__0__mux_tree_tapbuf_size4_3 mux_top_track_6 ( .in ( { top_left_grid_pin_44_[0] , top_left_grid_pin_47_[0] , top_left_grid_pin_50_[0] , chanx_left_in[27] } ) , @@ -22991,7 +22967,7 @@ sb_2__0__mux_tree_tapbuf_size4_3 mux_top_track_6 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , .out ( chany_top_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_152 ) ) ; + .p0 ( optlc_net_166 ) ) ; sb_2__0__mux_tree_tapbuf_size4_4 mux_top_track_8 ( .in ( { top_left_grid_pin_45_[0] , top_left_grid_pin_48_[0] , top_left_grid_pin_51_[0] , chanx_left_in[26] } ) , @@ -22999,7 +22975,7 @@ sb_2__0__mux_tree_tapbuf_size4_4 mux_top_track_8 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , SYNOPSYS_UNCONNECTED_15 } ) , .out ( chany_top_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_151 ) ) ; + .p0 ( optlc_net_169 ) ) ; sb_2__0__mux_tree_tapbuf_size4_5 mux_top_track_10 ( .in ( { top_left_grid_pin_46_[0] , top_left_grid_pin_49_[0] , top_right_grid_pin_1_[0] , chanx_left_in[25] } ) , @@ -23007,7 +22983,7 @@ sb_2__0__mux_tree_tapbuf_size4_5 mux_top_track_10 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_16 , SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 } ) , .out ( chany_top_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_151 ) ) ; + .p0 ( optlc_net_169 ) ) ; sb_2__0__mux_tree_tapbuf_size4_6 mux_left_track_1 ( .in ( { chany_top_in[0] , left_bottom_grid_pin_1_[0] , left_bottom_grid_pin_7_[0] , left_bottom_grid_pin_13_[0] } ) , @@ -23015,7 +22991,7 @@ sb_2__0__mux_tree_tapbuf_size4_6 mux_left_track_1 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 , SYNOPSYS_UNCONNECTED_21 } ) , .out ( chanx_left_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_153 ) ) ; + .p0 ( optlc_net_165 ) ) ; sb_2__0__mux_tree_tapbuf_size4_7 mux_left_track_3 ( .in ( { chany_top_in[29] , left_bottom_grid_pin_3_[0] , left_bottom_grid_pin_9_[0] , left_bottom_grid_pin_15_[0] } ) , @@ -23023,7 +22999,7 @@ sb_2__0__mux_tree_tapbuf_size4_7 mux_left_track_3 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_22 , SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) , .out ( chanx_left_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_153 ) ) ; + .p0 ( optlc_net_165 ) ) ; sb_2__0__mux_tree_tapbuf_size4_8 mux_left_track_5 ( .in ( { chany_top_in[28] , left_bottom_grid_pin_5_[0] , left_bottom_grid_pin_11_[0] , left_bottom_grid_pin_17_[0] } ) , @@ -23031,7 +23007,7 @@ sb_2__0__mux_tree_tapbuf_size4_8 mux_left_track_5 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , SYNOPSYS_UNCONNECTED_27 } ) , .out ( chanx_left_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_153 ) ) ; + .p0 ( optlc_net_167 ) ) ; sb_2__0__mux_tree_tapbuf_size4_9 mux_left_track_7 ( .in ( { chany_top_in[27] , left_bottom_grid_pin_1_[0] , left_bottom_grid_pin_7_[0] , left_bottom_grid_pin_13_[0] } ) , @@ -23039,7 +23015,7 @@ sb_2__0__mux_tree_tapbuf_size4_9 mux_left_track_7 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_28 , SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 } ) , .out ( chanx_left_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_153 ) ) ; + .p0 ( optlc_net_165 ) ) ; sb_2__0__mux_tree_tapbuf_size4_10 mux_left_track_9 ( .in ( { chany_top_in[26] , left_bottom_grid_pin_3_[0] , left_bottom_grid_pin_9_[0] , left_bottom_grid_pin_15_[0] } ) , @@ -23047,7 +23023,7 @@ sb_2__0__mux_tree_tapbuf_size4_10 mux_left_track_9 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 , SYNOPSYS_UNCONNECTED_33 } ) , .out ( chanx_left_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_150 ) ) ; + .p0 ( optlc_net_168 ) ) ; sb_2__0__mux_tree_tapbuf_size4 mux_left_track_11 ( .in ( { chany_top_in[25] , left_bottom_grid_pin_5_[0] , left_bottom_grid_pin_11_[0] , left_bottom_grid_pin_17_[0] } ) , @@ -23055,7 +23031,7 @@ sb_2__0__mux_tree_tapbuf_size4 mux_left_track_11 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_34 , SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) , .out ( chanx_left_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_150 ) ) ; + .p0 ( optlc_net_168 ) ) ; sb_2__0__mux_tree_tapbuf_size4_mem_0 mem_top_track_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , @@ -23121,35 +23097,35 @@ sb_2__0__mux_tree_tapbuf_size3_0 mux_top_track_12 ( .sram ( mux_tree_tapbuf_size3_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 } ) , .out ( chany_top_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_151 ) ) ; + .p0 ( optlc_net_168 ) ) ; sb_2__0__mux_tree_tapbuf_size3_1 mux_top_track_44 ( .in ( { top_left_grid_pin_48_[0] , top_right_grid_pin_1_[0] , chanx_left_in[8] } ) , .sram ( mux_tree_tapbuf_size3_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) , .out ( chany_top_out[22] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_151 ) ) ; + .p0 ( optlc_net_169 ) ) ; sb_2__0__mux_tree_tapbuf_size3_2 mux_left_track_13 ( .in ( { chany_top_in[24] , left_bottom_grid_pin_1_[0] , left_bottom_grid_pin_17_[0] } ) , .sram ( mux_tree_tapbuf_size3_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 } ) , .out ( chanx_left_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_150 ) ) ; + .p0 ( optlc_net_168 ) ) ; sb_2__0__mux_tree_tapbuf_size3_3 mux_left_track_29 ( .in ( { chany_top_in[16] , left_bottom_grid_pin_1_[0] , left_bottom_grid_pin_17_[0] } ) , .sram ( mux_tree_tapbuf_size3_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) , .out ( chanx_left_out[14] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_153 ) ) ; + .p0 ( optlc_net_167 ) ) ; sb_2__0__mux_tree_tapbuf_size3 mux_left_track_45 ( .in ( { chany_top_in[8] , left_bottom_grid_pin_1_[0] , left_bottom_grid_pin_17_[0] } ) , .sram ( mux_tree_tapbuf_size3_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 } ) , .out ( chanx_left_out[22] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_153 ) ) ; + .p0 ( optlc_net_167 ) ) ; sb_2__0__mux_tree_tapbuf_size3_mem_0 mem_top_track_12 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) , @@ -23180,217 +23156,217 @@ sb_2__0__mux_tree_tapbuf_size2_0 mux_top_track_14 ( .sram ( mux_tree_tapbuf_size2_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) , .out ( chany_top_out[7] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_151 ) ) ; + .p0 ( optlc_net_169 ) ) ; sb_2__0__mux_tree_tapbuf_size2_1 mux_top_track_16 ( .in ( { top_left_grid_pin_46_[0] , chanx_left_in[22] } ) , .sram ( mux_tree_tapbuf_size2_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 } ) , .out ( chany_top_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_151 ) ) ; + .p0 ( optlc_net_169 ) ) ; sb_2__0__mux_tree_tapbuf_size2_2 mux_top_track_18 ( .in ( { top_left_grid_pin_47_[0] , chanx_left_in[21] } ) , .sram ( mux_tree_tapbuf_size2_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) , .out ( chany_top_out[9] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_151 ) ) ; + .p0 ( optlc_net_169 ) ) ; sb_2__0__mux_tree_tapbuf_size2_3 mux_top_track_20 ( .in ( { top_left_grid_pin_48_[0] , chanx_left_in[20] } ) , .sram ( mux_tree_tapbuf_size2_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 } ) , .out ( chany_top_out[10] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_151 ) ) ; + .p0 ( optlc_net_169 ) ) ; sb_2__0__mux_tree_tapbuf_size2_4 mux_top_track_22 ( .in ( { top_left_grid_pin_49_[0] , chanx_left_in[19] } ) , .sram ( mux_tree_tapbuf_size2_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) , .out ( chany_top_out[11] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_152 ) ) ; + .p0 ( optlc_net_166 ) ) ; sb_2__0__mux_tree_tapbuf_size2_5 mux_top_track_24 ( .in ( { top_left_grid_pin_50_[0] , chanx_left_in[18] } ) , .sram ( mux_tree_tapbuf_size2_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 } ) , .out ( chany_top_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_152 ) ) ; + .p0 ( optlc_net_166 ) ) ; sb_2__0__mux_tree_tapbuf_size2_6 mux_top_track_26 ( .in ( { top_left_grid_pin_51_[0] , chanx_left_in[17] } ) , .sram ( mux_tree_tapbuf_size2_6_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) , .out ( chany_top_out[13] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_152 ) ) ; + .p0 ( optlc_net_166 ) ) ; sb_2__0__mux_tree_tapbuf_size2_7 mux_top_track_28 ( .in ( { top_right_grid_pin_1_[0] , chanx_left_in[16] } ) , .sram ( mux_tree_tapbuf_size2_7_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 } ) , .out ( chany_top_out[14] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_152 ) ) ; + .p0 ( optlc_net_166 ) ) ; sb_2__0__mux_tree_tapbuf_size2_8 mux_top_track_36 ( .in ( { top_left_grid_pin_44_[0] , chanx_left_in[12] } ) , .sram ( mux_tree_tapbuf_size2_8_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) , .out ( chany_top_out[18] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_152 ) ) ; + .p0 ( optlc_net_166 ) ) ; sb_2__0__mux_tree_tapbuf_size2_9 mux_top_track_38 ( .in ( { top_left_grid_pin_45_[0] , chanx_left_in[11] } ) , .sram ( mux_tree_tapbuf_size2_9_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 } ) , .out ( chany_top_out[19] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_151 ) ) ; + .p0 ( optlc_net_169 ) ) ; sb_2__0__mux_tree_tapbuf_size2_10 mux_top_track_40 ( .in ( { top_left_grid_pin_46_[0] , chanx_left_in[10] } ) , .sram ( mux_tree_tapbuf_size2_10_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 } ) , .out ( chany_top_out[20] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_151 ) ) ; + .p0 ( optlc_net_166 ) ) ; sb_2__0__mux_tree_tapbuf_size2_11 mux_top_track_42 ( .in ( { top_left_grid_pin_47_[0] , chanx_left_in[9] } ) , .sram ( mux_tree_tapbuf_size2_11_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_69 , SYNOPSYS_UNCONNECTED_70 } ) , .out ( chany_top_out[21] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_151 ) ) ; + .p0 ( optlc_net_166 ) ) ; sb_2__0__mux_tree_tapbuf_size2_12 mux_top_track_46 ( .in ( { top_left_grid_pin_49_[0] , chanx_left_in[7] } ) , .sram ( mux_tree_tapbuf_size2_12_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_71 , SYNOPSYS_UNCONNECTED_72 } ) , .out ( chany_top_out[23] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_152 ) ) ; + .p0 ( optlc_net_166 ) ) ; sb_2__0__mux_tree_tapbuf_size2_13 mux_top_track_48 ( .in ( { top_left_grid_pin_50_[0] , chanx_left_in[6] } ) , .sram ( mux_tree_tapbuf_size2_13_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_73 , SYNOPSYS_UNCONNECTED_74 } ) , .out ( chany_top_out[24] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_152 ) ) ; + .p0 ( optlc_net_166 ) ) ; sb_2__0__mux_tree_tapbuf_size2_14 mux_top_track_50 ( .in ( { top_left_grid_pin_51_[0] , chanx_left_in[5] } ) , .sram ( mux_tree_tapbuf_size2_14_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_75 , SYNOPSYS_UNCONNECTED_76 } ) , .out ( chany_top_out[25] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_152 ) ) ; + .p0 ( optlc_net_166 ) ) ; sb_2__0__mux_tree_tapbuf_size2_15 mux_left_track_15 ( .in ( { chany_top_in[23] , left_bottom_grid_pin_3_[0] } ) , .sram ( mux_tree_tapbuf_size2_15_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_77 , SYNOPSYS_UNCONNECTED_78 } ) , .out ( chanx_left_out[7] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_150 ) ) ; + .p0 ( optlc_net_168 ) ) ; sb_2__0__mux_tree_tapbuf_size2_16 mux_left_track_17 ( .in ( { chany_top_in[22] , left_bottom_grid_pin_5_[0] } ) , .sram ( mux_tree_tapbuf_size2_16_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_79 , SYNOPSYS_UNCONNECTED_80 } ) , .out ( chanx_left_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_150 ) ) ; + .p0 ( optlc_net_169 ) ) ; sb_2__0__mux_tree_tapbuf_size2_17 mux_left_track_19 ( .in ( { chany_top_in[21] , left_bottom_grid_pin_7_[0] } ) , .sram ( mux_tree_tapbuf_size2_17_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_81 , SYNOPSYS_UNCONNECTED_82 } ) , .out ( chanx_left_out[9] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_151 ) ) ; + .p0 ( optlc_net_169 ) ) ; sb_2__0__mux_tree_tapbuf_size2_18 mux_left_track_21 ( .in ( { chany_top_in[20] , left_bottom_grid_pin_9_[0] } ) , .sram ( mux_tree_tapbuf_size2_18_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_83 , SYNOPSYS_UNCONNECTED_84 } ) , .out ( chanx_left_out[10] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_151 ) ) ; + .p0 ( optlc_net_169 ) ) ; sb_2__0__mux_tree_tapbuf_size2_19 mux_left_track_23 ( .in ( { chany_top_in[19] , left_bottom_grid_pin_11_[0] } ) , .sram ( mux_tree_tapbuf_size2_19_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_85 , SYNOPSYS_UNCONNECTED_86 } ) , .out ( chanx_left_out[11] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_153 ) ) ; + .p0 ( optlc_net_167 ) ) ; sb_2__0__mux_tree_tapbuf_size2_20 mux_left_track_25 ( .in ( { chany_top_in[18] , left_bottom_grid_pin_13_[0] } ) , .sram ( mux_tree_tapbuf_size2_20_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_87 , SYNOPSYS_UNCONNECTED_88 } ) , .out ( chanx_left_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_152 ) ) ; + .p0 ( optlc_net_167 ) ) ; sb_2__0__mux_tree_tapbuf_size2_21 mux_left_track_27 ( .in ( { chany_top_in[17] , left_bottom_grid_pin_15_[0] } ) , .sram ( mux_tree_tapbuf_size2_21_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_89 , SYNOPSYS_UNCONNECTED_90 } ) , .out ( chanx_left_out[13] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_153 ) ) ; + .p0 ( optlc_net_167 ) ) ; sb_2__0__mux_tree_tapbuf_size2_22 mux_left_track_31 ( .in ( { chany_top_in[15] , left_bottom_grid_pin_3_[0] } ) , .sram ( mux_tree_tapbuf_size2_22_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_91 , SYNOPSYS_UNCONNECTED_92 } ) , .out ( chanx_left_out[15] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_152 ) ) ; + .p0 ( optlc_net_166 ) ) ; sb_2__0__mux_tree_tapbuf_size2_23 mux_left_track_33 ( .in ( { chany_top_in[14] , left_bottom_grid_pin_5_[0] } ) , .sram ( mux_tree_tapbuf_size2_23_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_93 , SYNOPSYS_UNCONNECTED_94 } ) , .out ( chanx_left_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_152 ) ) ; + .p0 ( optlc_net_166 ) ) ; sb_2__0__mux_tree_tapbuf_size2_24 mux_left_track_35 ( .in ( { chany_top_in[13] , left_bottom_grid_pin_7_[0] } ) , .sram ( mux_tree_tapbuf_size2_24_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_95 , SYNOPSYS_UNCONNECTED_96 } ) , .out ( chanx_left_out[17] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_151 ) ) ; + .p0 ( optlc_net_169 ) ) ; sb_2__0__mux_tree_tapbuf_size2_25 mux_left_track_37 ( .in ( { chany_top_in[12] , left_bottom_grid_pin_9_[0] } ) , .sram ( mux_tree_tapbuf_size2_25_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_97 , SYNOPSYS_UNCONNECTED_98 } ) , .out ( chanx_left_out[18] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_150 ) ) ; + .p0 ( optlc_net_167 ) ) ; sb_2__0__mux_tree_tapbuf_size2_26 mux_left_track_39 ( .in ( { chany_top_in[11] , left_bottom_grid_pin_11_[0] } ) , .sram ( mux_tree_tapbuf_size2_26_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_99 , SYNOPSYS_UNCONNECTED_100 } ) , .out ( chanx_left_out[19] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_153 ) ) ; + .p0 ( optlc_net_167 ) ) ; sb_2__0__mux_tree_tapbuf_size2_27 mux_left_track_41 ( .in ( { chany_top_in[10] , left_bottom_grid_pin_13_[0] } ) , .sram ( mux_tree_tapbuf_size2_27_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_101 , SYNOPSYS_UNCONNECTED_102 } ) , .out ( chanx_left_out[20] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_150 ) ) ; + .p0 ( optlc_net_165 ) ) ; sb_2__0__mux_tree_tapbuf_size2_28 mux_left_track_43 ( .in ( { chany_top_in[9] , left_bottom_grid_pin_15_[0] } ) , .sram ( mux_tree_tapbuf_size2_28_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_103 , SYNOPSYS_UNCONNECTED_104 } ) , .out ( chanx_left_out[21] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_153 ) ) ; + .p0 ( optlc_net_165 ) ) ; sb_2__0__mux_tree_tapbuf_size2_29 mux_left_track_47 ( .in ( { chany_top_in[7] , left_bottom_grid_pin_3_[0] } ) , .sram ( mux_tree_tapbuf_size2_29_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_105 , SYNOPSYS_UNCONNECTED_106 } ) , .out ( chanx_left_out[23] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_152 ) ) ; + .p0 ( optlc_net_167 ) ) ; sb_2__0__mux_tree_tapbuf_size2_30 mux_left_track_49 ( .in ( { chany_top_in[6] , left_bottom_grid_pin_5_[0] } ) , .sram ( mux_tree_tapbuf_size2_30_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_107 , SYNOPSYS_UNCONNECTED_108 } ) , .out ( chanx_left_out[24] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_153 ) ) ; + .p0 ( optlc_net_167 ) ) ; sb_2__0__mux_tree_tapbuf_size2_31 mux_left_track_51 ( .in ( { chany_top_in[5] , left_bottom_grid_pin_7_[0] } ) , .sram ( mux_tree_tapbuf_size2_31_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_109 , SYNOPSYS_UNCONNECTED_110 } ) , .out ( chanx_left_out[25] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_153 ) ) ; + .p0 ( optlc_net_165 ) ) ; sb_2__0__mux_tree_tapbuf_size2_32 mux_left_track_53 ( .in ( { chany_top_in[4] , left_bottom_grid_pin_9_[0] } ) , .sram ( mux_tree_tapbuf_size2_32_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_111 , SYNOPSYS_UNCONNECTED_112 } ) , .out ( chanx_left_out[26] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_150 ) ) ; + .p0 ( optlc_net_168 ) ) ; sb_2__0__mux_tree_tapbuf_size2_33 mux_left_track_55 ( .in ( { chany_top_in[3] , left_bottom_grid_pin_11_[0] } ) , .sram ( mux_tree_tapbuf_size2_33_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_113 , SYNOPSYS_UNCONNECTED_114 } ) , .out ( chanx_left_out[27] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_150 ) ) ; + .p0 ( optlc_net_168 ) ) ; sb_2__0__mux_tree_tapbuf_size2_34 mux_left_track_57 ( .in ( { chany_top_in[2] , left_bottom_grid_pin_13_[0] } ) , .sram ( mux_tree_tapbuf_size2_34_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_115 , SYNOPSYS_UNCONNECTED_116 } ) , .out ( chanx_left_out[28] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_150 ) ) ; + .p0 ( optlc_net_168 ) ) ; sb_2__0__mux_tree_tapbuf_size2 mux_left_track_59 ( .in ( { chany_top_in[1] , left_bottom_grid_pin_15_[0] } ) , .sram ( mux_tree_tapbuf_size2_35_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_117 , SYNOPSYS_UNCONNECTED_118 } ) , .out ( chanx_left_out[29] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_150 ) ) ; + .p0 ( optlc_net_168 ) ) ; sb_2__0__mux_tree_tapbuf_size2_mem_0 mem_top_track_14 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , @@ -23573,12 +23549,12 @@ sb_2__0__mux_tree_tapbuf_size2_mem mem_left_track_59 ( .pReset ( pReset ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_W_in ) , .X ( pReset[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_152 ( .LO ( SYNOPSYS_UNCONNECTED_119 ) , - .HI ( optlc_net_150 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_167 ( .LO ( SYNOPSYS_UNCONNECTED_119 ) , + .HI ( optlc_net_165 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_N_in ) , .X ( prog_clk[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 FTB_54__53 ( .A ( chanx_left_in[1] ) , - .X ( ropt_net_174 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chanx_left_in[1] ) , + .X ( chany_top_out[29] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chanx_left_in[2] ) , .X ( chany_top_out[28] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chanx_left_in[3] ) , @@ -23591,18 +23567,18 @@ sky130_fd_sc_hd__buf_6 FTB_59__58 ( .A ( chanx_left_in[14] ) , .X ( chany_top_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( chanx_left_in[15] ) , .X ( chany_top_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_120 ( .A ( BUF_net_121 ) , .Y ( pReset_N_out ) , +sky130_fd_sc_hd__inv_8 BINV_R_125 ( .A ( BUF_net_126 ) , .Y ( pReset_N_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_121 ( .A ( pReset_W_in ) , .Y ( BUF_net_121 ) , +sky130_fd_sc_hd__inv_1 BINV_R_126 ( .A ( pReset_W_in ) , .Y ( BUF_net_126 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_154 ( .LO ( SYNOPSYS_UNCONNECTED_120 ) , - .HI ( optlc_net_151 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_156 ( .LO ( SYNOPSYS_UNCONNECTED_121 ) , - .HI ( optlc_net_152 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_158 ( .LO ( SYNOPSYS_UNCONNECTED_122 ) , - .HI ( optlc_net_153 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1337 ( .A ( ropt_net_174 ) , - .X ( chany_top_out[29] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_170 ( .LO ( SYNOPSYS_UNCONNECTED_120 ) , + .HI ( optlc_net_166 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_172 ( .LO ( SYNOPSYS_UNCONNECTED_121 ) , + .HI ( optlc_net_167 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_174 ( .LO ( SYNOPSYS_UNCONNECTED_122 ) , + .HI ( optlc_net_168 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_176 ( .LO ( SYNOPSYS_UNCONNECTED_123 ) , + .HI ( optlc_net_169 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -23891,7 +23867,7 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_138 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_136 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -24025,7 +24001,7 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_137 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_135 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -24048,11 +24024,13 @@ supply0 VSS ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_136 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_133 ( .A ( BUF_net_134 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_134 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_134 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -24077,10 +24055,10 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_134 ( .A ( BUF_net_135 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_131 ( .A ( BUF_net_132 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_135 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_135 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_132 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_132 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -24105,7 +24083,7 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_133 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_130 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -24125,15 +24103,16 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_128 ( .A ( BUF_net_129 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_129 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_129 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -24158,7 +24137,7 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_132 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_127 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -24281,14 +24260,12 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_130 ( .A ( BUF_net_131 ) , .Y ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_131 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .Y ( BUF_net_131 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_126 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -24346,14 +24323,12 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_128 ( .A ( BUF_net_129 ) , .Y ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_129 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .Y ( BUF_net_129 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_125 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -24383,10 +24358,10 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_126 ( .A ( BUF_net_127 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_123 ( .A ( BUF_net_124 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_127 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .Y ( BUF_net_127 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_124 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .Y ( BUF_net_124 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -24537,10 +24512,10 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_124 ( .A ( BUF_net_125 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_121 ( .A ( BUF_net_122 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_125 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .Y ( BUF_net_125 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_122 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .Y ( BUF_net_122 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -24583,10 +24558,10 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_122 ( .A ( BUF_net_123 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_119 ( .A ( BUF_net_120 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_123 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .Y ( BUF_net_123 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_120 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .Y ( BUF_net_120 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -24629,10 +24604,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_120 ( .A ( BUF_net_121 ) , .Y ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_121 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .Y ( BUF_net_121 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_118 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -24675,10 +24648,10 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_118 ( .A ( BUF_net_119 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_116 ( .A ( BUF_net_117 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_119 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .Y ( BUF_net_119 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_117 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .Y ( BUF_net_117 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -24704,8 +24677,20 @@ sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 FTB_29__28 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_29__28 ( .A ( copt_net_158 ) , + .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1350 ( .A ( mem_out[2] ) , + .X ( copt_net_153 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1351 ( .A ( copt_net_153 ) , + .X ( copt_net_154 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1352 ( .A ( copt_net_154 ) , + .X ( copt_net_155 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1353 ( .A ( copt_net_155 ) , + .X ( copt_net_156 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1354 ( .A ( copt_net_156 ) , + .X ( copt_net_157 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1355 ( .A ( copt_net_157 ) , + .X ( copt_net_158 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -24915,6 +24900,9 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -24924,14 +24912,10 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_116 ( .A ( BUF_net_117 ) , .Y ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_117 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .Y ( BUF_net_117 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -24997,12 +24981,14 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_115 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_114 ( .A ( BUF_net_115 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_115 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_115 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -25036,10 +25022,10 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_113 ( .A ( BUF_net_114 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_112 ( .A ( BUF_net_113 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_114 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .Y ( BUF_net_114 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_113 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_113 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -25073,10 +25059,10 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_111 ( .A ( BUF_net_112 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_144 ( .A ( BUF_net_145 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_112 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .Y ( BUF_net_112 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_145 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_145 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -25110,10 +25096,10 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_109 ( .A ( BUF_net_110 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_110 ( .A ( BUF_net_111 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_110 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .Y ( BUF_net_110 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_111 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_111 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -25143,14 +25129,12 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_107 ( .A ( BUF_net_108 ) , .Y ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_108 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .Y ( BUF_net_108 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_109 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -25343,6 +25327,9 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -25356,14 +25343,10 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_105 ( .A ( BUF_net_106 ) , .Y ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_106 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .Y ( BUF_net_106 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -25402,10 +25385,10 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_103 ( .A ( BUF_net_104 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_107 ( .A ( BUF_net_108 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_104 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .Y ( BUF_net_104 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_108 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .Y ( BUF_net_108 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -25440,14 +25423,12 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_101 ( .A ( BUF_net_102 ) , .Y ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_102 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .Y ( BUF_net_102 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_106 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -25486,10 +25467,10 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_99 ( .A ( BUF_net_100 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_142 ( .A ( BUF_net_143 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_100 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .Y ( BUF_net_100 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_143 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .Y ( BUF_net_143 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -25647,10 +25628,10 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_97 ( .A ( BUF_net_98 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_104 ( .A ( BUF_net_105 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_98 ( .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .Y ( BUF_net_98 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_105 ( .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .Y ( BUF_net_105 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -25796,72 +25777,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -25896,6 +25811,72 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_140 ( .A ( BUF_net_141 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_141 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .Y ( BUF_net_141 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_103 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -26010,9 +25991,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -26040,6 +26018,8 @@ sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_102 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -26380,7 +26360,7 @@ input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_185 ) , +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_187 ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , @@ -26391,30 +26371,18 @@ sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1329 ( .A ( ccff_head[0] ) , - .X ( copt_net_146 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1330 ( .A ( copt_net_146 ) , - .X ( copt_net_147 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1331 ( .A ( copt_net_147 ) , - .X ( copt_net_148 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1332 ( .A ( copt_net_150 ) , - .X ( copt_net_149 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1333 ( .A ( copt_net_148 ) , - .X ( copt_net_150 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1334 ( .A ( copt_net_149 ) , - .X ( copt_net_151 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1360 ( .A ( copt_net_151 ) , - .X ( ropt_net_180 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1361 ( .A ( ropt_net_180 ) , - .X ( ropt_net_181 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1362 ( .A ( ropt_net_181 ) , +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1415 ( .A ( ccff_head[0] ) , .X ( ropt_net_182 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1363 ( .A ( ropt_net_182 ) , +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1416 ( .A ( ropt_net_182 ) , .X ( ropt_net_183 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1364 ( .A ( ropt_net_183 ) , +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1417 ( .A ( ropt_net_185 ) , .X ( ropt_net_184 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1365 ( .A ( ropt_net_184 ) , +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1418 ( .A ( ropt_net_183 ) , .X ( ropt_net_185 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1419 ( .A ( ropt_net_184 ) , + .X ( ropt_net_186 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1420 ( .A ( ropt_net_186 ) , + .X ( ropt_net_187 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -26462,10 +26430,10 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_95 ( .A ( BUF_net_96 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_100 ( .A ( BUF_net_101 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_96 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .Y ( BUF_net_96 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_101 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .Y ( BUF_net_101 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -26489,9 +26457,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -26512,10 +26477,14 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_98 ( .A ( BUF_net_99 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_99 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .Y ( BUF_net_99 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -26563,10 +26532,10 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_93 ( .A ( BUF_net_94 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_96 ( .A ( BUF_net_97 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_94 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .Y ( BUF_net_94 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_97 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .Y ( BUF_net_97 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -26590,9 +26559,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -26617,6 +26583,8 @@ sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_95 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -26764,10 +26732,10 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_91 ( .A ( BUF_net_92 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_93 ( .A ( BUF_net_94 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_92 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .Y ( BUF_net_92 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_94 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .Y ( BUF_net_94 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -26791,9 +26759,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -26818,6 +26783,10 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_91 ( .A ( BUF_net_92 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_92 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .Y ( BUF_net_92 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -26841,9 +26810,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -26868,6 +26834,10 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_138 ( .A ( BUF_net_139 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_139 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .Y ( BUF_net_139 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -26934,7 +26904,7 @@ input prog_clk_0_S_in ; input VDD ; input VSS ; -wire ropt_net_167 ; +wire ropt_net_166 ; wire [0:0] prog_clk ; wire prog_clk_0 ; wire [0:3] mux_tree_tapbuf_size10_0_sram ; @@ -27047,7 +27017,7 @@ sb_1__2__mux_tree_tapbuf_size7_0 mux_right_track_0 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 } ) , .out ( chanx_right_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_145 ) ) ; + .p0 ( optlc_net_150 ) ) ; sb_1__2__mux_tree_tapbuf_size7_1 mux_right_track_2 ( .in ( { right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_39_[0] , right_bottom_grid_pin_42_[0] , chany_bottom_in[8] , @@ -27056,7 +27026,7 @@ sb_1__2__mux_tree_tapbuf_size7_1 mux_right_track_2 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 } ) , .out ( chanx_right_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_145 ) ) ; + .p0 ( optlc_net_150 ) ) ; sb_1__2__mux_tree_tapbuf_size7_2 mux_right_track_12 ( .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_41_[0] , chany_bottom_in[4] , chany_bottom_in[15] , chany_bottom_in[26] , @@ -27065,7 +27035,7 @@ sb_1__2__mux_tree_tapbuf_size7_2 mux_right_track_12 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 , SYNOPSYS_UNCONNECTED_9 } ) , .out ( chanx_right_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_142 ) ) ; + .p0 ( optlc_net_148 ) ) ; sb_1__2__mux_tree_tapbuf_size7_3 mux_right_track_20 ( .in ( { right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_42_[0] , chany_bottom_in[3] , chany_bottom_in[14] , chany_bottom_in[25] , @@ -27074,7 +27044,7 @@ sb_1__2__mux_tree_tapbuf_size7_3 mux_right_track_20 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , .out ( chanx_right_out[10] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_143 ) ) ; + .p0 ( optlc_net_148 ) ) ; sb_1__2__mux_tree_tapbuf_size7_4 mux_right_track_28 ( .in ( { right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_43_[0] , chany_bottom_in[2] , chany_bottom_in[13] , chany_bottom_in[24] , @@ -27083,7 +27053,7 @@ sb_1__2__mux_tree_tapbuf_size7_4 mux_right_track_28 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , SYNOPSYS_UNCONNECTED_15 } ) , .out ( chanx_right_out[14] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_143 ) ) ; + .p0 ( optlc_net_148 ) ) ; sb_1__2__mux_tree_tapbuf_size7_5 mux_left_track_1 ( .in ( { chanx_left_out[4] , chanx_left_out[20] , chany_bottom_in[10] , chany_bottom_in[21] , left_top_grid_pin_1_[0] , @@ -27092,7 +27062,7 @@ sb_1__2__mux_tree_tapbuf_size7_5 mux_left_track_1 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_16 , SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 } ) , .out ( chanx_left_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_144 ) ) ; + .p0 ( optlc_net_149 ) ) ; sb_1__2__mux_tree_tapbuf_size7_6 mux_left_track_13 ( .in ( { chanx_left_out[12] , chanx_left_out[27] , chany_bottom_in[4] , chany_bottom_in[15] , chany_bottom_in[26] , left_top_grid_pin_1_[0] , @@ -27101,7 +27071,7 @@ sb_1__2__mux_tree_tapbuf_size7_6 mux_left_track_13 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 , SYNOPSYS_UNCONNECTED_21 } ) , .out ( chanx_left_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_144 ) ) ; + .p0 ( optlc_net_149 ) ) ; sb_1__2__mux_tree_tapbuf_size7_7 mux_left_track_21 ( .in ( { chanx_left_out[13] , chanx_left_out[28] , chany_bottom_in[5] , chany_bottom_in[16] , chany_bottom_in[27] , @@ -27110,7 +27080,7 @@ sb_1__2__mux_tree_tapbuf_size7_7 mux_left_track_21 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_22 , SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) , .out ( chanx_left_out[10] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_140 ) ) ; + .p0 ( optlc_net_151 ) ) ; sb_1__2__mux_tree_tapbuf_size7 mux_left_track_29 ( .in ( { chanx_left_out[15] , chanx_left_out[29] , chany_bottom_in[6] , chany_bottom_in[17] , chany_bottom_in[28] , @@ -27119,7 +27089,7 @@ sb_1__2__mux_tree_tapbuf_size7 mux_left_track_29 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , SYNOPSYS_UNCONNECTED_27 } ) , .out ( chanx_left_out[14] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_140 ) ) ; + .p0 ( optlc_net_151 ) ) ; sb_1__2__mux_tree_tapbuf_size7_mem_0 mem_right_track_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , @@ -27173,7 +27143,7 @@ sb_1__2__mux_tree_tapbuf_size8_0 mux_right_track_4 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_28 , SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 , SYNOPSYS_UNCONNECTED_31 } ) , .out ( chanx_right_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_143 ) ) ; + .p0 ( optlc_net_151 ) ) ; sb_1__2__mux_tree_tapbuf_size8_1 mux_left_track_3 ( .in ( { chanx_left_out[7] , chanx_left_out[21] , chany_bottom_in[0] , chany_bottom_in[11] , chany_bottom_in[22] , @@ -27183,7 +27153,7 @@ sb_1__2__mux_tree_tapbuf_size8_1 mux_left_track_3 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_32 , SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 , SYNOPSYS_UNCONNECTED_35 } ) , .out ( chanx_left_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_144 ) ) ; + .p0 ( optlc_net_146 ) ) ; sb_1__2__mux_tree_tapbuf_size8 mux_left_track_5 ( .in ( { chanx_left_out[8] , chanx_left_out[23] , chany_bottom_in[1] , chany_bottom_in[12] , chany_bottom_in[23] , @@ -27193,7 +27163,7 @@ sb_1__2__mux_tree_tapbuf_size8 mux_left_track_5 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_36 , SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 , SYNOPSYS_UNCONNECTED_39 } ) , .out ( chanx_left_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_140 ) ) ; + .p0 ( optlc_net_146 ) ) ; sb_1__2__mux_tree_tapbuf_size8_mem_0 mem_right_track_4 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , @@ -27219,7 +27189,7 @@ sb_1__2__mux_tree_tapbuf_size10_0 mux_right_track_6 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_40 , SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 , SYNOPSYS_UNCONNECTED_43 } ) , .out ( chanx_right_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_143 ) ) ; + .p0 ( optlc_net_148 ) ) ; sb_1__2__mux_tree_tapbuf_size10 mux_left_track_7 ( .in ( { chanx_left_out[9] , chanx_left_out[24] , chany_bottom_in[2] , chany_bottom_in[13] , chany_bottom_in[24] , left_top_grid_pin_1_[0] , @@ -27229,7 +27199,7 @@ sb_1__2__mux_tree_tapbuf_size10 mux_left_track_7 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_44 , SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 , SYNOPSYS_UNCONNECTED_47 } ) , .out ( chanx_left_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_140 ) ) ; + .p0 ( optlc_net_146 ) ) ; sb_1__2__mux_tree_tapbuf_size10_mem_0 mem_right_track_6 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , @@ -27249,7 +27219,7 @@ sb_1__2__mux_tree_tapbuf_size9_0 mux_right_track_10 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_48 , SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 , SYNOPSYS_UNCONNECTED_51 } ) , .out ( chanx_right_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_143 ) ) ; + .p0 ( optlc_net_148 ) ) ; sb_1__2__mux_tree_tapbuf_size9 mux_left_track_11 ( .in ( { chanx_left_out[11] , chanx_left_out[25] , chany_bottom_in[3] , chany_bottom_in[14] , chany_bottom_in[25] , @@ -27259,7 +27229,7 @@ sb_1__2__mux_tree_tapbuf_size9 mux_left_track_11 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_52 , SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 , SYNOPSYS_UNCONNECTED_55 } ) , .out ( chanx_left_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_144 ) ) ; + .p0 ( optlc_net_149 ) ) ; sb_1__2__mux_tree_tapbuf_size9_mem_0 mem_right_track_10 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , @@ -27277,15 +27247,15 @@ sb_1__2__mux_tree_tapbuf_size5_0 mux_right_track_36 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_56 , SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 } ) , .out ( chanx_right_out[18] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_142 ) ) ; + .p0 ( optlc_net_148 ) ) ; sb_1__2__mux_tree_tapbuf_size5_1 mux_right_track_44 ( .in ( { right_bottom_grid_pin_39_[0] , chany_bottom_in[0] , - chany_bottom_in[11] , chany_bottom_in[22] , chanx_right_out[17] } ) , + chany_bottom_in[11] , chany_bottom_in[22] , ropt_net_166 } ) , .sram ( mux_tree_tapbuf_size5_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 , SYNOPSYS_UNCONNECTED_61 } ) , .out ( chanx_right_out[22] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_142 ) ) ; + .p0 ( optlc_net_147 ) ) ; sb_1__2__mux_tree_tapbuf_size5_2 mux_bottom_track_5 ( .in ( { chanx_left_out[8] , bottom_left_grid_pin_46_[0] , bottom_left_grid_pin_49_[0] , chanx_left_in[4] , chanx_right_out[8] } ) , @@ -27293,7 +27263,7 @@ sb_1__2__mux_tree_tapbuf_size5_2 mux_bottom_track_5 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_62 , SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) , .out ( chany_bottom_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_140 ) ) ; + .p0 ( optlc_net_146 ) ) ; sb_1__2__mux_tree_tapbuf_size5_3 mux_bottom_track_11 ( .in ( { chanx_left_out[12] , bottom_left_grid_pin_46_[0] , bottom_left_grid_pin_49_[0] , chanx_right_out[12] , @@ -27302,7 +27272,7 @@ sb_1__2__mux_tree_tapbuf_size5_3 mux_bottom_track_11 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 , SYNOPSYS_UNCONNECTED_67 } ) , .out ( chany_bottom_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_141 ) ) ; + .p0 ( optlc_net_146 ) ) ; sb_1__2__mux_tree_tapbuf_size5 mux_left_track_37 ( .in ( { chanx_left_out[16] , chany_bottom_in[7] , chany_bottom_in[18] , chany_bottom_in[29] , left_bottom_grid_pin_38_[0] } ) , @@ -27310,7 +27280,7 @@ sb_1__2__mux_tree_tapbuf_size5 mux_left_track_37 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_68 , SYNOPSYS_UNCONNECTED_69 , SYNOPSYS_UNCONNECTED_70 } ) , .out ( chanx_left_out[18] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_140 ) ) ; + .p0 ( optlc_net_151 ) ) ; sb_1__2__mux_tree_tapbuf_size5_mem_0 mem_right_track_36 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , @@ -27343,7 +27313,7 @@ sb_1__2__mux_tree_tapbuf_size4_0 mux_right_track_52 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_71 , SYNOPSYS_UNCONNECTED_72 , SYNOPSYS_UNCONNECTED_73 } ) , .out ( chanx_right_out[26] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_142 ) ) ; + .p0 ( optlc_net_147 ) ) ; sb_1__2__mux_tree_tapbuf_size4_1 mux_bottom_track_13 ( .in ( { chanx_left_out[13] , bottom_left_grid_pin_44_[0] , chanx_right_out[13] , chanx_left_in[17] } ) , @@ -27351,7 +27321,7 @@ sb_1__2__mux_tree_tapbuf_size4_1 mux_bottom_track_13 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_74 , SYNOPSYS_UNCONNECTED_75 , SYNOPSYS_UNCONNECTED_76 } ) , .out ( chany_bottom_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_140 ) ) ; + .p0 ( optlc_net_146 ) ) ; sb_1__2__mux_tree_tapbuf_size4_2 mux_bottom_track_15 ( .in ( { chanx_left_out[15] , bottom_left_grid_pin_45_[0] , chanx_right_out[15] , chanx_left_in[21] } ) , @@ -27359,7 +27329,7 @@ sb_1__2__mux_tree_tapbuf_size4_2 mux_bottom_track_15 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_77 , SYNOPSYS_UNCONNECTED_78 , SYNOPSYS_UNCONNECTED_79 } ) , .out ( chany_bottom_out[7] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_141 ) ) ; + .p0 ( optlc_net_146 ) ) ; sb_1__2__mux_tree_tapbuf_size4_3 mux_bottom_track_17 ( .in ( { chanx_left_out[16] , bottom_left_grid_pin_46_[0] , chanx_right_out[16] , chanx_left_in[25] } ) , @@ -27367,15 +27337,15 @@ sb_1__2__mux_tree_tapbuf_size4_3 mux_bottom_track_17 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_80 , SYNOPSYS_UNCONNECTED_81 , SYNOPSYS_UNCONNECTED_82 } ) , .out ( chany_bottom_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_141 ) ) ; + .p0 ( optlc_net_146 ) ) ; sb_1__2__mux_tree_tapbuf_size4_4 mux_bottom_track_19 ( - .in ( { chanx_left_out[17] , bottom_left_grid_pin_47_[0] , - chanx_right_out[17] , chanx_left_in[29] } ) , + .in ( { chanx_left_out[17] , bottom_left_grid_pin_47_[0] , ropt_net_166 , + chanx_left_in[29] } ) , .sram ( mux_tree_tapbuf_size4_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_83 , SYNOPSYS_UNCONNECTED_84 , SYNOPSYS_UNCONNECTED_85 } ) , .out ( chany_bottom_out[9] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_141 ) ) ; + .p0 ( optlc_net_149 ) ) ; sb_1__2__mux_tree_tapbuf_size4_5 mux_bottom_track_37 ( .in ( { chanx_left_out[29] , chanx_right_in[29] , bottom_left_grid_pin_44_[0] , chanx_right_out[29] } ) , @@ -27383,7 +27353,7 @@ sb_1__2__mux_tree_tapbuf_size4_5 mux_bottom_track_37 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_86 , SYNOPSYS_UNCONNECTED_87 , SYNOPSYS_UNCONNECTED_88 } ) , .out ( chany_bottom_out[18] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_142 ) ) ; + .p0 ( optlc_net_147 ) ) ; sb_1__2__mux_tree_tapbuf_size4_6 mux_left_track_45 ( .in ( { chanx_left_out[17] , chany_bottom_in[8] , chany_bottom_in[19] , left_bottom_grid_pin_39_[0] } ) , @@ -27391,7 +27361,7 @@ sb_1__2__mux_tree_tapbuf_size4_6 mux_left_track_45 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_89 , SYNOPSYS_UNCONNECTED_90 , SYNOPSYS_UNCONNECTED_91 } ) , .out ( chanx_left_out[22] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_140 ) ) ; + .p0 ( optlc_net_151 ) ) ; sb_1__2__mux_tree_tapbuf_size4 mux_left_track_53 ( .in ( { chanx_left_out[19] , chany_bottom_in[9] , chany_bottom_in[20] , left_bottom_grid_pin_40_[0] } ) , @@ -27399,7 +27369,7 @@ sb_1__2__mux_tree_tapbuf_size4 mux_left_track_53 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_92 , SYNOPSYS_UNCONNECTED_93 , SYNOPSYS_UNCONNECTED_94 } ) , .out ( chanx_left_out[26] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_140 ) ) ; + .p0 ( optlc_net_152 ) ) ; sb_1__2__mux_tree_tapbuf_size4_mem_0 mem_right_track_52 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , @@ -27448,7 +27418,7 @@ sb_1__2__mux_tree_tapbuf_size6_0 mux_bottom_track_1 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_95 , SYNOPSYS_UNCONNECTED_96 , SYNOPSYS_UNCONNECTED_97 } ) , .out ( chany_bottom_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_141 ) ) ; + .p0 ( optlc_net_146 ) ) ; sb_1__2__mux_tree_tapbuf_size6_1 mux_bottom_track_3 ( .in ( { chanx_left_out[7] , bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_48_[0] , bottom_left_grid_pin_51_[0] , @@ -27457,7 +27427,7 @@ sb_1__2__mux_tree_tapbuf_size6_1 mux_bottom_track_3 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_98 , SYNOPSYS_UNCONNECTED_99 , SYNOPSYS_UNCONNECTED_100 } ) , .out ( chany_bottom_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_141 ) ) ; + .p0 ( optlc_net_146 ) ) ; sb_1__2__mux_tree_tapbuf_size6_2 mux_bottom_track_7 ( .in ( { chanx_left_out[9] , bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_47_[0] , bottom_left_grid_pin_50_[0] , @@ -27466,7 +27436,7 @@ sb_1__2__mux_tree_tapbuf_size6_2 mux_bottom_track_7 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_101 , SYNOPSYS_UNCONNECTED_102 , SYNOPSYS_UNCONNECTED_103 } ) , .out ( chany_bottom_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_140 ) ) ; + .p0 ( optlc_net_152 ) ) ; sb_1__2__mux_tree_tapbuf_size6 mux_bottom_track_9 ( .in ( { chanx_left_out[11] , bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_48_[0] , bottom_left_grid_pin_51_[0] , @@ -27475,7 +27445,7 @@ sb_1__2__mux_tree_tapbuf_size6 mux_bottom_track_9 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_104 , SYNOPSYS_UNCONNECTED_105 , SYNOPSYS_UNCONNECTED_106 } ) , .out ( chany_bottom_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_141 ) ) ; + .p0 ( optlc_net_146 ) ) ; sb_1__2__mux_tree_tapbuf_size6_mem_0 mem_bottom_track_1 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , @@ -27502,28 +27472,28 @@ sb_1__2__mux_tree_tapbuf_size3_0 mux_bottom_track_21 ( .sram ( mux_tree_tapbuf_size3_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_107 , SYNOPSYS_UNCONNECTED_108 } ) , .out ( chany_bottom_out[10] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_144 ) ) ; + .p0 ( optlc_net_149 ) ) ; sb_1__2__mux_tree_tapbuf_size3_1 mux_bottom_track_23 ( .in ( { chanx_left_out[20] , bottom_left_grid_pin_49_[0] , chanx_right_out[20] } ) , .sram ( mux_tree_tapbuf_size3_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_109 , SYNOPSYS_UNCONNECTED_110 } ) , .out ( chany_bottom_out[11] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_144 ) ) ; + .p0 ( optlc_net_149 ) ) ; sb_1__2__mux_tree_tapbuf_size3_2 mux_bottom_track_25 ( .in ( { chanx_left_out[21] , bottom_left_grid_pin_50_[0] , chanx_right_out[21] } ) , .sram ( mux_tree_tapbuf_size3_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_111 , SYNOPSYS_UNCONNECTED_112 } ) , .out ( chany_bottom_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_144 ) ) ; + .p0 ( optlc_net_149 ) ) ; sb_1__2__mux_tree_tapbuf_size3 mux_bottom_track_27 ( .in ( { chanx_left_out[23] , bottom_left_grid_pin_51_[0] , chanx_right_out[23] } ) , .sram ( mux_tree_tapbuf_size3_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_113 , SYNOPSYS_UNCONNECTED_114 } ) , .out ( chany_bottom_out[13] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_144 ) ) ; + .p0 ( optlc_net_149 ) ) ; sb_1__2__mux_tree_tapbuf_size3_mem_0 mem_bottom_track_21 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_4_ccff_tail ) , @@ -27549,67 +27519,67 @@ sb_1__2__mux_tree_tapbuf_size2_0 mux_bottom_track_29 ( .sram ( mux_tree_tapbuf_size2_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_115 , SYNOPSYS_UNCONNECTED_116 } ) , .out ( chany_bottom_out[14] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_144 ) ) ; + .p0 ( optlc_net_149 ) ) ; sb_1__2__mux_tree_tapbuf_size2_1 mux_bottom_track_31 ( .in ( { chanx_left_out[25] , chanx_right_out[25] } ) , .sram ( mux_tree_tapbuf_size2_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_117 , SYNOPSYS_UNCONNECTED_118 } ) , .out ( chany_bottom_out[15] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_142 ) ) ; + .p0 ( optlc_net_149 ) ) ; sb_1__2__mux_tree_tapbuf_size2_2 mux_bottom_track_33 ( .in ( { chanx_left_out[27] , chanx_right_out[27] } ) , .sram ( mux_tree_tapbuf_size2_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_119 , SYNOPSYS_UNCONNECTED_120 } ) , .out ( chany_bottom_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_142 ) ) ; + .p0 ( optlc_net_147 ) ) ; sb_1__2__mux_tree_tapbuf_size2_3 mux_bottom_track_35 ( .in ( { chanx_left_out[28] , chanx_right_out[28] } ) , .sram ( mux_tree_tapbuf_size2_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_121 , SYNOPSYS_UNCONNECTED_122 } ) , .out ( chany_bottom_out[17] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_142 ) ) ; + .p0 ( optlc_net_147 ) ) ; sb_1__2__mux_tree_tapbuf_size2_4 mux_bottom_track_39 ( .in ( { chanx_right_in[25] , bottom_left_grid_pin_45_[0] } ) , .sram ( mux_tree_tapbuf_size2_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_123 , SYNOPSYS_UNCONNECTED_124 } ) , .out ( chany_bottom_out[19] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_142 ) ) ; + .p0 ( optlc_net_147 ) ) ; sb_1__2__mux_tree_tapbuf_size2_5 mux_bottom_track_41 ( .in ( { chanx_right_in[21] , bottom_left_grid_pin_46_[0] } ) , .sram ( mux_tree_tapbuf_size2_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_125 , SYNOPSYS_UNCONNECTED_126 } ) , .out ( chany_bottom_out[20] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_142 ) ) ; + .p0 ( optlc_net_147 ) ) ; sb_1__2__mux_tree_tapbuf_size2_6 mux_bottom_track_43 ( .in ( { chanx_right_in[17] , bottom_left_grid_pin_47_[0] } ) , .sram ( mux_tree_tapbuf_size2_6_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_127 , SYNOPSYS_UNCONNECTED_128 } ) , .out ( chany_bottom_out[21] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_142 ) ) ; + .p0 ( optlc_net_147 ) ) ; sb_1__2__mux_tree_tapbuf_size2_7 mux_bottom_track_45 ( .in ( { chanx_right_in[13] , bottom_left_grid_pin_48_[0] } ) , .sram ( mux_tree_tapbuf_size2_7_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_129 , SYNOPSYS_UNCONNECTED_130 } ) , .out ( chany_bottom_out[22] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_142 ) ) ; + .p0 ( optlc_net_147 ) ) ; sb_1__2__mux_tree_tapbuf_size2_8 mux_bottom_track_47 ( .in ( { chanx_right_in[9] , bottom_left_grid_pin_49_[0] } ) , .sram ( mux_tree_tapbuf_size2_8_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_131 , SYNOPSYS_UNCONNECTED_132 } ) , .out ( chany_bottom_out[23] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_144 ) ) ; + .p0 ( optlc_net_149 ) ) ; sb_1__2__mux_tree_tapbuf_size2_9 mux_bottom_track_49 ( .in ( { chanx_right_in[5] , bottom_left_grid_pin_50_[0] } ) , .sram ( mux_tree_tapbuf_size2_9_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_133 , SYNOPSYS_UNCONNECTED_134 } ) , .out ( chany_bottom_out[24] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_144 ) ) ; + .p0 ( optlc_net_149 ) ) ; sb_1__2__mux_tree_tapbuf_size2 mux_bottom_track_51 ( .in ( { chanx_right_in[4] , bottom_left_grid_pin_51_[0] } ) , .sram ( mux_tree_tapbuf_size2_10_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_135 , SYNOPSYS_UNCONNECTED_136 } ) , .out ( chany_bottom_out[25] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_144 ) ) ; + .p0 ( optlc_net_149 ) ) ; sb_1__2__mux_tree_tapbuf_size2_mem_0 mem_bottom_track_29 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , @@ -27668,10 +27638,10 @@ sb_1__2__mux_tree_tapbuf_size2_mem mem_bottom_track_51 ( .pReset ( pReset ) , sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_E_in ) , .X ( pReset[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_1 pReset_W_FTB01 ( .A ( pReset_E_in ) , - .X ( net_net_139 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .X ( net_net_137 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_1 pReset_E_FTB01 ( .A ( pReset_E_in ) , .X ( aps_rename_505_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_S_in ) , +sky130_fd_sc_hd__buf_16 prog_clk_0_FTB00 ( .A ( prog_clk_0_S_in ) , .X ( prog_clk[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_49__48 ( .A ( chanx_right_in[0] ) , .X ( chany_bottom_out[28] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -27717,8 +27687,8 @@ sky130_fd_sc_hd__buf_8 FTB_69__68 ( .A ( chanx_right_in[27] ) , .X ( chanx_left_out[28] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_70__69 ( .A ( chanx_right_in[28] ) , .X ( chanx_left_out[29] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 FTB_71__70 ( .A ( chanx_left_in[0] ) , - .X ( ropt_net_167 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_71__70 ( .A ( chanx_left_in[0] ) , + .X ( chany_bottom_out[29] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_72__71 ( .A ( chanx_left_in[3] ) , .X ( chanx_right_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_73__72 ( .A ( chanx_left_in[6] ) , @@ -27737,8 +27707,8 @@ sky130_fd_sc_hd__buf_8 FTB_79__78 ( .A ( chanx_left_in[14] ) , .X ( chanx_right_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_80__79 ( .A ( chanx_left_in[15] ) , .X ( chanx_right_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 FTB_81__80 ( .A ( chanx_left_in[16] ) , - .X ( chanx_right_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 FTB_81__80 ( .A ( chanx_left_in[16] ) , + .X ( ropt_net_166 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_82__81 ( .A ( chanx_left_in[18] ) , .X ( chanx_right_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_83__82 ( .A ( chanx_left_in[19] ) , @@ -27759,24 +27729,26 @@ sky130_fd_sc_hd__buf_8 FTB_90__89 ( .A ( chanx_left_in[28] ) , .X ( chanx_right_out[29] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_91__90 ( .A ( SC_IN_BOT ) , .X ( SC_OUT_BOT ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_139 ( .A ( net_net_139 ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_137 ( .A ( net_net_137 ) , .X ( pReset_W_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_142 ( .LO ( SYNOPSYS_UNCONNECTED_137 ) , - .HI ( optlc_net_140 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_144 ( .LO ( SYNOPSYS_UNCONNECTED_138 ) , - .HI ( optlc_net_141 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_146 ( .LO ( SYNOPSYS_UNCONNECTED_139 ) , - .HI ( optlc_net_142 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_148 ( .LO ( SYNOPSYS_UNCONNECTED_140 ) , - .HI ( optlc_net_143 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_150 ( .LO ( SYNOPSYS_UNCONNECTED_141 ) , - .HI ( optlc_net_144 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_152 ( .LO ( SYNOPSYS_UNCONNECTED_142 ) , - .HI ( optlc_net_145 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 ZBUF_6_f_inst_153 ( .A ( aps_rename_505_ ) , +sky130_fd_sc_hd__conb_1 optlc_148 ( .LO ( SYNOPSYS_UNCONNECTED_137 ) , + .HI ( optlc_net_146 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_150 ( .LO ( SYNOPSYS_UNCONNECTED_138 ) , + .HI ( optlc_net_147 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_152 ( .LO ( SYNOPSYS_UNCONNECTED_139 ) , + .HI ( optlc_net_148 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_155 ( .LO ( SYNOPSYS_UNCONNECTED_140 ) , + .HI ( optlc_net_149 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_157 ( .LO ( SYNOPSYS_UNCONNECTED_141 ) , + .HI ( optlc_net_150 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_159 ( .LO ( SYNOPSYS_UNCONNECTED_142 ) , + .HI ( optlc_net_151 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_161 ( .LO ( SYNOPSYS_UNCONNECTED_143 ) , + .HI ( optlc_net_152 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_6_f_inst_162 ( .A ( aps_rename_505_ ) , .X ( pReset_E_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1349 ( .A ( ropt_net_167 ) , - .X ( chany_bottom_out[29] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1399 ( .A ( ropt_net_166 ) , + .X ( chanx_right_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -27802,7 +27774,7 @@ sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_1 FTB_44__43 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , +sky130_fd_sc_hd__buf_6 FTB_44__43 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -28434,13 +28406,9 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -28459,8 +28427,8 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -30206,7 +30174,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , @@ -30333,7 +30301,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , @@ -31179,20 +31147,26 @@ sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1366 ( .A ( copt_net_175 ) , +sky130_fd_sc_hd__buf_1 ropt_h_inst_1366 ( .A ( copt_net_175 ) , .X ( ropt_net_178 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1360 ( .A ( copt_net_174 ) , .X ( copt_net_172 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1361 ( .A ( copt_net_172 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1361 ( .A ( ropt_net_181 ) , .X ( copt_net_173 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1362 ( .A ( ropt_net_179 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1362 ( .A ( ccff_head[0] ) , .X ( copt_net_174 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1363 ( .A ( copt_net_173 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1363 ( .A ( ropt_net_183 ) , .X ( copt_net_175 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1364 ( .A ( ropt_net_178 ) , .X ( copt_net_176 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_1 ropt_h_inst_1367 ( .A ( ccff_head[0] ) , +sky130_fd_sc_hd__buf_4 ropt_h_inst_1371 ( .A ( ropt_net_180 ) , + .X ( ropt_net_183 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1367 ( .A ( copt_net_173 ) , .X ( ropt_net_179 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 ropt_h_inst_1368 ( .A ( ropt_net_179 ) , + .X ( ropt_net_180 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 ropt_h_inst_1369 ( .A ( copt_net_172 ) , + .X ( ropt_net_181 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -31287,7 +31261,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , @@ -32216,8 +32190,8 @@ sb_1__1__mux_tree_tapbuf_size10_9 mux_left_track_5 ( .sram ( mux_tree_tapbuf_size10_9_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_69 , SYNOPSYS_UNCONNECTED_70 , SYNOPSYS_UNCONNECTED_71 , SYNOPSYS_UNCONNECTED_72 } ) , - .out ( { ropt_net_180 } ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_159 ) ) ; + .out ( chanx_left_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , + .p0 ( optlc_net_159 ) ) ; sb_1__1__mux_tree_tapbuf_size10_10 mux_left_track_13 ( .in ( { chany_bottom_out[12] , chany_top_in[13] , chany_bottom_out[27] , chanx_left_out[12] , chanx_left_out[27] , chany_bottom_in[5] , @@ -32375,8 +32349,8 @@ sb_1__1__mux_tree_tapbuf_size12_6 mux_left_track_7 ( .sram ( mux_tree_tapbuf_size12_6_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_105 , SYNOPSYS_UNCONNECTED_106 , SYNOPSYS_UNCONNECTED_107 , SYNOPSYS_UNCONNECTED_108 } ) , - .out ( chanx_left_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_159 ) ) ; + .out ( { ropt_net_182 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_159 ) ) ; sb_1__1__mux_tree_tapbuf_size12 mux_left_track_11 ( .in ( { chany_bottom_out[11] , chany_top_in[17] , chany_bottom_out[25] , chanx_left_out[11] , chanx_left_out[25] , chany_bottom_in[4] , @@ -32530,8 +32504,8 @@ sb_1__1__mux_tree_tapbuf_size6_4 mux_right_track_44 ( .sram ( mux_tree_tapbuf_size6_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_141 , SYNOPSYS_UNCONNECTED_142 , SYNOPSYS_UNCONNECTED_143 } ) , - .out ( chanx_right_out[22] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_158 ) ) ; + .out ( { ZBUF_6_f_0 } ) , + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( optlc_net_158 ) ) ; sb_1__1__mux_tree_tapbuf_size6_5 mux_right_track_52 ( .in ( { chany_bottom_out[19] , chany_top_in[25] , right_bottom_grid_pin_41_[0] , chany_top_out[19] , @@ -32651,9 +32625,9 @@ sb_1__1__mux_tree_tapbuf_size6_mem_10 mem_left_track_45 ( .pReset ( pReset ) , .mem_out ( mux_tree_tapbuf_size6_10_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sb_1__1__mux_tree_tapbuf_size6_mem mem_left_track_53 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size6_mem_10_ccff_tail ) , - .ccff_tail ( { copt_net_170 } ) , - .mem_out ( mux_tree_tapbuf_size6_11_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; + .ccff_head ( mux_tree_tapbuf_size6_mem_10_ccff_tail ) , + .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size6_11_sram ) , + .VDD ( VDD ) , .VSS ( VSS ) ) ; sky130_fd_sc_hd__buf_4 Test_en_N_FTB01 ( .A ( Test_en_S_in ) , .X ( Test_en_N_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_E_in ) , .X ( pReset[0] ) , @@ -32834,10 +32808,10 @@ sky130_fd_sc_hd__conb_1 optlc_166 ( .LO ( SYNOPSYS_UNCONNECTED_169 ) , .HI ( optlc_net_160 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__conb_1 optlc_168 ( .LO ( SYNOPSYS_UNCONNECTED_170 ) , .HI ( optlc_net_161 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 copt_h_inst_1358 ( .A ( copt_net_170 ) , - .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 ropt_mt_inst_1368 ( .A ( ropt_net_180 ) , - .X ( chanx_left_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_6_f_inst_1350 ( .A ( ZBUF_6_f_0 ) , + .X ( chanx_right_out[22] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_4 ropt_mt_inst_1370 ( .A ( ropt_net_182 ) , + .X ( chanx_left_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -32984,10 +32958,10 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_144 ( .A ( BUF_net_145 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_147 ( .A ( BUF_net_148 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_145 ( .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .Y ( BUF_net_145 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_148 ( .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .Y ( BUF_net_148 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -33013,6 +32987,9 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -33040,14 +33017,10 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( +sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_130 ( .A ( BUF_net_131 ) , .Y ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_131 ( .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .Y ( BUF_net_131 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -33104,10 +33077,10 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_128 ( .A ( BUF_net_129 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_135 ( .A ( BUF_net_136 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_129 ( .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .Y ( BUF_net_129 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_136 ( .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .Y ( BUF_net_136 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -33198,10 +33171,10 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_126 ( .A ( BUF_net_127 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_133 ( .A ( BUF_net_134 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_127 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , - .Y ( BUF_net_127 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_134 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .Y ( BUF_net_134 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -33397,10 +33370,10 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_124 ( .A ( BUF_net_125 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_131 ( .A ( BUF_net_132 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_125 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , - .Y ( BUF_net_125 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_132 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .Y ( BUF_net_132 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -33425,9 +33398,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -33451,10 +33421,14 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ ( +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_129 ( .A ( BUF_net_130 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_130 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .Y ( BUF_net_130 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -33743,10 +33717,10 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_122 ( .A ( BUF_net_123 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_127 ( .A ( BUF_net_128 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_123 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_123 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_128 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_128 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -33771,7 +33745,7 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_121 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_126 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -33797,10 +33771,10 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_119 ( .A ( BUF_net_120 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_124 ( .A ( BUF_net_125 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_120 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_120 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_125 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_125 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -33852,10 +33826,10 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_117 ( .A ( BUF_net_118 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_122 ( .A ( BUF_net_123 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_118 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_118 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_123 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_123 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -33880,10 +33854,10 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_115 ( .A ( BUF_net_116 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_120 ( .A ( BUF_net_121 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_116 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_116 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_121 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_121 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -33908,10 +33882,10 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_113 ( .A ( BUF_net_114 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_118 ( .A ( BUF_net_119 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_114 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_114 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_119 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_119 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -33930,15 +33904,16 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_116 ( .A ( BUF_net_117 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_117 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_117 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -33963,10 +33938,10 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_111 ( .A ( BUF_net_112 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_114 ( .A ( BUF_net_115 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_112 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_112 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_115 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_115 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -34170,10 +34145,10 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_109 ( .A ( BUF_net_110 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_112 ( .A ( BUF_net_113 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_110 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .Y ( BUF_net_110 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_113 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .Y ( BUF_net_113 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -34203,10 +34178,10 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_107 ( .A ( BUF_net_108 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_110 ( .A ( BUF_net_111 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_108 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .Y ( BUF_net_108 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_111 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .Y ( BUF_net_111 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -34236,10 +34211,10 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_105 ( .A ( BUF_net_106 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_108 ( .A ( BUF_net_109 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_106 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .Y ( BUF_net_106 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_109 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .Y ( BUF_net_109 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -34522,6 +34497,9 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -34535,8 +34513,6 @@ sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_104 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -34593,9 +34569,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -34609,6 +34582,10 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_106 ( .A ( BUF_net_107 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_107 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_107 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -34642,10 +34619,10 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_102 ( .A ( BUF_net_103 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_104 ( .A ( BUF_net_105 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_103 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .Y ( BUF_net_103 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_105 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_105 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -34923,10 +34900,10 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_100 ( .A ( BUF_net_101 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_102 ( .A ( BUF_net_103 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_101 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .Y ( BUF_net_101 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_103 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .Y ( BUF_net_103 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -34948,6 +34925,9 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -34965,8 +34945,6 @@ sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_99 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -35005,7 +34983,7 @@ sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_98 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_101 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -35045,10 +35023,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_96 ( .A ( BUF_net_97 ) , .Y ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_97 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .Y ( BUF_net_97 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_100 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -35565,7 +35541,7 @@ input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_185 ) , +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_193 ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , @@ -35576,28 +35552,28 @@ sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1330 ( .A ( copt_net_155 ) , - .X ( copt_net_152 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1331 ( .A ( copt_net_157 ) , - .X ( copt_net_153 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1332 ( .A ( copt_net_152 ) , - .X ( copt_net_154 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1333 ( .A ( ccff_head[0] ) , - .X ( copt_net_155 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1334 ( .A ( copt_net_153 ) , - .X ( copt_net_156 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1335 ( .A ( copt_net_154 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1340 ( .A ( copt_net_159 ) , .X ( copt_net_157 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1357 ( .A ( copt_net_156 ) , - .X ( ropt_net_181 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1358 ( .A ( ropt_net_181 ) , - .X ( ropt_net_182 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1359 ( .A ( ropt_net_184 ) , - .X ( ropt_net_183 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1360 ( .A ( ropt_net_182 ) , - .X ( ropt_net_184 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1361 ( .A ( ropt_net_183 ) , - .X ( ropt_net_185 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1341 ( .A ( copt_net_157 ) , + .X ( copt_net_158 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1342 ( .A ( copt_net_160 ) , + .X ( copt_net_159 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1343 ( .A ( ccff_head[0] ) , + .X ( copt_net_160 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1344 ( .A ( copt_net_158 ) , + .X ( copt_net_161 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1345 ( .A ( copt_net_161 ) , + .X ( copt_net_162 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1371 ( .A ( copt_net_162 ) , + .X ( ropt_net_190 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1372 ( .A ( ropt_net_192 ) , + .X ( ropt_net_191 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1373 ( .A ( ropt_net_190 ) , + .X ( ropt_net_192 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1374 ( .A ( ropt_net_194 ) , + .X ( ropt_net_193 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1375 ( .A ( ropt_net_191 ) , + .X ( ropt_net_194 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -35695,7 +35671,7 @@ sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_95 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_99 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -35844,10 +35820,10 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_93 ( .A ( BUF_net_94 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_97 ( .A ( BUF_net_98 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_94 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .Y ( BUF_net_94 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_98 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .Y ( BUF_net_98 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -35995,10 +35971,10 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_142 ( .A ( BUF_net_143 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_95 ( .A ( BUF_net_96 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_143 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .Y ( BUF_net_143 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_96 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .Y ( BUF_net_96 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -36022,9 +35998,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -36045,10 +36018,14 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_93 ( .A ( BUF_net_94 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_94 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .Y ( BUF_net_94 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -36176,7 +36153,7 @@ output clk_3_N_out ; input VDD ; input VSS ; -wire ropt_net_170 ; +wire ropt_net_176 ; wire [0:0] prog_clk ; wire prog_clk_0 ; wire [0:3] mux_tree_tapbuf_size10_0_sram ; @@ -36289,7 +36266,7 @@ sb_1__0__mux_tree_tapbuf_size7_0 mux_top_track_0 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 } ) , .out ( chany_top_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_146 ) ) ; + .p0 ( optlc_net_154 ) ) ; sb_1__0__mux_tree_tapbuf_size7_1 mux_right_track_0 ( .in ( { chany_top_in[10] , chany_top_in[21] , right_bottom_grid_pin_1_[0] , right_bottom_grid_pin_7_[0] , @@ -36299,7 +36276,7 @@ sb_1__0__mux_tree_tapbuf_size7_1 mux_right_track_0 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 } ) , .out ( chanx_right_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_151 ) ) ; + .p0 ( optlc_net_154 ) ) ; sb_1__0__mux_tree_tapbuf_size7_2 mux_right_track_12 ( .in ( { chany_top_in[4] , chany_top_in[15] , chany_top_in[26] , right_bottom_grid_pin_1_[0] , right_bottom_grid_pin_13_[0] , @@ -36308,7 +36285,7 @@ sb_1__0__mux_tree_tapbuf_size7_2 mux_right_track_12 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 , SYNOPSYS_UNCONNECTED_9 } ) , .out ( chanx_right_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_151 ) ) ; + .p0 ( optlc_net_154 ) ) ; sb_1__0__mux_tree_tapbuf_size7_3 mux_right_track_20 ( .in ( { chany_top_in[5] , chany_top_in[16] , chany_top_in[27] , right_bottom_grid_pin_3_[0] , right_bottom_grid_pin_15_[0] , @@ -36317,7 +36294,7 @@ sb_1__0__mux_tree_tapbuf_size7_3 mux_right_track_20 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , .out ( chanx_right_out[10] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_147 ) ) ; + .p0 ( optlc_net_150 ) ) ; sb_1__0__mux_tree_tapbuf_size7_4 mux_right_track_28 ( .in ( { chany_top_in[6] , chany_top_in[17] , chany_top_in[28] , right_bottom_grid_pin_5_[0] , right_bottom_grid_pin_17_[0] , @@ -36326,7 +36303,7 @@ sb_1__0__mux_tree_tapbuf_size7_4 mux_right_track_28 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , SYNOPSYS_UNCONNECTED_15 } ) , .out ( chanx_right_out[14] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_147 ) ) ; + .p0 ( optlc_net_150 ) ) ; sb_1__0__mux_tree_tapbuf_size7_5 mux_left_track_3 ( .in ( { chany_top_in[10] , chany_top_in[21] , chanx_left_out[7] , chanx_left_out[21] , left_bottom_grid_pin_3_[0] , @@ -36335,7 +36312,7 @@ sb_1__0__mux_tree_tapbuf_size7_5 mux_left_track_3 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_16 , SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 } ) , .out ( chanx_left_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_146 ) ) ; + .p0 ( optlc_net_151 ) ) ; sb_1__0__mux_tree_tapbuf_size7_6 mux_left_track_5 ( .in ( { chany_top_in[9] , chany_top_in[20] , chanx_left_out[8] , chanx_left_out[23] , left_bottom_grid_pin_5_[0] , @@ -36344,7 +36321,7 @@ sb_1__0__mux_tree_tapbuf_size7_6 mux_left_track_5 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 , SYNOPSYS_UNCONNECTED_21 } ) , .out ( chanx_left_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_148 ) ) ; + .p0 ( optlc_net_149 ) ) ; sb_1__0__mux_tree_tapbuf_size7_7 mux_left_track_13 ( .in ( { chany_top_in[6] , chany_top_in[17] , chany_top_in[28] , chanx_left_out[12] , chanx_left_out[27] , left_bottom_grid_pin_1_[0] , @@ -36353,7 +36330,7 @@ sb_1__0__mux_tree_tapbuf_size7_7 mux_left_track_13 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_22 , SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) , .out ( chanx_left_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_148 ) ) ; + .p0 ( optlc_net_149 ) ) ; sb_1__0__mux_tree_tapbuf_size7_8 mux_left_track_21 ( .in ( { chany_top_in[5] , chany_top_in[16] , chany_top_in[27] , chanx_left_out[13] , chanx_left_out[28] , left_bottom_grid_pin_3_[0] , @@ -36362,7 +36339,7 @@ sb_1__0__mux_tree_tapbuf_size7_8 mux_left_track_21 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , SYNOPSYS_UNCONNECTED_27 } ) , .out ( chanx_left_out[10] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_146 ) ) ; + .p0 ( optlc_net_149 ) ) ; sb_1__0__mux_tree_tapbuf_size7 mux_left_track_29 ( .in ( { chany_top_in[4] , chany_top_in[15] , chany_top_in[26] , chanx_left_out[15] , chanx_left_out[29] , left_bottom_grid_pin_5_[0] , @@ -36371,7 +36348,7 @@ sb_1__0__mux_tree_tapbuf_size7 mux_left_track_29 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_28 , SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 } ) , .out ( chanx_left_out[14] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_146 ) ) ; + .p0 ( optlc_net_149 ) ) ; sb_1__0__mux_tree_tapbuf_size7_mem_0 mem_top_track_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , @@ -36429,7 +36406,7 @@ sb_1__0__mux_tree_tapbuf_size6_0 mux_top_track_2 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 , SYNOPSYS_UNCONNECTED_33 } ) , .out ( chany_top_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_151 ) ) ; + .p0 ( optlc_net_152 ) ) ; sb_1__0__mux_tree_tapbuf_size6_1 mux_top_track_6 ( .in ( { top_left_grid_pin_44_[0] , top_left_grid_pin_47_[0] , top_left_grid_pin_50_[0] , chanx_right_in[5] , chanx_left_out[9] , @@ -36438,7 +36415,7 @@ sb_1__0__mux_tree_tapbuf_size6_1 mux_top_track_6 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_34 , SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) , .out ( chany_top_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_151 ) ) ; + .p0 ( optlc_net_152 ) ) ; sb_1__0__mux_tree_tapbuf_size6 mux_top_track_8 ( .in ( { chany_top_out[19] , top_left_grid_pin_48_[0] , top_left_grid_pin_51_[0] , chanx_right_in[9] , chanx_left_out[11] , @@ -36447,7 +36424,7 @@ sb_1__0__mux_tree_tapbuf_size6 mux_top_track_8 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 , SYNOPSYS_UNCONNECTED_39 } ) , .out ( chany_top_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_150 ) ) ; + .p0 ( optlc_net_152 ) ) ; sb_1__0__mux_tree_tapbuf_size6_mem_0 mem_top_track_2 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , @@ -36470,7 +36447,7 @@ sb_1__0__mux_tree_tapbuf_size5_0 mux_top_track_4 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_40 , SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 } ) , .out ( chany_top_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_150 ) ) ; + .p0 ( optlc_net_152 ) ) ; sb_1__0__mux_tree_tapbuf_size5_1 mux_top_track_10 ( .in ( { top_left_grid_pin_46_[0] , top_left_grid_pin_49_[0] , chanx_left_out[12] , chanx_right_in[13] , chanx_right_out[12] } ) , @@ -36478,7 +36455,7 @@ sb_1__0__mux_tree_tapbuf_size5_1 mux_top_track_10 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 , SYNOPSYS_UNCONNECTED_45 } ) , .out ( chany_top_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_149 ) ) ; + .p0 ( optlc_net_155 ) ) ; sb_1__0__mux_tree_tapbuf_size5_2 mux_right_track_36 ( .in ( { chany_top_in[7] , chany_top_in[18] , chany_top_in[29] , right_bottom_grid_pin_7_[0] , chanx_right_out[16] } ) , @@ -36486,7 +36463,7 @@ sb_1__0__mux_tree_tapbuf_size5_2 mux_right_track_36 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_46 , SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) , .out ( chanx_right_out[18] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_147 ) ) ; + .p0 ( optlc_net_150 ) ) ; sb_1__0__mux_tree_tapbuf_size5_3 mux_left_track_37 ( .in ( { chany_top_in[3] , chany_top_in[14] , chany_top_in[25] , chanx_left_out[16] , left_bottom_grid_pin_7_[0] } ) , @@ -36494,7 +36471,7 @@ sb_1__0__mux_tree_tapbuf_size5_3 mux_left_track_37 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 , SYNOPSYS_UNCONNECTED_51 } ) , .out ( chanx_left_out[18] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_146 ) ) ; + .p0 ( optlc_net_151 ) ) ; sb_1__0__mux_tree_tapbuf_size5_4 mux_left_track_45 ( .in ( { chany_top_in[2] , chany_top_in[13] , chany_top_in[24] , chanx_left_out[17] , left_bottom_grid_pin_9_[0] } ) , @@ -36502,7 +36479,7 @@ sb_1__0__mux_tree_tapbuf_size5_4 mux_left_track_45 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_52 , SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 } ) , .out ( chanx_left_out[22] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_146 ) ) ; + .p0 ( optlc_net_151 ) ) ; sb_1__0__mux_tree_tapbuf_size5 mux_left_track_53 ( .in ( { chany_top_in[1] , chany_top_in[12] , chany_top_in[23] , chanx_left_out[19] , left_bottom_grid_pin_11_[0] } ) , @@ -36510,7 +36487,7 @@ sb_1__0__mux_tree_tapbuf_size5 mux_left_track_53 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 , SYNOPSYS_UNCONNECTED_57 } ) , .out ( chanx_left_out[26] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_148 ) ) ; + .p0 ( optlc_net_149 ) ) ; sb_1__0__mux_tree_tapbuf_size5_mem_0 mem_top_track_4 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , @@ -36548,7 +36525,7 @@ sb_1__0__mux_tree_tapbuf_size4_0 mux_top_track_12 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_58 , SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) , .out ( chany_top_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_151 ) ) ; + .p0 ( optlc_net_152 ) ) ; sb_1__0__mux_tree_tapbuf_size4_1 mux_top_track_14 ( .in ( { chany_top_out[19] , chanx_left_out[15] , chanx_right_in[21] , chanx_right_out[15] } ) , @@ -36556,7 +36533,7 @@ sb_1__0__mux_tree_tapbuf_size4_1 mux_top_track_14 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 , SYNOPSYS_UNCONNECTED_63 } ) , .out ( chany_top_out[7] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_147 ) ) ; + .p0 ( optlc_net_150 ) ) ; sb_1__0__mux_tree_tapbuf_size4_2 mux_top_track_16 ( .in ( { top_left_grid_pin_46_[0] , chanx_left_out[16] , chanx_right_in[25] , chanx_right_out[16] } ) , @@ -36572,7 +36549,7 @@ sb_1__0__mux_tree_tapbuf_size4_3 mux_top_track_18 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 , SYNOPSYS_UNCONNECTED_69 } ) , .out ( chany_top_out[9] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_150 ) ) ; + .p0 ( optlc_net_155 ) ) ; sb_1__0__mux_tree_tapbuf_size4_4 mux_right_track_44 ( .in ( { chany_top_in[8] , chany_top_in[19] , right_bottom_grid_pin_9_[0] , chanx_right_out[17] } ) , @@ -36580,7 +36557,7 @@ sb_1__0__mux_tree_tapbuf_size4_4 mux_right_track_44 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_70 , SYNOPSYS_UNCONNECTED_71 , SYNOPSYS_UNCONNECTED_72 } ) , .out ( chanx_right_out[22] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_147 ) ) ; + .p0 ( optlc_net_150 ) ) ; sb_1__0__mux_tree_tapbuf_size4 mux_right_track_52 ( .in ( { chany_top_in[9] , chany_top_in[20] , right_bottom_grid_pin_11_[0] , chanx_right_out[19] } ) , @@ -36588,7 +36565,7 @@ sb_1__0__mux_tree_tapbuf_size4 mux_right_track_52 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_73 , SYNOPSYS_UNCONNECTED_74 , SYNOPSYS_UNCONNECTED_75 } ) , .out ( chanx_right_out[26] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_147 ) ) ; + .p0 ( optlc_net_150 ) ) ; sb_1__0__mux_tree_tapbuf_size4_mem_0 mem_top_track_12 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , @@ -36625,35 +36602,35 @@ sb_1__0__mux_tree_tapbuf_size3_0 mux_top_track_20 ( .sram ( mux_tree_tapbuf_size3_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_76 , SYNOPSYS_UNCONNECTED_77 } ) , .out ( chany_top_out[10] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_149 ) ) ; + .p0 ( optlc_net_155 ) ) ; sb_1__0__mux_tree_tapbuf_size3_1 mux_top_track_22 ( .in ( { top_left_grid_pin_49_[0] , chanx_left_out[20] , chanx_right_out[20] } ) , .sram ( mux_tree_tapbuf_size3_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_78 , SYNOPSYS_UNCONNECTED_79 } ) , .out ( chany_top_out[11] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_149 ) ) ; + .p0 ( optlc_net_156 ) ) ; sb_1__0__mux_tree_tapbuf_size3_2 mux_top_track_24 ( .in ( { top_left_grid_pin_50_[0] , chanx_left_out[21] , chanx_right_out[21] } ) , .sram ( mux_tree_tapbuf_size3_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_80 , SYNOPSYS_UNCONNECTED_81 } ) , .out ( chany_top_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_149 ) ) ; + .p0 ( optlc_net_155 ) ) ; sb_1__0__mux_tree_tapbuf_size3_3 mux_top_track_26 ( .in ( { top_left_grid_pin_51_[0] , chanx_left_out[23] , chanx_right_out[23] } ) , .sram ( mux_tree_tapbuf_size3_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_82 , SYNOPSYS_UNCONNECTED_83 } ) , .out ( chany_top_out[13] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_150 ) ) ; + .p0 ( optlc_net_155 ) ) ; sb_1__0__mux_tree_tapbuf_size3 mux_top_track_36 ( .in ( { top_left_grid_pin_44_[0] , chanx_left_out[29] , chanx_right_out[29] } ) , .sram ( mux_tree_tapbuf_size3_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_84 , SYNOPSYS_UNCONNECTED_85 } ) , .out ( chany_top_out[18] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_149 ) ) ; + .p0 ( optlc_net_156 ) ) ; sb_1__0__mux_tree_tapbuf_size3_mem_0 mem_top_track_20 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , @@ -36684,67 +36661,67 @@ sb_1__0__mux_tree_tapbuf_size2_0 mux_top_track_28 ( .sram ( mux_tree_tapbuf_size2_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_86 , SYNOPSYS_UNCONNECTED_87 } ) , .out ( chany_top_out[14] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_150 ) ) ; + .p0 ( optlc_net_155 ) ) ; sb_1__0__mux_tree_tapbuf_size2_1 mux_top_track_30 ( .in ( { chanx_left_out[25] , chanx_right_out[25] } ) , .sram ( mux_tree_tapbuf_size2_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_88 , SYNOPSYS_UNCONNECTED_89 } ) , .out ( chany_top_out[15] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_150 ) ) ; + .p0 ( optlc_net_152 ) ) ; sb_1__0__mux_tree_tapbuf_size2_2 mux_top_track_32 ( .in ( { chanx_left_out[27] , chanx_right_out[27] } ) , .sram ( mux_tree_tapbuf_size2_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_90 , SYNOPSYS_UNCONNECTED_91 } ) , .out ( chany_top_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_150 ) ) ; + .p0 ( optlc_net_155 ) ) ; sb_1__0__mux_tree_tapbuf_size2_3 mux_top_track_34 ( .in ( { chanx_left_out[28] , chanx_right_out[28] } ) , .sram ( mux_tree_tapbuf_size2_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_92 , SYNOPSYS_UNCONNECTED_93 } ) , .out ( chany_top_out[17] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_149 ) ) ; + .p0 ( optlc_net_156 ) ) ; sb_1__0__mux_tree_tapbuf_size2_4 mux_top_track_40 ( .in ( { top_left_grid_pin_46_[0] , chanx_left_in[29] } ) , .sram ( mux_tree_tapbuf_size2_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_94 , SYNOPSYS_UNCONNECTED_95 } ) , .out ( chany_top_out[20] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_149 ) ) ; + .p0 ( optlc_net_156 ) ) ; sb_1__0__mux_tree_tapbuf_size2_5 mux_top_track_42 ( .in ( { top_left_grid_pin_47_[0] , chanx_left_in[25] } ) , .sram ( mux_tree_tapbuf_size2_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_96 , SYNOPSYS_UNCONNECTED_97 } ) , .out ( chany_top_out[21] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_149 ) ) ; + .p0 ( optlc_net_156 ) ) ; sb_1__0__mux_tree_tapbuf_size2_6 mux_top_track_44 ( .in ( { top_left_grid_pin_48_[0] , chanx_left_in[21] } ) , .sram ( mux_tree_tapbuf_size2_6_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_98 , SYNOPSYS_UNCONNECTED_99 } ) , .out ( chany_top_out[22] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_149 ) ) ; + .p0 ( optlc_net_156 ) ) ; sb_1__0__mux_tree_tapbuf_size2_7 mux_top_track_46 ( .in ( { top_left_grid_pin_49_[0] , chanx_left_in[17] } ) , .sram ( mux_tree_tapbuf_size2_7_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_100 , SYNOPSYS_UNCONNECTED_101 } ) , .out ( chany_top_out[23] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_149 ) ) ; + .p0 ( optlc_net_156 ) ) ; sb_1__0__mux_tree_tapbuf_size2_8 mux_top_track_48 ( .in ( { top_left_grid_pin_50_[0] , chanx_left_in[13] } ) , .sram ( mux_tree_tapbuf_size2_8_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_102 , SYNOPSYS_UNCONNECTED_103 } ) , .out ( chany_top_out[24] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_149 ) ) ; + .p0 ( optlc_net_156 ) ) ; sb_1__0__mux_tree_tapbuf_size2_9 mux_top_track_50 ( .in ( { top_left_grid_pin_51_[0] , chanx_left_in[9] } ) , .sram ( mux_tree_tapbuf_size2_9_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_104 , SYNOPSYS_UNCONNECTED_105 } ) , .out ( chany_top_out[25] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_149 ) ) ; + .p0 ( optlc_net_155 ) ) ; sb_1__0__mux_tree_tapbuf_size2 mux_top_track_58 ( .in ( { chanx_right_in[0] , chanx_left_in[1] } ) , .sram ( mux_tree_tapbuf_size2_10_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_106 , SYNOPSYS_UNCONNECTED_107 } ) , .out ( chany_top_out[29] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_150 ) ) ; + .p0 ( optlc_net_154 ) ) ; sb_1__0__mux_tree_tapbuf_size2_mem_0 mem_top_track_28 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , @@ -36809,7 +36786,7 @@ sb_1__0__mux_tree_tapbuf_size8_0 mux_right_track_2 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_108 , SYNOPSYS_UNCONNECTED_109 , SYNOPSYS_UNCONNECTED_110 , SYNOPSYS_UNCONNECTED_111 } ) , .out ( chanx_right_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_147 ) ) ; + .p0 ( optlc_net_150 ) ) ; sb_1__0__mux_tree_tapbuf_size8_1 mux_right_track_4 ( .in ( { chany_top_in[1] , chany_top_in[12] , chany_top_in[23] , right_bottom_grid_pin_5_[0] , right_bottom_grid_pin_11_[0] , @@ -36819,7 +36796,7 @@ sb_1__0__mux_tree_tapbuf_size8_1 mux_right_track_4 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_112 , SYNOPSYS_UNCONNECTED_113 , SYNOPSYS_UNCONNECTED_114 , SYNOPSYS_UNCONNECTED_115 } ) , .out ( chanx_right_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_147 ) ) ; + .p0 ( optlc_net_150 ) ) ; sb_1__0__mux_tree_tapbuf_size8 mux_left_track_1 ( .in ( { chany_top_in[0] , chany_top_in[11] , chany_top_in[22] , chanx_left_out[4] , chanx_left_out[20] , left_bottom_grid_pin_1_[0] , @@ -36828,7 +36805,7 @@ sb_1__0__mux_tree_tapbuf_size8 mux_left_track_1 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_116 , SYNOPSYS_UNCONNECTED_117 , SYNOPSYS_UNCONNECTED_118 , SYNOPSYS_UNCONNECTED_119 } ) , .out ( chanx_left_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_148 ) ) ; + .p0 ( optlc_net_151 ) ) ; sb_1__0__mux_tree_tapbuf_size8_mem_0 mem_right_track_2 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , @@ -36854,7 +36831,7 @@ sb_1__0__mux_tree_tapbuf_size10 mux_right_track_6 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_120 , SYNOPSYS_UNCONNECTED_121 , SYNOPSYS_UNCONNECTED_122 , SYNOPSYS_UNCONNECTED_123 } ) , .out ( chanx_right_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_151 ) ) ; + .p0 ( optlc_net_153 ) ) ; sb_1__0__mux_tree_tapbuf_size10_mem mem_right_track_6 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , @@ -36869,7 +36846,7 @@ sb_1__0__mux_tree_tapbuf_size9_0 mux_right_track_10 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_124 , SYNOPSYS_UNCONNECTED_125 , SYNOPSYS_UNCONNECTED_126 , SYNOPSYS_UNCONNECTED_127 } ) , .out ( chanx_right_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_151 ) ) ; + .p0 ( optlc_net_153 ) ) ; sb_1__0__mux_tree_tapbuf_size9_1 mux_left_track_7 ( .in ( { chany_top_in[8] , chany_top_in[19] , chanx_left_out[9] , chanx_left_out[24] , left_bottom_grid_pin_1_[0] , @@ -36879,7 +36856,7 @@ sb_1__0__mux_tree_tapbuf_size9_1 mux_left_track_7 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_128 , SYNOPSYS_UNCONNECTED_129 , SYNOPSYS_UNCONNECTED_130 , SYNOPSYS_UNCONNECTED_131 } ) , .out ( chanx_left_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_148 ) ) ; + .p0 ( optlc_net_151 ) ) ; sb_1__0__mux_tree_tapbuf_size9 mux_left_track_11 ( .in ( { chany_top_in[7] , chany_top_in[18] , chany_top_in[29] , chanx_left_out[11] , chanx_left_out[25] , left_bottom_grid_pin_3_[0] , @@ -36889,7 +36866,7 @@ sb_1__0__mux_tree_tapbuf_size9 mux_left_track_11 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_132 , SYNOPSYS_UNCONNECTED_133 , SYNOPSYS_UNCONNECTED_134 , SYNOPSYS_UNCONNECTED_135 } ) , .out ( chanx_left_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_148 ) ) ; + .p0 ( optlc_net_149 ) ) ; sb_1__0__mux_tree_tapbuf_size9_mem_0 mem_right_track_10 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , @@ -36905,8 +36882,8 @@ sb_1__0__mux_tree_tapbuf_size9_mem mem_left_track_11 ( .pReset ( pReset ) , .ccff_head ( mux_tree_tapbuf_size9_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size9_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size9_2_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_148 ( .LO ( SYNOPSYS_UNCONNECTED_136 ) , - .HI ( optlc_net_146 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_151 ( .LO ( SYNOPSYS_UNCONNECTED_136 ) , + .HI ( optlc_net_149 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_E_in ) , .X ( pReset[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_1 pReset_N_FTB01 ( .A ( pReset_E_in ) , @@ -36915,8 +36892,8 @@ sky130_fd_sc_hd__bufbuf_16 pReset_W_FTB01 ( .A ( pReset_E_in ) , .X ( pReset_W_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__bufbuf_16 pReset_E_FTB01 ( .A ( pReset_E_in ) , .X ( pReset_E_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_150 ( .LO ( SYNOPSYS_UNCONNECTED_137 ) , - .HI ( optlc_net_147 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_153 ( .LO ( SYNOPSYS_UNCONNECTED_137 ) , + .HI ( optlc_net_150 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_N_in ) , .X ( prog_clk[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_1 prog_clk_3_N_FTB01 ( .A ( prog_clk_3_S_in ) , @@ -36925,7 +36902,7 @@ sky130_fd_sc_hd__buf_1 clk_3_N_FTB01 ( .A ( clk_3_S_in ) , .X ( aps_rename_507_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_49__48 ( .A ( top_left_grid_pin_45_[0] ) , .X ( chany_top_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 FTB_50__49 ( .A ( chanx_right_in[3] ) , +sky130_fd_sc_hd__buf_12 FTB_50__49 ( .A ( chanx_right_in[3] ) , .X ( chanx_left_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_51__50 ( .A ( chanx_right_in[6] ) , .X ( chanx_left_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -37007,37 +36984,41 @@ sky130_fd_sc_hd__buf_8 FTB_89__88 ( .A ( chanx_left_in[27] ) , .X ( chanx_right_out[28] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_90__89 ( .A ( chanx_left_in[28] ) , .X ( chanx_right_out[29] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 FTB_91__90 ( .A ( SC_IN_TOP ) , .X ( ropt_net_170 ) , +sky130_fd_sc_hd__buf_6 FTB_91__90 ( .A ( SC_IN_TOP ) , .X ( ropt_net_176 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_132 ( .A ( BUF_net_133 ) , +sky130_fd_sc_hd__inv_8 BINV_R_137 ( .A ( BUF_net_138 ) , .Y ( Test_en_N_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_133 ( .A ( Test_en_S_in ) , .Y ( BUF_net_133 ) , +sky130_fd_sc_hd__inv_1 BINV_R_138 ( .A ( Test_en_S_in ) , .Y ( BUF_net_138 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_134 ( .A ( BUF_net_135 ) , .Y ( pReset_N_out ) , +sky130_fd_sc_hd__inv_8 BINV_R_139 ( .A ( BUF_net_140 ) , .Y ( pReset_N_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_135 ( .A ( aps_rename_505_ ) , - .Y ( BUF_net_135 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_136 ( .A ( BUF_net_137 ) , .Y ( Reset_N_out ) , +sky130_fd_sc_hd__inv_1 BINV_R_140 ( .A ( aps_rename_505_ ) , + .Y ( BUF_net_140 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_141 ( .A ( BUF_net_142 ) , .Y ( Reset_N_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_137 ( .A ( Reset_S_in ) , .Y ( BUF_net_137 ) , +sky130_fd_sc_hd__inv_1 BINV_R_142 ( .A ( Reset_S_in ) , .Y ( BUF_net_142 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_138 ( .A ( BUF_net_139 ) , +sky130_fd_sc_hd__inv_8 BINV_R_143 ( .A ( BUF_net_144 ) , .Y ( prog_clk_3_N_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_139 ( .A ( aps_rename_506_ ) , - .Y ( BUF_net_139 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_140 ( .A ( BUF_net_141 ) , .Y ( clk_3_N_out ) , +sky130_fd_sc_hd__inv_1 BINV_R_144 ( .A ( aps_rename_506_ ) , + .Y ( BUF_net_144 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_145 ( .A ( BUF_net_146 ) , .Y ( clk_3_N_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_141 ( .A ( aps_rename_507_ ) , - .Y ( BUF_net_141 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_152 ( .LO ( SYNOPSYS_UNCONNECTED_138 ) , - .HI ( optlc_net_148 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_154 ( .LO ( SYNOPSYS_UNCONNECTED_139 ) , - .HI ( optlc_net_149 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_156 ( .LO ( SYNOPSYS_UNCONNECTED_140 ) , - .HI ( optlc_net_150 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_158 ( .LO ( SYNOPSYS_UNCONNECTED_141 ) , +sky130_fd_sc_hd__inv_1 BINV_R_146 ( .A ( aps_rename_507_ ) , + .Y ( BUF_net_146 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_155 ( .LO ( SYNOPSYS_UNCONNECTED_138 ) , .HI ( optlc_net_151 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1347 ( .A ( ropt_net_170 ) , +sky130_fd_sc_hd__conb_1 optlc_157 ( .LO ( SYNOPSYS_UNCONNECTED_139 ) , + .HI ( optlc_net_152 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_162 ( .LO ( SYNOPSYS_UNCONNECTED_140 ) , + .HI ( optlc_net_153 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_164 ( .LO ( SYNOPSYS_UNCONNECTED_141 ) , + .HI ( optlc_net_154 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_166 ( .LO ( SYNOPSYS_UNCONNECTED_142 ) , + .HI ( optlc_net_155 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_168 ( .LO ( SYNOPSYS_UNCONNECTED_143 ) , + .HI ( optlc_net_156 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1359 ( .A ( ropt_net_176 ) , .X ( SC_OUT_TOP ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -37164,7 +37145,7 @@ output [0:1] mem_out ; input VDD ; input VSS ; -wire copt_net_102 ; +wire copt_net_103 ; supply1 VDD ; supply0 VSS ; @@ -37172,15 +37153,15 @@ sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( copt_net_102 ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( copt_net_103 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_6 FTB_33__32 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1267 ( .A ( copt_net_102 ) , - .X ( copt_net_101 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1269 ( .A ( copt_net_101 ) , - .X ( copt_net_103 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1270 ( .A ( copt_net_103 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1265 ( .A ( copt_net_103 ) , + .X ( copt_net_99 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1266 ( .A ( copt_net_99 ) , + .X ( copt_net_100 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1267 ( .A ( copt_net_100 ) , .X ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -37824,15 +37805,14 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_84 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -37932,15 +37912,16 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_79 ( .A ( BUF_net_80 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_80 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_80 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -37986,16 +37967,15 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_79 ( .A ( BUF_net_80 ) , .Y ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_80 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_80 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -38101,10 +38081,10 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_77 ( .A ( BUF_net_78 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_6 BINV_R_86 ( .A ( BUF_net_87 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_78 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_78 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_87 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_87 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -38129,7 +38109,7 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_76 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_78 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -38179,13 +38159,11 @@ supply0 VSS ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_88 ( .A ( BUF_net_89 ) , .Y ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_89 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_89 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_77 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -38210,10 +38188,10 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_74 ( .A ( BUF_net_75 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_75 ( .A ( BUF_net_76 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_75 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_75 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_76 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_76 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -38238,10 +38216,10 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_72 ( .A ( BUF_net_73 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_6 BINV_R_73 ( .A ( BUF_net_74 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_73 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_73 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_74 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_74 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -38260,16 +38238,15 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_86 ( .A ( BUF_net_87 ) , .Y ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_87 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_87 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -38288,14 +38265,15 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_71 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -38368,16 +38346,15 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_84 ( .A ( BUF_net_85 ) , .Y ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_85 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_85 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -38402,10 +38379,10 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_69 ( .A ( BUF_net_70 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_71 ( .A ( BUF_net_72 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_70 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_70 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_72 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_72 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -38430,8 +38407,10 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_68 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_69 ( .A ( BUF_net_70 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_70 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_70 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -38504,14 +38483,15 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_67 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -38536,10 +38516,10 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_65 ( .A ( BUF_net_66 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_67 ( .A ( BUF_net_68 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_66 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_66 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_68 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_68 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -38691,7 +38671,7 @@ input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_181 ) , +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_190 ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , @@ -38702,26 +38682,24 @@ sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1258 ( .A ( copt_net_94 ) , + .X ( copt_net_92 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1259 ( .A ( copt_net_92 ) , + .X ( copt_net_93 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1260 ( .A ( copt_net_96 ) , .X ( copt_net_94 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1261 ( .A ( copt_net_94 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1261 ( .A ( ccff_head[0] ) , .X ( copt_net_95 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 copt_h_inst_1262 ( .A ( copt_net_97 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1262 ( .A ( copt_net_95 ) , .X ( copt_net_96 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1263 ( .A ( copt_net_98 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1263 ( .A ( copt_net_93 ) , .X ( copt_net_97 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1264 ( .A ( copt_net_99 ) , - .X ( copt_net_98 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1265 ( .A ( ccff_head[0] ) , - .X ( copt_net_99 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1343 ( .A ( copt_net_95 ) , - .X ( ropt_net_178 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1344 ( .A ( ropt_net_178 ) , - .X ( ropt_net_179 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1345 ( .A ( ropt_net_179 ) , - .X ( ropt_net_180 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 ropt_h_inst_1346 ( .A ( ropt_net_180 ) , - .X ( ropt_net_181 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1351 ( .A ( copt_net_97 ) , + .X ( ropt_net_188 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1352 ( .A ( ropt_net_188 ) , + .X ( ropt_net_189 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 ropt_h_inst_1353 ( .A ( ropt_net_189 ) , + .X ( ropt_net_190 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -38742,6 +38720,43 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_65 ( .A ( BUF_net_66 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_66 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_66 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size4_4 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +supply1 VDD ; +supply0 VSS ; + sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -38762,43 +38777,6 @@ sky130_fd_sc_hd__inv_1 BINV_R_64 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , endmodule -module sb_0__2__mux_tree_tapbuf_size4_4 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:3] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_61 ( .A ( BUF_net_62 ) , .Y ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_62 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .Y ( BUF_net_62 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - module sb_0__2__mux_tree_tapbuf_size4_3 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; input [0:3] in ; @@ -38816,9 +38794,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -38832,6 +38807,10 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_61 ( .A ( BUF_net_62 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_62 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_62 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -38977,10 +38956,9 @@ input VDD ; input VSS ; wire ropt_net_129 ; -wire ropt_net_127 ; -wire ropt_net_137 ; +wire ropt_net_130 ; +wire ropt_net_131 ; wire ropt_net_128 ; -wire ropt_net_134 ; wire [0:0] prog_clk ; wire prog_clk_0 ; wire [0:1] mux_tree_tapbuf_size2_0_sram ; @@ -39072,7 +39050,7 @@ sb_0__2__mux_tree_tapbuf_size4_1 mux_right_track_2 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 } ) , .out ( chanx_right_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_92 ) ) ; + .p0 ( optlc_net_90 ) ) ; sb_0__2__mux_tree_tapbuf_size4_2 mux_right_track_4 ( .in ( { right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_40_[0] , right_bottom_grid_pin_43_[0] , chany_bottom_in[26] } ) , @@ -39088,7 +39066,7 @@ sb_0__2__mux_tree_tapbuf_size4_3 mux_right_track_6 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , .out ( chanx_right_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_92 ) ) ; + .p0 ( optlc_net_90 ) ) ; sb_0__2__mux_tree_tapbuf_size4_4 mux_right_track_8 ( .in ( { right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_39_[0] , right_bottom_grid_pin_42_[0] , chany_bottom_in[24] } ) , @@ -39139,91 +39117,91 @@ sb_0__2__mux_tree_tapbuf_size2_0 mux_right_track_12 ( .sram ( mux_tree_tapbuf_size2_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) , .out ( chanx_right_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_90 ) ) ; + .p0 ( optlc_net_91 ) ) ; sb_0__2__mux_tree_tapbuf_size2_1 mux_right_track_14 ( .in ( { right_bottom_grid_pin_36_[0] , chany_bottom_in[21] } ) , .sram ( mux_tree_tapbuf_size2_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 } ) , .out ( chanx_right_out[7] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_93 ) ) ; + .p0 ( optlc_net_88 ) ) ; sb_0__2__mux_tree_tapbuf_size2_2 mux_right_track_16 ( .in ( { right_bottom_grid_pin_37_[0] , chany_bottom_in[20] } ) , .sram ( mux_tree_tapbuf_size2_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) , .out ( chanx_right_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_93 ) ) ; + .p0 ( optlc_net_88 ) ) ; sb_0__2__mux_tree_tapbuf_size2_3 mux_right_track_18 ( .in ( { right_bottom_grid_pin_38_[0] , chany_bottom_in[19] } ) , .sram ( mux_tree_tapbuf_size2_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 } ) , .out ( chanx_right_out[9] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_91 ) ) ; + .p0 ( optlc_net_89 ) ) ; sb_0__2__mux_tree_tapbuf_size2_4 mux_right_track_20 ( .in ( { right_bottom_grid_pin_39_[0] , chany_bottom_in[18] } ) , .sram ( mux_tree_tapbuf_size2_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) , .out ( chanx_right_out[10] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_93 ) ) ; + .p0 ( optlc_net_88 ) ) ; sb_0__2__mux_tree_tapbuf_size2_5 mux_right_track_22 ( .in ( { right_bottom_grid_pin_40_[0] , chany_bottom_in[17] } ) , .sram ( mux_tree_tapbuf_size2_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 } ) , .out ( chanx_right_out[11] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_93 ) ) ; + .p0 ( optlc_net_88 ) ) ; sb_0__2__mux_tree_tapbuf_size2_6 mux_right_track_24 ( .in ( { right_bottom_grid_pin_41_[0] , chany_bottom_in[16] } ) , .sram ( mux_tree_tapbuf_size2_6_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) , .out ( chanx_right_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_93 ) ) ; + .p0 ( optlc_net_88 ) ) ; sb_0__2__mux_tree_tapbuf_size2_7 mux_right_track_26 ( .in ( { right_bottom_grid_pin_42_[0] , chany_bottom_in[15] } ) , .sram ( mux_tree_tapbuf_size2_7_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 } ) , .out ( chanx_right_out[13] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_93 ) ) ; + .p0 ( optlc_net_88 ) ) ; sb_0__2__mux_tree_tapbuf_size2_8 mux_right_track_30 ( .in ( { right_bottom_grid_pin_36_[0] , chany_bottom_in[13] } ) , .sram ( mux_tree_tapbuf_size2_8_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) , .out ( chanx_right_out[15] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_90 ) ) ; + .p0 ( optlc_net_88 ) ) ; sb_0__2__mux_tree_tapbuf_size2_9 mux_right_track_32 ( .in ( { right_bottom_grid_pin_37_[0] , chany_bottom_in[12] } ) , .sram ( mux_tree_tapbuf_size2_9_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 } ) , .out ( chanx_right_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_93 ) ) ; + .p0 ( optlc_net_89 ) ) ; sb_0__2__mux_tree_tapbuf_size2_10 mux_right_track_34 ( .in ( { right_bottom_grid_pin_38_[0] , chany_bottom_in[11] } ) , .sram ( mux_tree_tapbuf_size2_10_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) , .out ( chanx_right_out[17] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_91 ) ) ; + .p0 ( optlc_net_89 ) ) ; sb_0__2__mux_tree_tapbuf_size2_11 mux_right_track_36 ( .in ( { right_bottom_grid_pin_39_[0] , chany_bottom_in[10] } ) , .sram ( mux_tree_tapbuf_size2_11_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 } ) , .out ( chanx_right_out[18] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_93 ) ) ; + .p0 ( optlc_net_88 ) ) ; sb_0__2__mux_tree_tapbuf_size2_12 mux_right_track_38 ( .in ( { right_bottom_grid_pin_40_[0] , chany_bottom_in[9] } ) , .sram ( mux_tree_tapbuf_size2_12_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) , .out ( chanx_right_out[19] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_93 ) ) ; + .p0 ( optlc_net_88 ) ) ; sb_0__2__mux_tree_tapbuf_size2_13 mux_right_track_40 ( .in ( { right_bottom_grid_pin_41_[0] , chany_bottom_in[8] } ) , .sram ( mux_tree_tapbuf_size2_13_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 } ) , .out ( chanx_right_out[20] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_93 ) ) ; + .p0 ( optlc_net_88 ) ) ; sb_0__2__mux_tree_tapbuf_size2_14 mux_right_track_42 ( .in ( { right_bottom_grid_pin_42_[0] , chany_bottom_in[7] } ) , .sram ( mux_tree_tapbuf_size2_14_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) , .out ( chanx_right_out[21] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_90 ) ) ; + .p0 ( optlc_net_88 ) ) ; sb_0__2__mux_tree_tapbuf_size2_15 mux_right_track_44 ( .in ( { right_top_grid_pin_1_[0] , chany_bottom_in[6] } ) , .sram ( mux_tree_tapbuf_size2_15_sram ) , @@ -39241,31 +39219,31 @@ sb_0__2__mux_tree_tapbuf_size2_17 mux_right_track_48 ( .sram ( mux_tree_tapbuf_size2_17_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 } ) , .out ( chanx_right_out[24] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_92 ) ) ; + .p0 ( optlc_net_90 ) ) ; sb_0__2__mux_tree_tapbuf_size2_18 mux_right_track_50 ( .in ( { right_bottom_grid_pin_38_[0] , chany_bottom_in[3] } ) , .sram ( mux_tree_tapbuf_size2_18_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) , .out ( chanx_right_out[25] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_92 ) ) ; + .p0 ( optlc_net_90 ) ) ; sb_0__2__mux_tree_tapbuf_size2_19 mux_right_track_54 ( .in ( { right_bottom_grid_pin_40_[0] , chany_bottom_in[1] } ) , .sram ( mux_tree_tapbuf_size2_19_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 } ) , .out ( chanx_right_out[27] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_92 ) ) ; + .p0 ( optlc_net_90 ) ) ; sb_0__2__mux_tree_tapbuf_size2_20 mux_right_track_56 ( .in ( { right_bottom_grid_pin_41_[0] , chany_bottom_in[0] } ) , .sram ( mux_tree_tapbuf_size2_20_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) , .out ( chanx_right_out[28] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_93 ) ) ; + .p0 ( optlc_net_88 ) ) ; sb_0__2__mux_tree_tapbuf_size2_21 mux_right_track_58 ( .in ( { right_bottom_grid_pin_42_[0] , chany_bottom_in[29] } ) , .sram ( mux_tree_tapbuf_size2_21_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 } ) , .out ( chanx_right_out[29] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_93 ) ) ; + .p0 ( optlc_net_88 ) ) ; sb_0__2__mux_tree_tapbuf_size2_22 mux_bottom_track_1 ( .in ( { chanx_right_in[28] , bottom_left_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size2_22_sram ) , @@ -39283,19 +39261,19 @@ sb_0__2__mux_tree_tapbuf_size2_24 mux_bottom_track_13 ( .sram ( mux_tree_tapbuf_size2_24_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 } ) , .out ( chany_bottom_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_91 ) ) ; + .p0 ( optlc_net_89 ) ) ; sb_0__2__mux_tree_tapbuf_size2_25 mux_bottom_track_29 ( .in ( { chanx_right_in[14] , bottom_left_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size2_25_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_69 , SYNOPSYS_UNCONNECTED_70 } ) , .out ( chany_bottom_out[14] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_91 ) ) ; + .p0 ( optlc_net_89 ) ) ; sb_0__2__mux_tree_tapbuf_size2 mux_bottom_track_45 ( .in ( { chanx_right_in[6] , bottom_left_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size2_26_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_71 , SYNOPSYS_UNCONNECTED_72 } ) , .out ( chany_bottom_out[22] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_91 ) ) ; + .p0 ( optlc_net_89 ) ) ; sb_0__2__mux_tree_tapbuf_size2_mem_0 mem_right_track_12 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) , @@ -39444,7 +39422,7 @@ sb_0__2__mux_tree_tapbuf_size3 mux_right_track_52 ( .sram ( mux_tree_tapbuf_size3_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_75 , SYNOPSYS_UNCONNECTED_76 } ) , .out ( chanx_right_out[26] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_92 ) ) ; + .p0 ( optlc_net_90 ) ) ; sb_0__2__mux_tree_tapbuf_size3_mem_0 mem_right_track_28 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , @@ -39457,8 +39435,8 @@ sb_0__2__mux_tree_tapbuf_size3_mem mem_right_track_52 ( .pReset ( pReset ) , .mem_out ( mux_tree_tapbuf_size3_1_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_E_in ) , .X ( pReset[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 pReset_S_FTB01 ( .A ( pReset_E_in ) , - .X ( pReset_S_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_90 ( .LO ( SYNOPSYS_UNCONNECTED_77 ) , + .HI ( optlc_net_88 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_E_in ) , .X ( prog_clk[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_36__35 ( .A ( chanx_right_in[0] ) , @@ -39467,33 +39445,33 @@ sky130_fd_sc_hd__buf_8 FTB_37__36 ( .A ( chanx_right_in[1] ) , .X ( chany_bottom_out[27] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_38__37 ( .A ( chanx_right_in[2] ) , .X ( chany_bottom_out[26] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 FTB_39__38 ( .A ( chanx_right_in[3] ) , - .X ( ropt_net_129 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chanx_right_in[3] ) , + .X ( chany_bottom_out[25] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_6 FTB_40__39 ( .A ( chanx_right_in[4] ) , - .X ( ropt_net_127 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .X ( ropt_net_129 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_41__40 ( .A ( chanx_right_in[5] ) , .X ( chany_bottom_out[23] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_42__41 ( .A ( chanx_right_in[7] ) , .X ( chany_bottom_out[21] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 FTB_43__42 ( .A ( chanx_right_in[8] ) , - .X ( ropt_net_137 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_43__42 ( .A ( chanx_right_in[8] ) , + .X ( chany_bottom_out[20] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_44__43 ( .A ( chanx_right_in[9] ) , .X ( chany_bottom_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_45__44 ( .A ( chanx_right_in[10] ) , .X ( chany_bottom_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 FTB_46__45 ( .A ( chanx_right_in[11] ) , - .X ( ropt_net_128 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 FTB_47__46 ( .A ( chanx_right_in[12] ) , - .X ( chany_bottom_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_46__45 ( .A ( chanx_right_in[11] ) , + .X ( chany_bottom_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_47__46 ( .A ( chanx_right_in[12] ) , + .X ( ropt_net_130 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_48__47 ( .A ( chanx_right_in[13] ) , .X ( chany_bottom_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 FTB_49__48 ( .A ( chanx_right_in[15] ) , - .X ( chany_bottom_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_49__48 ( .A ( chanx_right_in[15] ) , + .X ( ropt_net_131 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_50__49 ( .A ( chanx_right_in[16] ) , .X ( chany_bottom_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_51__50 ( .A ( chanx_right_in[17] ) , .X ( chany_bottom_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 FTB_52__51 ( .A ( chanx_right_in[18] ) , +sky130_fd_sc_hd__buf_8 FTB_52__51 ( .A ( chanx_right_in[18] ) , .X ( chany_bottom_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_53__52 ( .A ( chanx_right_in[19] ) , .X ( chany_bottom_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -39504,7 +39482,7 @@ sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chanx_right_in[21] ) , sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chanx_right_in[23] ) , .X ( chany_bottom_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_6 FTB_57__56 ( .A ( chanx_right_in[24] ) , - .X ( ropt_net_134 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .X ( ropt_net_128 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chanx_right_in[26] ) , .X ( chany_bottom_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( chanx_right_in[27] ) , @@ -39513,24 +39491,22 @@ sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( chanx_right_in[29] ) , .X ( chany_bottom_out[29] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_6 FTB_61__60 ( .A ( SC_IN_TOP ) , .X ( SC_OUT_BOT ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_92 ( .LO ( SYNOPSYS_UNCONNECTED_77 ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_85 ( .A ( pReset_E_in ) , .X ( pReset_S_out ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_92 ( .LO ( SYNOPSYS_UNCONNECTED_78 ) , + .HI ( optlc_net_89 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_94 ( .LO ( SYNOPSYS_UNCONNECTED_79 ) , .HI ( optlc_net_90 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_94 ( .LO ( SYNOPSYS_UNCONNECTED_78 ) , +sky130_fd_sc_hd__conb_1 optlc_96 ( .LO ( SYNOPSYS_UNCONNECTED_80 ) , .HI ( optlc_net_91 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_96 ( .LO ( SYNOPSYS_UNCONNECTED_79 ) , - .HI ( optlc_net_92 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_98 ( .LO ( SYNOPSYS_UNCONNECTED_80 ) , - .HI ( optlc_net_93 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1293 ( .A ( ropt_net_127 ) , - .X ( chany_bottom_out[24] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1294 ( .A ( ropt_net_128 ) , - .X ( chany_bottom_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1295 ( .A ( ropt_net_129 ) , - .X ( chany_bottom_out[25] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1300 ( .A ( ropt_net_134 ) , +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1293 ( .A ( ropt_net_128 ) , .X ( chany_bottom_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1303 ( .A ( ropt_net_137 ) , - .X ( chany_bottom_out[20] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1294 ( .A ( ropt_net_129 ) , + .X ( chany_bottom_out[24] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1295 ( .A ( ropt_net_130 ) , + .X ( chany_bottom_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1296 ( .A ( ropt_net_131 ) , + .X ( chany_bottom_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -39747,10 +39723,10 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_147 ( .A ( BUF_net_148 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_141 ( .A ( BUF_net_142 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_148 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_148 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_142 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_142 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -39769,15 +39745,16 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_139 ( .A ( BUF_net_140 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_140 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_140 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -39796,15 +39773,16 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_137 ( .A ( BUF_net_138 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_138 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_138 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -39850,16 +39828,15 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_145 ( .A ( BUF_net_146 ) , .Y ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_146 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_146 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -39878,14 +39855,15 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_144 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -39904,14 +39882,15 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_143 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -39936,10 +39915,10 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_141 ( .A ( BUF_net_142 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_135 ( .A ( BUF_net_136 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_142 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_142 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_136 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_136 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -39953,7 +39932,7 @@ output [0:1] mem_out ; input VDD ; input VSS ; -wire copt_net_164 ; +wire copt_net_160 ; supply1 VDD ; supply0 VSS ; @@ -39961,11 +39940,11 @@ sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( copt_net_164 ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( copt_net_160 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 FTB_42__41 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , +sky130_fd_sc_hd__buf_6 FTB_42__41 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1334 ( .A ( copt_net_164 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1336 ( .A ( copt_net_160 ) , .X ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -40212,7 +40191,7 @@ sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_140 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_134 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -40239,12 +40218,14 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_139 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_132 ( .A ( BUF_net_133 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_133 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .Y ( BUF_net_133 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -40274,7 +40255,7 @@ sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_138 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_131 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -40295,168 +40276,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size3_5 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_136 ( .A ( BUF_net_137 ) , .Y ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_137 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .Y ( BUF_net_137 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size3_4 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_134 ( .A ( BUF_net_135 ) , .Y ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_135 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .Y ( BUF_net_135 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size3_3 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_133 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size3_2 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_131 ( .A ( BUF_net_132 ) , .Y ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_132 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .Y ( BUF_net_132 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size3_1 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -supply1 VDD ; -supply0 VSS ; - sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -40474,7 +40293,39 @@ sky130_fd_sc_hd__inv_1 BINV_R_130 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , endmodule -module sb_0__1__mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , VDD , +module sb_0__1__mux_tree_tapbuf_size3_5 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size3_4 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; input [0:2] in ; input [0:1] sram ; @@ -40507,6 +40358,136 @@ sky130_fd_sc_hd__inv_1 BINV_R_128 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , endmodule +module sb_0__1__mux_tree_tapbuf_size3_3 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size3_2 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_125 ( .A ( BUF_net_126 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_126 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .Y ( BUF_net_126 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size3_1 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_123 ( .A ( BUF_net_124 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_124 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .Y ( BUF_net_124 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + module sb_0__1__mux_tree_tapbuf_size4_mem ( pReset , prog_clk , ccff_head , ccff_tail , mem_out , VDD , VSS ) ; input [0:0] pReset ; @@ -40848,6 +40829,9 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -40861,8 +40845,6 @@ sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_126 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -40892,14 +40874,12 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_124 ( .A ( BUF_net_125 ) , .Y ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_125 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .Y ( BUF_net_125 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_122 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -40929,12 +40909,14 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_123 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_120 ( .A ( BUF_net_121 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_121 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_121 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -40955,9 +40937,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -40967,10 +40946,14 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_118 ( .A ( BUF_net_119 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_119 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_119 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -40991,9 +40974,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -41007,6 +40987,8 @@ sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_117 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -41040,10 +41022,10 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_121 ( .A ( BUF_net_122 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_115 ( .A ( BUF_net_116 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_122 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .Y ( BUF_net_122 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_116 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_116 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -41113,7 +41095,7 @@ sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_120 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_114 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -41148,10 +41130,10 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_118 ( .A ( BUF_net_119 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_112 ( .A ( BUF_net_113 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_119 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .Y ( BUF_net_119 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_113 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_113 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -41185,10 +41167,10 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_116 ( .A ( BUF_net_117 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_110 ( .A ( BUF_net_111 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_117 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .Y ( BUF_net_117 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_111 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_111 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -41222,10 +41204,10 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_114 ( .A ( BUF_net_115 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_108 ( .A ( BUF_net_109 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_115 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .Y ( BUF_net_115 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_109 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_109 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -41246,6 +41228,9 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -41259,10 +41244,6 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_112 ( .A ( BUF_net_113 ) , .Y ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_113 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .Y ( BUF_net_113 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -41625,10 +41606,10 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_110 ( .A ( BUF_net_111 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_106 ( .A ( BUF_net_107 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_111 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .Y ( BUF_net_111 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_107 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .Y ( BUF_net_107 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -41650,6 +41631,9 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -41667,8 +41651,6 @@ sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_109 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -41707,10 +41689,10 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_107 ( .A ( BUF_net_108 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_104 ( .A ( BUF_net_105 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_108 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .Y ( BUF_net_108 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_105 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .Y ( BUF_net_105 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -41749,7 +41731,7 @@ sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_106 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_103 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -41830,10 +41812,10 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_104 ( .A ( BUF_net_105 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_101 ( .A ( BUF_net_102 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_105 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .Y ( BUF_net_105 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_102 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .Y ( BUF_net_102 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -41872,10 +41854,10 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_102 ( .A ( BUF_net_103 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_99 ( .A ( BUF_net_100 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_103 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .Y ( BUF_net_103 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_100 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .Y ( BUF_net_100 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -41955,10 +41937,10 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_100 ( .A ( BUF_net_101 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_97 ( .A ( BUF_net_98 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_101 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .Y ( BUF_net_101 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_98 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .Y ( BUF_net_98 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -41980,6 +41962,9 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -41997,10 +41982,6 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_98 ( .A ( BUF_net_99 ) , .Y ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_99 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .Y ( BUF_net_99 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -42288,7 +42269,7 @@ input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_181 ) , +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_168 ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , @@ -42299,28 +42280,32 @@ sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1325 ( .A ( ccff_head[0] ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1326 ( .A ( ropt_net_172 ) , + .X ( copt_net_149 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1327 ( .A ( copt_net_149 ) , + .X ( copt_net_150 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1328 ( .A ( ropt_net_170 ) , + .X ( copt_net_151 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1329 ( .A ( copt_net_153 ) , + .X ( copt_net_152 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1330 ( .A ( copt_net_150 ) , .X ( copt_net_153 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1326 ( .A ( copt_net_153 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1331 ( .A ( ccff_head[0] ) , .X ( copt_net_154 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1327 ( .A ( copt_net_154 ) , - .X ( copt_net_155 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1328 ( .A ( copt_net_155 ) , - .X ( copt_net_156 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1329 ( .A ( copt_net_156 ) , - .X ( copt_net_157 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1330 ( .A ( copt_net_157 ) , - .X ( copt_net_158 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1347 ( .A ( copt_net_158 ) , - .X ( ropt_net_177 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1348 ( .A ( ropt_net_177 ) , - .X ( ropt_net_178 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1349 ( .A ( ropt_net_178 ) , - .X ( ropt_net_179 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1350 ( .A ( ropt_net_179 ) , - .X ( ropt_net_180 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1351 ( .A ( ropt_net_180 ) , - .X ( ropt_net_181 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1340 ( .A ( copt_net_151 ) , + .X ( ropt_net_166 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1341 ( .A ( ropt_net_166 ) , + .X ( ropt_net_167 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_2 ropt_h_inst_1342 ( .A ( ropt_net_167 ) , + .X ( ropt_net_168 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1343 ( .A ( copt_net_152 ) , + .X ( ropt_net_169 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1344 ( .A ( ropt_net_171 ) , + .X ( ropt_net_170 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_4 ropt_h_inst_1345 ( .A ( ropt_net_169 ) , + .X ( ropt_net_171 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 ropt_h_inst_1346 ( .A ( copt_net_154 ) , + .X ( ropt_net_172 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -42433,6 +42418,9 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -42449,12 +42437,10 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_97 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -42569,51 +42555,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size6_1 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:5] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -supply1 VDD ; -supply0 VSS ; - sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -42641,6 +42582,51 @@ sky130_fd_sc_hd__inv_1 BINV_R_92 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , endmodule +module sb_0__1__mux_tree_tapbuf_size6_1 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + module sb_0__1__mux_tree_tapbuf_size6_0 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; input [0:5] in ; @@ -42720,7 +42706,6 @@ input prog_clk_0_E_in ; input VDD ; input VSS ; -wire ropt_net_168 ; wire [0:0] prog_clk ; wire prog_clk_0 ; wire [0:1] mux_tree_tapbuf_size2_0_sram ; @@ -42834,7 +42819,7 @@ sb_0__1__mux_tree_tapbuf_size6_0 mux_top_track_0 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 } ) , .out ( chany_top_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_151 ) ) ; + .p0 ( optlc_net_148 ) ) ; sb_0__1__mux_tree_tapbuf_size6_1 mux_top_track_6 ( .in ( { top_left_grid_pin_1_[0] , chanx_right_in[4] , chanx_right_in[15] , chanx_right_in[26] , chany_top_out[9] , chany_top_out[24] } ) , @@ -42842,7 +42827,7 @@ sb_0__1__mux_tree_tapbuf_size6_1 mux_top_track_6 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 } ) , .out ( chany_top_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_152 ) ) ; + .p0 ( optlc_net_146 ) ) ; sb_0__1__mux_tree_tapbuf_size6_2 mux_top_track_12 ( .in ( { top_left_grid_pin_1_[0] , chanx_right_in[6] , chanx_right_in[17] , chanx_right_in[28] , chany_top_out[12] , chany_top_out[27] } ) , @@ -42850,7 +42835,7 @@ sb_0__1__mux_tree_tapbuf_size6_2 mux_top_track_12 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 , SYNOPSYS_UNCONNECTED_9 } ) , .out ( chany_top_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_152 ) ) ; + .p0 ( optlc_net_146 ) ) ; sb_0__1__mux_tree_tapbuf_size6_3 mux_right_track_2 ( .in ( { chany_top_in[0] , chany_bottom_out[7] , right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_40_[0] , @@ -42859,7 +42844,7 @@ sb_0__1__mux_tree_tapbuf_size6_3 mux_right_track_2 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , .out ( chanx_right_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_149 ) ) ; + .p0 ( optlc_net_147 ) ) ; sb_0__1__mux_tree_tapbuf_size6_4 mux_right_track_6 ( .in ( { chany_top_in[2] , chany_bottom_out[9] , right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_39_[0] , @@ -42868,7 +42853,7 @@ sb_0__1__mux_tree_tapbuf_size6_4 mux_right_track_6 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , SYNOPSYS_UNCONNECTED_15 } ) , .out ( chanx_right_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_151 ) ) ; + .p0 ( optlc_net_144 ) ) ; sb_0__1__mux_tree_tapbuf_size6_5 mux_right_track_8 ( .in ( { chany_top_in[4] , chany_bottom_out[11] , right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_40_[0] , @@ -42877,7 +42862,7 @@ sb_0__1__mux_tree_tapbuf_size6_5 mux_right_track_8 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_16 , SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 } ) , .out ( chanx_right_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_149 ) ) ; + .p0 ( optlc_net_147 ) ) ; sb_0__1__mux_tree_tapbuf_size6_6 mux_bottom_track_7 ( .in ( { chany_bottom_out[9] , chany_bottom_out[24] , chanx_right_in[6] , chanx_right_in[17] , chanx_right_in[28] , bottom_left_grid_pin_1_[0] } ) , @@ -42885,7 +42870,7 @@ sb_0__1__mux_tree_tapbuf_size6_6 mux_bottom_track_7 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 , SYNOPSYS_UNCONNECTED_21 } ) , .out ( chany_bottom_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_152 ) ) ; + .p0 ( optlc_net_145 ) ) ; sb_0__1__mux_tree_tapbuf_size6 mux_bottom_track_13 ( .in ( { chany_bottom_out[12] , chany_bottom_out[27] , chanx_right_in[4] , chanx_right_in[15] , chanx_right_in[26] , bottom_left_grid_pin_1_[0] } ) , @@ -42893,7 +42878,7 @@ sb_0__1__mux_tree_tapbuf_size6 mux_bottom_track_13 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_22 , SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) , .out ( chany_bottom_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_152 ) ) ; + .p0 ( optlc_net_145 ) ) ; sb_0__1__mux_tree_tapbuf_size6_mem_0 mem_top_track_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , @@ -42940,15 +42925,15 @@ sb_0__1__mux_tree_tapbuf_size5_0 mux_top_track_2 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , SYNOPSYS_UNCONNECTED_27 } ) , .out ( chany_top_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_151 ) ) ; + .p0 ( optlc_net_148 ) ) ; sb_0__1__mux_tree_tapbuf_size5_1 mux_top_track_4 ( .in ( { chanx_right_in[3] , chanx_right_in[14] , chanx_right_in[25] , - chany_top_out[8] , ropt_net_168 } ) , + chany_top_out[8] , chany_top_out[23] } ) , .sram ( mux_tree_tapbuf_size5_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_28 , SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 } ) , .out ( chany_top_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_152 ) ) ; + .p0 ( optlc_net_146 ) ) ; sb_0__1__mux_tree_tapbuf_size5_2 mux_top_track_10 ( .in ( { chanx_right_in[5] , chanx_right_in[16] , chanx_right_in[27] , chany_top_out[11] , chany_top_out[25] } ) , @@ -42956,7 +42941,7 @@ sb_0__1__mux_tree_tapbuf_size5_2 mux_top_track_10 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 , SYNOPSYS_UNCONNECTED_33 } ) , .out ( chany_top_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_152 ) ) ; + .p0 ( optlc_net_146 ) ) ; sb_0__1__mux_tree_tapbuf_size5_3 mux_top_track_20 ( .in ( { chanx_right_in[7] , chanx_right_in[18] , chanx_right_in[29] , chany_top_out[13] , chany_top_out[28] } ) , @@ -42964,7 +42949,7 @@ sb_0__1__mux_tree_tapbuf_size5_3 mux_top_track_20 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_34 , SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) , .out ( chany_top_out[10] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_152 ) ) ; + .p0 ( optlc_net_148 ) ) ; sb_0__1__mux_tree_tapbuf_size5_4 mux_right_track_0 ( .in ( { chany_bottom_out[4] , right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_39_[0] , right_bottom_grid_pin_42_[0] , @@ -42973,7 +42958,7 @@ sb_0__1__mux_tree_tapbuf_size5_4 mux_right_track_0 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 , SYNOPSYS_UNCONNECTED_39 } ) , .out ( chanx_right_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_151 ) ) ; + .p0 ( optlc_net_148 ) ) ; sb_0__1__mux_tree_tapbuf_size5_5 mux_right_track_4 ( .in ( { chany_top_in[1] , chany_bottom_out[8] , right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_41_[0] , @@ -42982,7 +42967,7 @@ sb_0__1__mux_tree_tapbuf_size5_5 mux_right_track_4 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_40 , SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 } ) , .out ( chanx_right_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_151 ) ) ; + .p0 ( optlc_net_144 ) ) ; sb_0__1__mux_tree_tapbuf_size5_6 mux_right_track_10 ( .in ( { chany_top_in[5] , chany_bottom_out[12] , right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_41_[0] , @@ -42991,7 +42976,7 @@ sb_0__1__mux_tree_tapbuf_size5_6 mux_right_track_10 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 , SYNOPSYS_UNCONNECTED_45 } ) , .out ( chanx_right_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_149 ) ) ; + .p0 ( optlc_net_147 ) ) ; sb_0__1__mux_tree_tapbuf_size5_7 mux_bottom_track_1 ( .in ( { chany_bottom_out[4] , chany_bottom_out[20] , chanx_right_in[9] , chanx_right_in[20] , bottom_left_grid_pin_1_[0] } ) , @@ -42999,7 +42984,7 @@ sb_0__1__mux_tree_tapbuf_size5_7 mux_bottom_track_1 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_46 , SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) , .out ( chany_bottom_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_152 ) ) ; + .p0 ( optlc_net_145 ) ) ; sb_0__1__mux_tree_tapbuf_size5_8 mux_bottom_track_5 ( .in ( { chany_bottom_out[8] , chany_bottom_out[23] , chanx_right_in[7] , chanx_right_in[18] , chanx_right_in[29] } ) , @@ -43007,7 +42992,7 @@ sb_0__1__mux_tree_tapbuf_size5_8 mux_bottom_track_5 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 , SYNOPSYS_UNCONNECTED_51 } ) , .out ( chany_bottom_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_152 ) ) ; + .p0 ( optlc_net_145 ) ) ; sb_0__1__mux_tree_tapbuf_size5_9 mux_bottom_track_11 ( .in ( { chany_bottom_out[11] , chany_bottom_out[25] , chanx_right_in[5] , chanx_right_in[16] , chanx_right_in[27] } ) , @@ -43015,7 +43000,7 @@ sb_0__1__mux_tree_tapbuf_size5_9 mux_bottom_track_11 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_52 , SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 } ) , .out ( chany_bottom_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_152 ) ) ; + .p0 ( optlc_net_145 ) ) ; sb_0__1__mux_tree_tapbuf_size5_10 mux_bottom_track_21 ( .in ( { chany_bottom_out[13] , chany_bottom_out[28] , chanx_right_in[3] , chanx_right_in[14] , chanx_right_in[25] } ) , @@ -43023,7 +43008,7 @@ sb_0__1__mux_tree_tapbuf_size5_10 mux_bottom_track_21 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 , SYNOPSYS_UNCONNECTED_57 } ) , .out ( chany_bottom_out[10] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_150 ) ) ; + .p0 ( optlc_net_148 ) ) ; sb_0__1__mux_tree_tapbuf_size5 mux_bottom_track_29 ( .in ( { chany_bottom_out[15] , chany_bottom_out[29] , chanx_right_in[2] , chanx_right_in[13] , chanx_right_in[24] } ) , @@ -43031,7 +43016,7 @@ sb_0__1__mux_tree_tapbuf_size5 mux_bottom_track_29 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_58 , SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) , .out ( chany_bottom_out[14] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_150 ) ) ; + .p0 ( optlc_net_143 ) ) ; sb_0__1__mux_tree_tapbuf_size5_mem_0 mem_top_track_2 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , @@ -43099,7 +43084,7 @@ sb_0__1__mux_tree_tapbuf_size4_0 mux_top_track_28 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 , SYNOPSYS_UNCONNECTED_63 } ) , .out ( chany_top_out[14] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_151 ) ) ; + .p0 ( optlc_net_148 ) ) ; sb_0__1__mux_tree_tapbuf_size4_1 mux_top_track_52 ( .in ( { chanx_right_in[0] , chanx_right_in[11] , chanx_right_in[22] , chany_top_out[19] } ) , @@ -43107,7 +43092,7 @@ sb_0__1__mux_tree_tapbuf_size4_1 mux_top_track_52 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_64 , SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 } ) , .out ( chany_top_out[26] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_151 ) ) ; + .p0 ( optlc_net_148 ) ) ; sb_0__1__mux_tree_tapbuf_size4_2 mux_right_track_12 ( .in ( { chany_top_in[9] , chany_bottom_out[13] , right_bottom_grid_pin_36_[0] , chany_top_out[13] } ) , @@ -43115,7 +43100,7 @@ sb_0__1__mux_tree_tapbuf_size4_2 mux_right_track_12 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 , SYNOPSYS_UNCONNECTED_69 } ) , .out ( chanx_right_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_151 ) ) ; + .p0 ( optlc_net_147 ) ) ; sb_0__1__mux_tree_tapbuf_size4_3 mux_right_track_14 ( .in ( { chany_top_in[13] , chany_bottom_out[15] , right_bottom_grid_pin_37_[0] , chany_top_out[15] } ) , @@ -43123,7 +43108,7 @@ sb_0__1__mux_tree_tapbuf_size4_3 mux_right_track_14 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_70 , SYNOPSYS_UNCONNECTED_71 , SYNOPSYS_UNCONNECTED_72 } ) , .out ( chanx_right_out[7] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_151 ) ) ; + .p0 ( optlc_net_144 ) ) ; sb_0__1__mux_tree_tapbuf_size4_4 mux_right_track_16 ( .in ( { chany_bottom_out[16] , chany_top_in[17] , right_bottom_grid_pin_38_[0] , chany_top_out[16] } ) , @@ -43131,7 +43116,7 @@ sb_0__1__mux_tree_tapbuf_size4_4 mux_right_track_16 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_73 , SYNOPSYS_UNCONNECTED_74 , SYNOPSYS_UNCONNECTED_75 } ) , .out ( chanx_right_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_151 ) ) ; + .p0 ( optlc_net_144 ) ) ; sb_0__1__mux_tree_tapbuf_size4_5 mux_right_track_18 ( .in ( { chany_bottom_out[17] , chany_top_in[21] , right_bottom_grid_pin_39_[0] , chany_top_out[17] } ) , @@ -43139,7 +43124,7 @@ sb_0__1__mux_tree_tapbuf_size4_5 mux_right_track_18 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_76 , SYNOPSYS_UNCONNECTED_77 , SYNOPSYS_UNCONNECTED_78 } ) , .out ( chanx_right_out[9] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_151 ) ) ; + .p0 ( optlc_net_144 ) ) ; sb_0__1__mux_tree_tapbuf_size4_6 mux_right_track_20 ( .in ( { chany_bottom_out[19] , chany_top_in[25] , right_bottom_grid_pin_40_[0] , chany_top_out[19] } ) , @@ -43147,7 +43132,7 @@ sb_0__1__mux_tree_tapbuf_size4_6 mux_right_track_20 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_79 , SYNOPSYS_UNCONNECTED_80 , SYNOPSYS_UNCONNECTED_81 } ) , .out ( chanx_right_out[10] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_149 ) ) ; + .p0 ( optlc_net_146 ) ) ; sb_0__1__mux_tree_tapbuf_size4_7 mux_right_track_22 ( .in ( { chany_bottom_out[20] , chany_top_in[29] , right_bottom_grid_pin_41_[0] , chany_top_out[20] } ) , @@ -43155,7 +43140,7 @@ sb_0__1__mux_tree_tapbuf_size4_7 mux_right_track_22 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_82 , SYNOPSYS_UNCONNECTED_83 , SYNOPSYS_UNCONNECTED_84 } ) , .out ( chanx_right_out[11] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_149 ) ) ; + .p0 ( optlc_net_146 ) ) ; sb_0__1__mux_tree_tapbuf_size4_8 mux_right_track_36 ( .in ( { chany_bottom_out[29] , right_bottom_grid_pin_40_[0] , chany_top_out[29] , chany_bottom_in[29] } ) , @@ -43163,7 +43148,7 @@ sb_0__1__mux_tree_tapbuf_size4_8 mux_right_track_36 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_85 , SYNOPSYS_UNCONNECTED_86 , SYNOPSYS_UNCONNECTED_87 } ) , .out ( chanx_right_out[18] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_150 ) ) ; + .p0 ( optlc_net_143 ) ) ; sb_0__1__mux_tree_tapbuf_size4_9 mux_bottom_track_3 ( .in ( { chany_bottom_out[7] , chany_bottom_out[21] , chanx_right_in[8] , chanx_right_in[19] } ) , @@ -43171,7 +43156,7 @@ sb_0__1__mux_tree_tapbuf_size4_9 mux_bottom_track_3 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_88 , SYNOPSYS_UNCONNECTED_89 , SYNOPSYS_UNCONNECTED_90 } ) , .out ( chany_bottom_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_150 ) ) ; + .p0 ( optlc_net_143 ) ) ; sb_0__1__mux_tree_tapbuf_size4_10 mux_bottom_track_37 ( .in ( { chany_bottom_out[16] , chanx_right_in[1] , chanx_right_in[12] , chanx_right_in[23] } ) , @@ -43179,7 +43164,7 @@ sb_0__1__mux_tree_tapbuf_size4_10 mux_bottom_track_37 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_91 , SYNOPSYS_UNCONNECTED_92 , SYNOPSYS_UNCONNECTED_93 } ) , .out ( chany_bottom_out[18] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_150 ) ) ; + .p0 ( optlc_net_143 ) ) ; sb_0__1__mux_tree_tapbuf_size4 mux_bottom_track_45 ( .in ( { chany_bottom_out[17] , chanx_right_in[0] , chanx_right_in[11] , chanx_right_in[22] } ) , @@ -43187,7 +43172,7 @@ sb_0__1__mux_tree_tapbuf_size4 mux_bottom_track_45 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_94 , SYNOPSYS_UNCONNECTED_95 , SYNOPSYS_UNCONNECTED_96 } ) , .out ( chany_bottom_out[22] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_150 ) ) ; + .p0 ( optlc_net_144 ) ) ; sb_0__1__mux_tree_tapbuf_size4_mem_0 mem_top_track_28 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , @@ -43253,68 +43238,68 @@ sb_0__1__mux_tree_tapbuf_size3_0 mux_top_track_36 ( .sram ( mux_tree_tapbuf_size3_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_97 , SYNOPSYS_UNCONNECTED_98 } ) , .out ( chany_top_out[18] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_151 ) ) ; + .p0 ( optlc_net_144 ) ) ; sb_0__1__mux_tree_tapbuf_size3_1 mux_top_track_44 ( .in ( { chanx_right_in[10] , chanx_right_in[21] , chany_top_out[17] } ) , .sram ( mux_tree_tapbuf_size3_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_99 , SYNOPSYS_UNCONNECTED_100 } ) , .out ( chany_top_out[22] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_151 ) ) ; + .p0 ( optlc_net_144 ) ) ; sb_0__1__mux_tree_tapbuf_size3_2 mux_right_track_24 ( .in ( { chany_bottom_out[21] , right_bottom_grid_pin_42_[0] , chany_top_out[21] } ) , .sram ( mux_tree_tapbuf_size3_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_101 , SYNOPSYS_UNCONNECTED_102 } ) , .out ( chanx_right_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_149 ) ) ; + .p0 ( optlc_net_146 ) ) ; sb_0__1__mux_tree_tapbuf_size3_3 mux_right_track_26 ( .in ( { chany_bottom_out[23] , right_bottom_grid_pin_43_[0] , - ropt_net_168 } ) , + chany_top_out[23] } ) , .sram ( mux_tree_tapbuf_size3_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_103 , SYNOPSYS_UNCONNECTED_104 } ) , .out ( chanx_right_out[13] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_149 ) ) ; + .p0 ( optlc_net_147 ) ) ; sb_0__1__mux_tree_tapbuf_size3_4 mux_right_track_28 ( .in ( { chany_bottom_out[24] , right_bottom_grid_pin_36_[0] , chany_top_out[24] } ) , .sram ( mux_tree_tapbuf_size3_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_105 , SYNOPSYS_UNCONNECTED_106 } ) , .out ( chanx_right_out[14] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_149 ) ) ; + .p0 ( optlc_net_148 ) ) ; sb_0__1__mux_tree_tapbuf_size3_5 mux_right_track_30 ( .in ( { chany_bottom_out[25] , right_bottom_grid_pin_37_[0] , chany_top_out[25] } ) , .sram ( mux_tree_tapbuf_size3_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_107 , SYNOPSYS_UNCONNECTED_108 } ) , .out ( chanx_right_out[15] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_149 ) ) ; + .p0 ( optlc_net_148 ) ) ; sb_0__1__mux_tree_tapbuf_size3_6 mux_right_track_32 ( .in ( { chany_bottom_out[27] , right_bottom_grid_pin_38_[0] , chany_top_out[27] } ) , .sram ( mux_tree_tapbuf_size3_6_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_109 , SYNOPSYS_UNCONNECTED_110 } ) , .out ( chanx_right_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_151 ) ) ; + .p0 ( optlc_net_147 ) ) ; sb_0__1__mux_tree_tapbuf_size3_7 mux_right_track_34 ( .in ( { chany_bottom_out[28] , right_bottom_grid_pin_39_[0] , chany_top_out[28] } ) , .sram ( mux_tree_tapbuf_size3_7_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_111 , SYNOPSYS_UNCONNECTED_112 } ) , .out ( chanx_right_out[17] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_151 ) ) ; + .p0 ( optlc_net_144 ) ) ; sb_0__1__mux_tree_tapbuf_size3_8 mux_right_track_50 ( .in ( { right_bottom_grid_pin_39_[0] , right_bottom_grid_pin_43_[0] , chany_bottom_in[4] } ) , .sram ( mux_tree_tapbuf_size3_8_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_113 , SYNOPSYS_UNCONNECTED_114 } ) , .out ( chanx_right_out[25] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_150 ) ) ; + .p0 ( optlc_net_143 ) ) ; sb_0__1__mux_tree_tapbuf_size3 mux_bottom_track_53 ( .in ( { chany_bottom_out[19] , chanx_right_in[10] , chanx_right_in[21] } ) , .sram ( mux_tree_tapbuf_size3_9_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_115 , SYNOPSYS_UNCONNECTED_116 } ) , .out ( chany_bottom_out[26] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_150 ) ) ; + .p0 ( optlc_net_143 ) ) ; sb_0__1__mux_tree_tapbuf_size3_mem_0 mem_top_track_36 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , @@ -43370,49 +43355,49 @@ sb_0__1__mux_tree_tapbuf_size2_0 mux_right_track_38 ( .sram ( mux_tree_tapbuf_size2_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_117 , SYNOPSYS_UNCONNECTED_118 } ) , .out ( chanx_right_out[19] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_150 ) ) ; + .p0 ( optlc_net_143 ) ) ; sb_0__1__mux_tree_tapbuf_size2_1 mux_right_track_40 ( .in ( { right_bottom_grid_pin_42_[0] , chany_bottom_in[21] } ) , .sram ( mux_tree_tapbuf_size2_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_119 , SYNOPSYS_UNCONNECTED_120 } ) , .out ( chanx_right_out[20] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_150 ) ) ; + .p0 ( optlc_net_143 ) ) ; sb_0__1__mux_tree_tapbuf_size2_2 mux_right_track_44 ( .in ( { right_bottom_grid_pin_36_[0] , chany_bottom_in[13] } ) , .sram ( mux_tree_tapbuf_size2_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_121 , SYNOPSYS_UNCONNECTED_122 } ) , .out ( chanx_right_out[22] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_150 ) ) ; + .p0 ( optlc_net_143 ) ) ; sb_0__1__mux_tree_tapbuf_size2_3 mux_right_track_46 ( .in ( { right_bottom_grid_pin_37_[0] , chany_bottom_in[9] } ) , .sram ( mux_tree_tapbuf_size2_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_123 , SYNOPSYS_UNCONNECTED_124 } ) , .out ( chanx_right_out[23] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_150 ) ) ; + .p0 ( optlc_net_143 ) ) ; sb_0__1__mux_tree_tapbuf_size2_4 mux_right_track_48 ( .in ( { right_bottom_grid_pin_38_[0] , chany_bottom_in[5] } ) , .sram ( mux_tree_tapbuf_size2_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_125 , SYNOPSYS_UNCONNECTED_126 } ) , .out ( chanx_right_out[24] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_150 ) ) ; + .p0 ( optlc_net_143 ) ) ; sb_0__1__mux_tree_tapbuf_size2_5 mux_right_track_52 ( .in ( { right_bottom_grid_pin_40_[0] , chany_bottom_in[2] } ) , .sram ( mux_tree_tapbuf_size2_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_127 , SYNOPSYS_UNCONNECTED_128 } ) , .out ( chanx_right_out[26] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_150 ) ) ; + .p0 ( optlc_net_143 ) ) ; sb_0__1__mux_tree_tapbuf_size2_6 mux_right_track_54 ( .in ( { right_bottom_grid_pin_41_[0] , chany_bottom_in[1] } ) , .sram ( mux_tree_tapbuf_size2_6_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_129 , SYNOPSYS_UNCONNECTED_130 } ) , .out ( chanx_right_out[27] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_150 ) ) ; + .p0 ( optlc_net_143 ) ) ; sb_0__1__mux_tree_tapbuf_size2 mux_right_track_56 ( .in ( { right_bottom_grid_pin_42_[0] , chany_bottom_in[0] } ) , .sram ( mux_tree_tapbuf_size2_7_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_131 , SYNOPSYS_UNCONNECTED_132 } ) , .out ( chanx_right_out[28] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_150 ) ) ; + .p0 ( optlc_net_143 ) ) ; sb_0__1__mux_tree_tapbuf_size2_mem_0 mem_right_track_38 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_8_ccff_tail ) , @@ -43525,8 +43510,8 @@ sky130_fd_sc_hd__buf_8 FTB_82__81 ( .A ( chany_bottom_in[19] ) , .X ( chany_top_out[20] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_83__82 ( .A ( chany_bottom_in[20] ) , .X ( chany_top_out[21] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_1 FTB_84__83 ( .A ( chany_bottom_in[22] ) , - .X ( ropt_net_168 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_84__83 ( .A ( chany_bottom_in[22] ) , + .X ( chany_top_out[23] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_85__84 ( .A ( chany_bottom_in[23] ) , .X ( chany_top_out[24] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_86__85 ( .A ( chany_bottom_in[24] ) , @@ -43537,16 +43522,18 @@ sky130_fd_sc_hd__buf_8 FTB_88__87 ( .A ( chany_bottom_in[27] ) , .X ( chany_top_out[28] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_89__88 ( .A ( chany_bottom_in[28] ) , .X ( chany_top_out[29] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_151 ( .LO ( SYNOPSYS_UNCONNECTED_133 ) , - .HI ( optlc_net_149 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_153 ( .LO ( SYNOPSYS_UNCONNECTED_134 ) , - .HI ( optlc_net_150 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_155 ( .LO ( SYNOPSYS_UNCONNECTED_135 ) , - .HI ( optlc_net_151 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_157 ( .LO ( SYNOPSYS_UNCONNECTED_136 ) , - .HI ( optlc_net_152 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 ropt_mt_inst_1340 ( .A ( ropt_net_168 ) , - .X ( chany_top_out[23] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_146 ( .LO ( SYNOPSYS_UNCONNECTED_133 ) , + .HI ( optlc_net_143 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_148 ( .LO ( SYNOPSYS_UNCONNECTED_134 ) , + .HI ( optlc_net_144 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_151 ( .LO ( SYNOPSYS_UNCONNECTED_135 ) , + .HI ( optlc_net_145 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_154 ( .LO ( SYNOPSYS_UNCONNECTED_136 ) , + .HI ( optlc_net_146 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_156 ( .LO ( SYNOPSYS_UNCONNECTED_137 ) , + .HI ( optlc_net_147 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_158 ( .LO ( SYNOPSYS_UNCONNECTED_138 ) , + .HI ( optlc_net_148 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -43946,10 +43933,10 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_95 ( .A ( BUF_net_96 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_6 BINV_R_88 ( .A ( BUF_net_89 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_96 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .Y ( BUF_net_96 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_89 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_89 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -43983,10 +43970,10 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_93 ( .A ( BUF_net_94 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_6 BINV_R_86 ( .A ( BUF_net_87 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_94 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .Y ( BUF_net_94 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_87 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_87 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -44020,10 +44007,10 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_99 ( .A ( BUF_net_100 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_6 BINV_R_90 ( .A ( BUF_net_91 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_100 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .Y ( BUF_net_100 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_91 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_91 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -44057,10 +44044,10 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_91 ( .A ( BUF_net_92 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_6 BINV_R_84 ( .A ( BUF_net_85 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_92 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .Y ( BUF_net_92 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_85 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_85 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -44119,14 +44106,14 @@ sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 FTB_26__25 ( .A ( copt_net_116 ) , +sky130_fd_sc_hd__buf_8 FTB_26__25 ( .A ( copt_net_108 ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1278 ( .A ( mem_out[1] ) , - .X ( copt_net_114 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1279 ( .A ( copt_net_114 ) , - .X ( copt_net_115 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1280 ( .A ( copt_net_115 ) , - .X ( copt_net_116 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1272 ( .A ( mem_out[1] ) , + .X ( copt_net_106 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1273 ( .A ( copt_net_106 ) , + .X ( copt_net_107 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1274 ( .A ( copt_net_107 ) , + .X ( copt_net_108 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -44719,7 +44706,7 @@ input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_194 ) , +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_191 ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , @@ -44727,24 +44714,24 @@ sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1271 ( .A ( ccff_head[0] ) , - .X ( copt_net_107 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1272 ( .A ( copt_net_107 ) , - .X ( copt_net_108 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1273 ( .A ( copt_net_108 ) , - .X ( copt_net_109 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1274 ( .A ( copt_net_112 ) , - .X ( copt_net_110 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1275 ( .A ( copt_net_110 ) , - .X ( copt_net_111 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1276 ( .A ( copt_net_109 ) , - .X ( copt_net_112 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1356 ( .A ( copt_net_111 ) , - .X ( ropt_net_192 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1357 ( .A ( ropt_net_192 ) , - .X ( ropt_net_193 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 ropt_h_inst_1358 ( .A ( ropt_net_193 ) , - .X ( ropt_net_194 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1265 ( .A ( ccff_head[0] ) , + .X ( copt_net_99 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1266 ( .A ( copt_net_99 ) , + .X ( copt_net_100 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1267 ( .A ( copt_net_103 ) , + .X ( copt_net_101 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1268 ( .A ( copt_net_101 ) , + .X ( copt_net_102 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1269 ( .A ( copt_net_100 ) , + .X ( copt_net_103 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1270 ( .A ( copt_net_102 ) , + .X ( copt_net_104 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1355 ( .A ( copt_net_104 ) , + .X ( ropt_net_189 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1356 ( .A ( ropt_net_189 ) , + .X ( ropt_net_190 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1357 ( .A ( ropt_net_190 ) , + .X ( ropt_net_191 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -44793,13 +44780,11 @@ supply0 VSS ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_89 ( .A ( BUF_net_90 ) , .Y ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_90 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_90 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_83 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -44824,7 +44809,7 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_88 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_82 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -44871,16 +44856,15 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_86 ( .A ( BUF_net_87 ) , .Y ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_87 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_87 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -44902,13 +44886,11 @@ supply0 VSS ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_84 ( .A ( BUF_net_85 ) , .Y ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_85 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_85 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_81 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -44927,6 +44909,33 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_18 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -44939,32 +44948,6 @@ sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module sb_0__0__mux_tree_tapbuf_size2_18 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_83 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - module sb_0__0__mux_tree_tapbuf_size2_17 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; input [0:1] in ; @@ -44980,34 +44963,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , - .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_81 ( .A ( BUF_net_82 ) , .Y ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_82 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_82 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -endmodule - - -module sb_0__0__mux_tree_tapbuf_size2_16 ( in , sram , sram_inv , out , VDD , - VSS , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input VDD ; -input VSS ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -supply1 VDD ; -supply0 VSS ; - sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -45021,6 +44976,34 @@ sky130_fd_sc_hd__inv_2 BINV_R_80 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , endmodule +module sb_0__0__mux_tree_tapbuf_size2_16 ( in , sram , sram_inv , out , VDD , + VSS , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input VDD ; +input VSS ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +supply1 VDD ; +supply0 VSS ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_77 ( .A ( BUF_net_78 ) , .Y ( out[0] ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_78 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_78 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +endmodule + + module sb_0__0__mux_tree_tapbuf_size2_15 ( in , sram , sram_inv , out , VDD , VSS , p0 ) ; input [0:1] in ; @@ -45096,10 +45079,10 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_77 ( .A ( BUF_net_78 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_6 BINV_R_75 ( .A ( BUF_net_76 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_78 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_78 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_76 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_76 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -45124,7 +45107,7 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_76 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_74 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -45147,13 +45130,11 @@ supply0 VSS ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_74 ( .A ( BUF_net_75 ) , .Y ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_75 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_75 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_73 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -45205,9 +45186,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_73 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_73 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_101 ( .A ( BUF_net_73 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_2 BINV_R_72 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_72 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_92 ( .A ( BUF_net_72 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -45233,10 +45214,8 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_97 ( .A ( BUF_net_98 ) , .Y ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_98 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_98 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_70 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -45282,16 +45261,15 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; supply1 VDD ; supply0 VSS ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) , + .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_70 ( .A ( BUF_net_71 ) , .Y ( out[0] ) , - .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_71 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_71 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -45491,8 +45469,10 @@ input prog_clk_0_E_in ; input VDD ; input VSS ; -wire ropt_net_139 ; -wire ropt_net_140 ; +wire ropt_net_141 ; +wire ropt_net_133 ; +wire ropt_net_134 ; +wire ropt_net_135 ; wire [0:0] prog_clk ; wire prog_clk_0 ; wire [0:1] mux_tree_tapbuf_size2_0_sram ; @@ -45574,157 +45554,157 @@ sb_0__0__mux_tree_tapbuf_size2_0 mux_top_track_0 ( .sram ( mux_tree_tapbuf_size2_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 } ) , .out ( chany_top_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_105 ) ) ; + .p0 ( optlc_net_95 ) ) ; sb_0__0__mux_tree_tapbuf_size2_1 mux_top_track_6 ( .in ( { top_left_grid_pin_1_[0] , chanx_right_in[4] } ) , .sram ( mux_tree_tapbuf_size2_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , .out ( chany_top_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_105 ) ) ; + .p0 ( optlc_net_95 ) ) ; sb_0__0__mux_tree_tapbuf_size2_2 mux_top_track_12 ( .in ( { top_left_grid_pin_1_[0] , chanx_right_in[7] } ) , .sram ( mux_tree_tapbuf_size2_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 } ) , .out ( chany_top_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_105 ) ) ; + .p0 ( optlc_net_95 ) ) ; sb_0__0__mux_tree_tapbuf_size2_3 mux_top_track_28 ( .in ( { top_left_grid_pin_1_[0] , chanx_right_in[15] } ) , .sram ( mux_tree_tapbuf_size2_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) , .out ( chany_top_out[14] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_105 ) ) ; + .p0 ( optlc_net_95 ) ) ; sb_0__0__mux_tree_tapbuf_size2_4 mux_top_track_44 ( .in ( { top_left_grid_pin_1_[0] , chanx_right_in[23] } ) , .sram ( mux_tree_tapbuf_size2_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 } ) , .out ( chany_top_out[22] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_105 ) ) ; + .p0 ( optlc_net_95 ) ) ; sb_0__0__mux_tree_tapbuf_size2_5 mux_right_track_14 ( .in ( { chany_top_in[6] , right_bottom_grid_pin_3_[0] } ) , .sram ( mux_tree_tapbuf_size2_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , .out ( chanx_right_out[7] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_105 ) ) ; + .p0 ( optlc_net_95 ) ) ; sb_0__0__mux_tree_tapbuf_size2_6 mux_right_track_16 ( .in ( { chany_top_in[7] , right_bottom_grid_pin_5_[0] } ) , .sram ( mux_tree_tapbuf_size2_6_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 } ) , .out ( chanx_right_out[8] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_106 ) ) ; + .p0 ( optlc_net_94 ) ) ; sb_0__0__mux_tree_tapbuf_size2_7 mux_right_track_18 ( .in ( { chany_top_in[8] , right_bottom_grid_pin_7_[0] } ) , .sram ( mux_tree_tapbuf_size2_7_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) , .out ( chanx_right_out[9] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_106 ) ) ; + .p0 ( optlc_net_94 ) ) ; sb_0__0__mux_tree_tapbuf_size2_8 mux_right_track_20 ( .in ( { chany_top_in[9] , right_bottom_grid_pin_9_[0] } ) , .sram ( mux_tree_tapbuf_size2_8_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 } ) , .out ( chanx_right_out[10] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_106 ) ) ; + .p0 ( optlc_net_96 ) ) ; sb_0__0__mux_tree_tapbuf_size2_9 mux_right_track_22 ( .in ( { chany_top_in[10] , right_bottom_grid_pin_11_[0] } ) , .sram ( mux_tree_tapbuf_size2_9_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) , .out ( chanx_right_out[11] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_106 ) ) ; + .p0 ( optlc_net_96 ) ) ; sb_0__0__mux_tree_tapbuf_size2_10 mux_right_track_24 ( .in ( { chany_top_in[11] , right_bottom_grid_pin_13_[0] } ) , .sram ( mux_tree_tapbuf_size2_10_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 } ) , .out ( chanx_right_out[12] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_103 ) ) ; + .p0 ( optlc_net_96 ) ) ; sb_0__0__mux_tree_tapbuf_size2_11 mux_right_track_26 ( .in ( { chany_top_in[12] , right_bottom_grid_pin_15_[0] } ) , .sram ( mux_tree_tapbuf_size2_11_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) , .out ( chanx_right_out[13] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_103 ) ) ; + .p0 ( optlc_net_94 ) ) ; sb_0__0__mux_tree_tapbuf_size2_12 mux_right_track_30 ( .in ( { chany_top_in[14] , right_bottom_grid_pin_3_[0] } ) , .sram ( mux_tree_tapbuf_size2_12_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 } ) , .out ( chanx_right_out[15] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_103 ) ) ; + .p0 ( optlc_net_98 ) ) ; sb_0__0__mux_tree_tapbuf_size2_13 mux_right_track_32 ( .in ( { chany_top_in[15] , right_bottom_grid_pin_5_[0] } ) , .sram ( mux_tree_tapbuf_size2_13_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) , .out ( chanx_right_out[16] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_103 ) ) ; + .p0 ( optlc_net_94 ) ) ; sb_0__0__mux_tree_tapbuf_size2_14 mux_right_track_34 ( .in ( { chany_top_in[16] , right_bottom_grid_pin_7_[0] } ) , .sram ( mux_tree_tapbuf_size2_14_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 } ) , .out ( chanx_right_out[17] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_106 ) ) ; + .p0 ( optlc_net_96 ) ) ; sb_0__0__mux_tree_tapbuf_size2_15 mux_right_track_36 ( .in ( { chany_top_in[17] , right_bottom_grid_pin_9_[0] } ) , .sram ( mux_tree_tapbuf_size2_15_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) , .out ( chanx_right_out[18] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_106 ) ) ; + .p0 ( optlc_net_94 ) ) ; sb_0__0__mux_tree_tapbuf_size2_16 mux_right_track_38 ( .in ( { chany_top_in[18] , right_bottom_grid_pin_11_[0] } ) , .sram ( mux_tree_tapbuf_size2_16_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 } ) , .out ( chanx_right_out[19] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_103 ) ) ; + .p0 ( optlc_net_94 ) ) ; sb_0__0__mux_tree_tapbuf_size2_17 mux_right_track_40 ( .in ( { chany_top_in[19] , right_bottom_grid_pin_13_[0] } ) , .sram ( mux_tree_tapbuf_size2_17_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) , .out ( chanx_right_out[20] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_103 ) ) ; + .p0 ( optlc_net_96 ) ) ; sb_0__0__mux_tree_tapbuf_size2_18 mux_right_track_42 ( .in ( { chany_top_in[20] , right_bottom_grid_pin_15_[0] } ) , .sram ( mux_tree_tapbuf_size2_18_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 } ) , .out ( chanx_right_out[21] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_103 ) ) ; + .p0 ( optlc_net_96 ) ) ; sb_0__0__mux_tree_tapbuf_size2_19 mux_right_track_46 ( .in ( { chany_top_in[22] , right_bottom_grid_pin_3_[0] } ) , .sram ( mux_tree_tapbuf_size2_19_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) , .out ( chanx_right_out[23] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_106 ) ) ; + .p0 ( optlc_net_95 ) ) ; sb_0__0__mux_tree_tapbuf_size2_20 mux_right_track_48 ( .in ( { chany_top_in[23] , right_bottom_grid_pin_5_[0] } ) , .sram ( mux_tree_tapbuf_size2_20_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 } ) , .out ( chanx_right_out[24] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_105 ) ) ; + .p0 ( optlc_net_95 ) ) ; sb_0__0__mux_tree_tapbuf_size2_21 mux_right_track_50 ( .in ( { chany_top_in[24] , right_bottom_grid_pin_7_[0] } ) , .sram ( mux_tree_tapbuf_size2_21_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) , .out ( chanx_right_out[25] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_105 ) ) ; + .p0 ( optlc_net_95 ) ) ; sb_0__0__mux_tree_tapbuf_size2_22 mux_right_track_52 ( .in ( { chany_top_in[25] , right_bottom_grid_pin_9_[0] } ) , .sram ( mux_tree_tapbuf_size2_22_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 } ) , .out ( chanx_right_out[26] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_103 ) ) ; + .p0 ( optlc_net_94 ) ) ; sb_0__0__mux_tree_tapbuf_size2_23 mux_right_track_54 ( .in ( { chany_top_in[26] , right_bottom_grid_pin_11_[0] } ) , .sram ( mux_tree_tapbuf_size2_23_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) , .out ( chanx_right_out[27] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_103 ) ) ; + .p0 ( optlc_net_94 ) ) ; sb_0__0__mux_tree_tapbuf_size2_24 mux_right_track_56 ( .in ( { chany_top_in[27] , right_bottom_grid_pin_13_[0] } ) , .sram ( mux_tree_tapbuf_size2_24_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 } ) , .out ( chanx_right_out[28] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_103 ) ) ; + .p0 ( optlc_net_98 ) ) ; sb_0__0__mux_tree_tapbuf_size2 mux_right_track_58 ( .in ( { chany_top_in[28] , right_bottom_grid_pin_15_[0] } ) , .sram ( mux_tree_tapbuf_size2_25_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) , .out ( chanx_right_out[29] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_103 ) ) ; + .p0 ( optlc_net_94 ) ) ; sb_0__0__mux_tree_tapbuf_size2_mem_0 mem_top_track_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , @@ -45861,7 +45841,7 @@ sb_0__0__mux_tree_tapbuf_size4_0 mux_right_track_0 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 , SYNOPSYS_UNCONNECTED_55 } ) , .out ( chanx_right_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_104 ) ) ; + .p0 ( optlc_net_97 ) ) ; sb_0__0__mux_tree_tapbuf_size4_1 mux_right_track_2 ( .in ( { chany_top_in[0] , right_bottom_grid_pin_3_[0] , right_bottom_grid_pin_9_[0] , right_bottom_grid_pin_15_[0] } ) , @@ -45869,7 +45849,7 @@ sb_0__0__mux_tree_tapbuf_size4_1 mux_right_track_2 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_56 , SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 } ) , .out ( chanx_right_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_104 ) ) ; + .p0 ( optlc_net_97 ) ) ; sb_0__0__mux_tree_tapbuf_size4_2 mux_right_track_4 ( .in ( { chany_top_in[1] , right_bottom_grid_pin_5_[0] , right_bottom_grid_pin_11_[0] , right_bottom_grid_pin_17_[0] } ) , @@ -45877,7 +45857,7 @@ sb_0__0__mux_tree_tapbuf_size4_2 mux_right_track_4 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 , SYNOPSYS_UNCONNECTED_61 } ) , .out ( chanx_right_out[2] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_104 ) ) ; + .p0 ( optlc_net_97 ) ) ; sb_0__0__mux_tree_tapbuf_size4_3 mux_right_track_6 ( .in ( { chany_top_in[2] , right_bottom_grid_pin_1_[0] , right_bottom_grid_pin_7_[0] , right_bottom_grid_pin_13_[0] } ) , @@ -45885,7 +45865,7 @@ sb_0__0__mux_tree_tapbuf_size4_3 mux_right_track_6 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_62 , SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) , .out ( chanx_right_out[3] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_104 ) ) ; + .p0 ( optlc_net_97 ) ) ; sb_0__0__mux_tree_tapbuf_size4_4 mux_right_track_8 ( .in ( { chany_top_in[3] , right_bottom_grid_pin_3_[0] , right_bottom_grid_pin_9_[0] , right_bottom_grid_pin_15_[0] } ) , @@ -45893,7 +45873,7 @@ sb_0__0__mux_tree_tapbuf_size4_4 mux_right_track_8 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 , SYNOPSYS_UNCONNECTED_67 } ) , .out ( chanx_right_out[4] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_104 ) ) ; + .p0 ( optlc_net_97 ) ) ; sb_0__0__mux_tree_tapbuf_size4 mux_right_track_10 ( .in ( { chany_top_in[4] , right_bottom_grid_pin_5_[0] , right_bottom_grid_pin_11_[0] , right_bottom_grid_pin_17_[0] } ) , @@ -45901,7 +45881,7 @@ sb_0__0__mux_tree_tapbuf_size4 mux_right_track_10 ( .sram_inv ( { SYNOPSYS_UNCONNECTED_68 , SYNOPSYS_UNCONNECTED_69 , SYNOPSYS_UNCONNECTED_70 } ) , .out ( chanx_right_out[5] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_104 ) ) ; + .p0 ( optlc_net_97 ) ) ; sb_0__0__mux_tree_tapbuf_size4_mem_0 mem_right_track_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , @@ -45938,21 +45918,21 @@ sb_0__0__mux_tree_tapbuf_size3_0 mux_right_track_12 ( .sram ( mux_tree_tapbuf_size3_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_71 , SYNOPSYS_UNCONNECTED_72 } ) , .out ( chanx_right_out[6] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_104 ) ) ; + .p0 ( optlc_net_98 ) ) ; sb_0__0__mux_tree_tapbuf_size3_1 mux_right_track_28 ( .in ( { chany_top_in[13] , right_bottom_grid_pin_1_[0] , right_bottom_grid_pin_17_[0] } ) , .sram ( mux_tree_tapbuf_size3_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_73 , SYNOPSYS_UNCONNECTED_74 } ) , .out ( chanx_right_out[14] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_103 ) ) ; + .p0 ( optlc_net_98 ) ) ; sb_0__0__mux_tree_tapbuf_size3 mux_right_track_44 ( .in ( { chany_top_in[21] , right_bottom_grid_pin_1_[0] , right_bottom_grid_pin_17_[0] } ) , .sram ( mux_tree_tapbuf_size3_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_75 , SYNOPSYS_UNCONNECTED_76 } ) , .out ( chanx_right_out[22] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p0 ( optlc_net_103 ) ) ; + .p0 ( optlc_net_98 ) ) ; sb_0__0__mux_tree_tapbuf_size3_mem_0 mem_right_track_12 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) , @@ -45972,39 +45952,39 @@ sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_E_in ) , .X ( pReset[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_E_in ) , .X ( prog_clk[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 FTB_36__35 ( .A ( chanx_right_in[0] ) , - .X ( ropt_net_139 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 FTB_37__36 ( .A ( chanx_right_in[2] ) , - .X ( chany_top_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_36__35 ( .A ( chanx_right_in[0] ) , + .X ( chany_top_out[29] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_37__36 ( .A ( chanx_right_in[2] ) , + .X ( ropt_net_141 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_38__37 ( .A ( chanx_right_in[3] ) , .X ( chany_top_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chanx_right_in[5] ) , - .X ( chany_top_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_39__38 ( .A ( chanx_right_in[5] ) , + .X ( ropt_net_133 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_40__39 ( .A ( chanx_right_in[6] ) , .X ( chany_top_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_41__40 ( .A ( chanx_right_in[8] ) , .X ( chany_top_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_6 FTB_42__41 ( .A ( chanx_right_in[9] ) , .X ( chany_top_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 FTB_43__42 ( .A ( chanx_right_in[10] ) , - .X ( chany_top_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_43__42 ( .A ( chanx_right_in[10] ) , + .X ( ropt_net_134 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_44__43 ( .A ( chanx_right_in[11] ) , .X ( chany_top_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_45__44 ( .A ( chanx_right_in[12] ) , .X ( chany_top_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 FTB_46__45 ( .A ( chanx_right_in[13] ) , - .X ( chany_top_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 FTB_46__45 ( .A ( chanx_right_in[13] ) , + .X ( ropt_net_135 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_47__46 ( .A ( chanx_right_in[14] ) , .X ( chany_top_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_48__47 ( .A ( chanx_right_in[16] ) , .X ( chany_top_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 FTB_49__48 ( .A ( chanx_right_in[17] ) , - .X ( ropt_net_140 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 FTB_49__48 ( .A ( chanx_right_in[17] ) , + .X ( chany_top_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_50__49 ( .A ( chanx_right_in[18] ) , .X ( chany_top_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_51__50 ( .A ( chanx_right_in[19] ) , .X ( chany_top_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 FTB_52__51 ( .A ( chanx_right_in[20] ) , +sky130_fd_sc_hd__buf_8 FTB_52__51 ( .A ( chanx_right_in[20] ) , .X ( chany_top_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_53__52 ( .A ( chanx_right_in[21] ) , .X ( chany_top_out[20] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; @@ -46022,18 +46002,24 @@ sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( chanx_right_in[28] ) , .X ( chany_top_out[27] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( chanx_right_in[29] ) , .X ( chany_top_out[28] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_105 ( .LO ( SYNOPSYS_UNCONNECTED_77 ) , - .HI ( optlc_net_103 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_107 ( .LO ( SYNOPSYS_UNCONNECTED_78 ) , - .HI ( optlc_net_104 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_109 ( .LO ( SYNOPSYS_UNCONNECTED_79 ) , - .HI ( optlc_net_105 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_111 ( .LO ( SYNOPSYS_UNCONNECTED_80 ) , - .HI ( optlc_net_106 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1303 ( .A ( ropt_net_139 ) , - .X ( chany_top_out[29] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1304 ( .A ( ropt_net_140 ) , - .X ( chany_top_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_96 ( .LO ( SYNOPSYS_UNCONNECTED_77 ) , + .HI ( optlc_net_94 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_99 ( .LO ( SYNOPSYS_UNCONNECTED_78 ) , + .HI ( optlc_net_95 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_101 ( .LO ( SYNOPSYS_UNCONNECTED_79 ) , + .HI ( optlc_net_96 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_103 ( .LO ( SYNOPSYS_UNCONNECTED_80 ) , + .HI ( optlc_net_97 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_105 ( .LO ( SYNOPSYS_UNCONNECTED_81 ) , + .HI ( optlc_net_98 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1299 ( .A ( ropt_net_133 ) , + .X ( chany_top_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1300 ( .A ( ropt_net_134 ) , + .X ( chany_top_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1301 ( .A ( ropt_net_135 ) , + .X ( chany_top_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1307 ( .A ( ropt_net_141 ) , + .X ( chany_top_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -46058,16 +46044,16 @@ sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_6 FTB_63__62 ( .A ( copt_net_196 ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1614 ( .A ( copt_net_198 ) , - .X ( copt_net_195 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1615 ( .A ( copt_net_195 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1637 ( .A ( copt_net_200 ) , .X ( copt_net_196 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1616 ( .A ( copt_net_199 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1638 ( .A ( copt_net_199 ) , .X ( copt_net_197 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1617 ( .A ( copt_net_197 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1639 ( .A ( mem_out[1] ) , .X ( copt_net_198 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1618 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1640 ( .A ( copt_net_198 ) , .X ( copt_net_199 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1641 ( .A ( copt_net_197 ) , + .X ( copt_net_200 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -46209,12 +46195,12 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( aps_rename_521_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_129 ( .A ( BUF_net_131 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_130 ( .A ( BUF_net_132 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_130 ( .A ( BUF_net_131 ) , .Y ( p_abuf0 ) , +sky130_fd_sc_hd__inv_2 BINV_R_131 ( .A ( BUF_net_132 ) , .Y ( p_abuf0 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_131 ( .A ( aps_rename_521_ ) , - .Y ( BUF_net_131 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_132 ( .A ( aps_rename_521_ ) , + .Y ( BUF_net_132 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -46239,12 +46225,12 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( aps_rename_520_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_126 ( .A ( BUF_net_128 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_2 BINV_R_127 ( .A ( BUF_net_129 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_127 ( .A ( BUF_net_128 ) , .Y ( p_abuf0 ) , +sky130_fd_sc_hd__inv_8 BINV_R_128 ( .A ( BUF_net_129 ) , .Y ( p_abuf0 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_128 ( .A ( aps_rename_520_ ) , - .Y ( BUF_net_128 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_129 ( .A ( aps_rename_520_ ) , + .Y ( BUF_net_129 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -46267,14 +46253,16 @@ supply0 VSS ; sky130_fd_sc_hd__sdfrtp_1 sky130_fd_sc_hd__sdfrtp_1_0_ ( .D ( ff_D[0] ) , .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( ff_clk[0] ) , - .RESET_B ( ff_reset[0] ) , .Q ( p_abuf1 ) , .VPWR ( VDD ) , + .RESET_B ( ff_reset[0] ) , .Q ( aps_rename_519_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_81 ( .A ( BUF_net_83 ) , .Y ( ff_Q[0] ) , +sky130_fd_sc_hd__inv_1 BINV_R_81 ( .A ( BUF_net_84 ) , .Y ( ff_Q[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_82 ( .A ( BUF_net_83 ) , .Y ( p_abuf0 ) , +sky130_fd_sc_hd__inv_8 BINV_R_82 ( .A ( BUF_net_84 ) , .Y ( p_abuf0 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_83 ( .A ( p_abuf1 ) , .Y ( BUF_net_83 ) , +sky130_fd_sc_hd__inv_1 BINV_R_83 ( .A ( BUF_net_84 ) , .Y ( p_abuf1 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_84 ( .A ( aps_rename_519_ ) , + .Y ( BUF_net_84 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -46739,7 +46727,7 @@ module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric ( pReset , prog_clk , Test_en , fabric_in , fabric_reg_in , fabric_sc_in , fabric_cin , fabric_reset , fabric_clk , ccff_head , fabric_out , fabric_reg_out , fabric_sc_out , fabric_cout , ccff_tail , VDD , VSS , - p_abuf0 , p_abuf2 , p_abuf3 , p0 ) ; + p_abuf0 , p_abuf2 , p_abuf3 , p0 , p1 ) ; input [0:0] pReset ; input [0:0] prog_clk ; input [0:0] Test_en ; @@ -46761,6 +46749,7 @@ output p_abuf0 ; output p_abuf2 ; output p_abuf3 ; input p0 ; +input p1 ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ; @@ -46787,7 +46776,7 @@ grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ .frac_logic_cout ( { SYNOPSYS_UNCONNECTED_1 } ) , .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p1 ) ) ; grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_14 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( .Test_en ( Test_en ) , .ff_D ( mux_tree_size2_2_out ) , .ff_DI ( fabric_sc_in ) , .ff_reset ( fabric_reset ) , @@ -46807,15 +46796,15 @@ grid_clb_mux_tree_size2_44 mux_fabric_out_0 ( .sram ( mux_tree_size2_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 } ) , .out ( fabric_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p_abuf0 ( p_abuf2 ) , .p0 ( p0 ) ) ; + .p_abuf0 ( p_abuf2 ) , .p0 ( p1 ) ) ; grid_clb_mux_tree_size2_45 mux_fabric_out_1 ( - .in ( { fabric_sc_out[0] , + .in ( { p_abuf1 , logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] } ) , .sram ( mux_tree_size2_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 } ) , .out ( fabric_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p_abuf0 ( p_abuf3 ) , .p0 ( p0 ) ) ; + .p_abuf0 ( p_abuf3 ) , .p0 ( p1 ) ) ; grid_clb_mux_tree_size2_46 mux_ff_0_D_0 ( .in ( { logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] , @@ -46830,7 +46819,7 @@ grid_clb_mux_tree_size2 mux_ff_1_D_0 ( } ) , .sram ( mux_tree_size2_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_8 , SYNOPSYS_UNCONNECTED_9 } ) , - .out ( mux_tree_size2_3_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; + .out ( mux_tree_size2_3_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p1 ) ) ; grid_clb_mux_tree_size2_mem_44 mem_fabric_out_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , @@ -46856,7 +46845,7 @@ endmodule module grid_clb_logical_tile_clb_mode_default__fle ( pReset , prog_clk , Test_en , fle_in , fle_reg_in , fle_sc_in , fle_cin , fle_reset , fle_clk , ccff_head , fle_out , fle_reg_out , fle_sc_out , fle_cout , - ccff_tail , VDD , VSS , p_abuf0 , p_abuf1 , p_abuf2 , p1 ) ; + ccff_tail , VDD , VSS , p_abuf0 , p_abuf1 , p_abuf2 , p0 , p1 ) ; input [0:0] pReset ; input [0:0] prog_clk ; input [0:0] Test_en ; @@ -46877,6 +46866,7 @@ input VSS ; output p_abuf0 ; output p_abuf1 ; output p_abuf2 ; +input p0 ; input p1 ; supply1 VDD ; @@ -46892,7 +46882,7 @@ grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric logical_tile_c .fabric_reg_out ( fle_reg_out ) , .fabric_sc_out ( fle_sc_out ) , .fabric_cout ( fle_cout ) , .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( p_abuf0 ) , .p_abuf2 ( p_abuf1 ) , - .p_abuf3 ( p_abuf2 ) , .p0 ( p1 ) ) ; + .p_abuf3 ( p_abuf2 ) , .p0 ( p0 ) , .p1 ( p1 ) ) ; endmodule @@ -47059,17 +47049,17 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( aps_rename_518_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_123 ( .A ( BUF_net_125 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_2 BINV_R_124 ( .A ( BUF_net_126 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_124 ( .A ( BUF_net_125 ) , .Y ( p_abuf0 ) , +sky130_fd_sc_hd__inv_8 BINV_R_125 ( .A ( BUF_net_126 ) , .Y ( p_abuf0 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_125 ( .A ( aps_rename_518_ ) , - .Y ( BUF_net_125 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_126 ( .A ( aps_rename_518_ ) , + .Y ( BUF_net_126 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module grid_clb_mux_tree_size2_38 ( in , sram , sram_inv , out , VDD , VSS , - p_abuf0 , p3 ) ; + p_abuf0 , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -47077,7 +47067,7 @@ output [0:0] out ; input VDD ; input VSS ; output p_abuf0 ; -input p3 ; +input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; supply1 VDD ; @@ -47086,15 +47076,15 @@ supply0 VSS ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p3 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( aps_rename_517_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_120 ( .A ( BUF_net_122 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_2 BINV_R_121 ( .A ( BUF_net_123 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_121 ( .A ( BUF_net_122 ) , .Y ( p_abuf0 ) , +sky130_fd_sc_hd__inv_8 BINV_R_122 ( .A ( BUF_net_123 ) , .Y ( p_abuf0 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_122 ( .A ( aps_rename_517_ ) , - .Y ( BUF_net_122 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_123 ( .A ( aps_rename_517_ ) , + .Y ( BUF_net_123 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -47189,14 +47179,14 @@ endmodule module grid_clb_mux_tree_size2_37 ( in , sram , sram_inv , out , VDD , VSS , - p3 ) ; + p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; input VDD ; input VSS ; -input p3 ; +input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; supply1 VDD ; @@ -47205,7 +47195,7 @@ supply0 VSS ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p3 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -47507,7 +47497,7 @@ endmodule module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_6 ( pReset , prog_clk , frac_logic_in , frac_logic_cin , ccff_head , - frac_logic_out , frac_logic_cout , ccff_tail , VDD , VSS , p3 ) ; + frac_logic_out , frac_logic_cout , ccff_tail , VDD , VSS , p0 , p3 ) ; input [0:0] pReset ; input [0:0] prog_clk ; input [0:3] frac_logic_in ; @@ -47518,6 +47508,7 @@ output [0:0] frac_logic_cout ; output [0:0] ccff_tail ; input VDD ; input VSS ; +input p0 ; input p3 ; wire [0:0] direct_interc_5_out ; @@ -47563,7 +47554,7 @@ grid_clb_mux_tree_size2_37 mux_frac_lut4_0_in_2 ( .in ( { frac_logic_cin[0] , frac_logic_in[2] } ) , .sram ( mux_tree_size2_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 } ) , - .out ( mux_tree_size2_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p3 ( p3 ) ) ; + .out ( mux_tree_size2_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; grid_clb_mux_tree_size2_mem_36 mem_frac_logic_out_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , @@ -47629,7 +47620,7 @@ grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ .frac_logic_cout ( { SYNOPSYS_UNCONNECTED_1 } ) , .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p3 ( p3 ) ) ; + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p1 ) , .p3 ( p3 ) ) ; grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_12 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( .Test_en ( Test_en ) , .ff_D ( mux_tree_size2_2_out ) , .ff_DI ( fabric_sc_in ) , .ff_reset ( fabric_reset ) , @@ -47648,7 +47639,7 @@ grid_clb_mux_tree_size2_38 mux_fabric_out_0 ( .sram ( mux_tree_size2_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 } ) , .out ( fabric_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p_abuf0 ( p_abuf0 ) , .p3 ( p3 ) ) ; + .p_abuf0 ( p_abuf0 ) , .p0 ( p1 ) ) ; grid_clb_mux_tree_size2_39 mux_fabric_out_1 ( .in ( { fabric_sc_out[0] , logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] @@ -47671,7 +47662,7 @@ grid_clb_mux_tree_size2_41 mux_ff_1_D_0 ( } ) , .sram ( mux_tree_size2_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_8 , SYNOPSYS_UNCONNECTED_9 } ) , - .out ( mux_tree_size2_3_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p1 ) ) ; + .out ( mux_tree_size2_3_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; grid_clb_mux_tree_size2_mem_38 mem_fabric_out_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , @@ -47859,14 +47850,14 @@ endmodule module grid_clb_mux_tree_size2_34 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; + p3 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; input VDD ; input VSS ; -input p0 ; +input p3 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; supply1 VDD ; @@ -47875,7 +47866,7 @@ supply0 VSS ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p3 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -47902,12 +47893,12 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p3 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( aps_rename_516_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_117 ( .A ( BUF_net_119 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_118 ( .A ( BUF_net_120 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_118 ( .A ( BUF_net_119 ) , .Y ( p_abuf0 ) , +sky130_fd_sc_hd__inv_2 BINV_R_119 ( .A ( BUF_net_120 ) , .Y ( p_abuf0 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_119 ( .A ( aps_rename_516_ ) , - .Y ( BUF_net_119 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_120 ( .A ( aps_rename_516_ ) , + .Y ( BUF_net_120 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -47932,12 +47923,12 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p3 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( aps_rename_515_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_114 ( .A ( BUF_net_116 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_115 ( .A ( BUF_net_117 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_115 ( .A ( BUF_net_116 ) , .Y ( p_abuf0 ) , +sky130_fd_sc_hd__inv_2 BINV_R_116 ( .A ( BUF_net_117 ) , .Y ( p_abuf0 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_116 ( .A ( aps_rename_515_ ) , - .Y ( BUF_net_116 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_117 ( .A ( aps_rename_515_ ) , + .Y ( BUF_net_117 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -48423,7 +48414,7 @@ module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_5 ( pReset , prog_clk , Test_en , fabric_in , fabric_reg_in , fabric_sc_in , fabric_cin , fabric_reset , fabric_clk , ccff_head , fabric_out , fabric_reg_out , fabric_sc_out , fabric_cout , ccff_tail , VDD , VSS , - p_abuf0 , p_abuf1 , p0 , p3 ) ; + p_abuf0 , p_abuf1 , p3 ) ; input [0:0] pReset ; input [0:0] prog_clk ; input [0:0] Test_en ; @@ -48443,7 +48434,6 @@ input VDD ; input VSS ; output p_abuf0 ; output p_abuf1 ; -input p0 ; input p3 ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ; @@ -48505,7 +48495,7 @@ grid_clb_mux_tree_size2_34 mux_ff_0_D_0 ( fabric_reg_in[0] } ) , .sram ( mux_tree_size2_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_6 , SYNOPSYS_UNCONNECTED_7 } ) , - .out ( mux_tree_size2_2_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; + .out ( mux_tree_size2_2_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p3 ( p3 ) ) ; grid_clb_mux_tree_size2_35 mux_ff_1_D_0 ( .in ( { logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] , @@ -48539,7 +48529,7 @@ endmodule module grid_clb_logical_tile_clb_mode_default__fle_5 ( pReset , prog_clk , Test_en , fle_in , fle_reg_in , fle_sc_in , fle_cin , fle_reset , fle_clk , ccff_head , fle_out , fle_reg_out , fle_sc_out , fle_cout , - ccff_tail , VDD , VSS , p_abuf0 , p_abuf1 , p0 , p3 ) ; + ccff_tail , VDD , VSS , p_abuf0 , p_abuf1 , p3 ) ; input [0:0] pReset ; input [0:0] prog_clk ; input [0:0] Test_en ; @@ -48559,7 +48549,6 @@ input VDD ; input VSS ; output p_abuf0 ; output p_abuf1 ; -input p0 ; input p3 ; supply1 VDD ; @@ -48575,7 +48564,7 @@ grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_5 logical_tile .fabric_reg_out ( fle_reg_out ) , .fabric_sc_out ( fle_sc_out ) , .fabric_cout ( { SYNOPSYS_UNCONNECTED_2 } ) , .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , .p0 ( p0 ) , .p3 ( p3 ) ) ; + .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , .p3 ( p3 ) ) ; endmodule @@ -48676,14 +48665,14 @@ endmodule module grid_clb_mux_tree_size2_29 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; + p3 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; input VDD ; input VSS ; -input p0 ; +input p3 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; supply1 VDD ; @@ -48692,21 +48681,21 @@ supply0 VSS ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p3 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module grid_clb_mux_tree_size2_28 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; + p2 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; input VDD ; input VSS ; -input p0 ; +input p2 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; supply1 VDD ; @@ -48715,7 +48704,7 @@ supply0 VSS ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -48742,17 +48731,17 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p3 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( aps_rename_514_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_111 ( .A ( BUF_net_113 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_2 BINV_R_112 ( .A ( BUF_net_114 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_112 ( .A ( BUF_net_113 ) , .Y ( p_abuf0 ) , +sky130_fd_sc_hd__inv_8 BINV_R_113 ( .A ( BUF_net_114 ) , .Y ( p_abuf0 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_113 ( .A ( aps_rename_514_ ) , - .Y ( BUF_net_113 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_114 ( .A ( aps_rename_514_ ) , + .Y ( BUF_net_114 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module grid_clb_mux_tree_size2_26 ( in , sram , sram_inv , out , VDD , VSS , - p_abuf0 , p0 ) ; + p_abuf0 , p3 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -48760,7 +48749,7 @@ output [0:0] out ; input VDD ; input VSS ; output p_abuf0 ; -input p0 ; +input p3 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; supply1 VDD ; @@ -48769,15 +48758,15 @@ supply0 VSS ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p3 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( aps_rename_513_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_108 ( .A ( BUF_net_110 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_2 BINV_R_109 ( .A ( BUF_net_111 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_109 ( .A ( BUF_net_110 ) , .Y ( p_abuf0 ) , +sky130_fd_sc_hd__inv_8 BINV_R_110 ( .A ( BUF_net_111 ) , .Y ( p_abuf0 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_110 ( .A ( aps_rename_513_ ) , - .Y ( BUF_net_110 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_111 ( .A ( aps_rename_513_ ) , + .Y ( BUF_net_111 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -48895,14 +48884,14 @@ endmodule module grid_clb_mux_tree_size2_24 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; + p2 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; input VDD ; input VSS ; -input p0 ; +input p2 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; supply1 VDD ; @@ -48911,7 +48900,7 @@ supply0 VSS ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -49190,7 +49179,7 @@ endmodule module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_4 ( pReset , prog_clk , frac_logic_in , frac_logic_cin , ccff_head , - frac_logic_out , frac_logic_cout , ccff_tail , VDD , VSS , p0 , p2 ) ; + frac_logic_out , frac_logic_cout , ccff_tail , VDD , VSS , p2 ) ; input [0:0] pReset ; input [0:0] prog_clk ; input [0:3] frac_logic_in ; @@ -49201,7 +49190,6 @@ output [0:0] frac_logic_cout ; output [0:0] ccff_tail ; input VDD ; input VSS ; -input p0 ; input p2 ; wire [0:0] direct_interc_5_out ; @@ -49242,7 +49230,7 @@ grid_clb_mux_tree_size2_24 mux_frac_logic_out_0 ( } ) , .sram ( mux_tree_size2_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 } ) , - .out ( frac_logic_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; + .out ( frac_logic_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , .p2 ( p2 ) ) ; grid_clb_mux_tree_size2_25 mux_frac_lut4_0_in_2 ( .in ( { frac_logic_cin[0] , frac_logic_in[2] } ) , .sram ( mux_tree_size2_1_sram ) , @@ -49264,7 +49252,7 @@ module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_4 ( pReset , prog_clk , Test_en , fabric_in , fabric_reg_in , fabric_sc_in , fabric_cin , fabric_reset , fabric_clk , ccff_head , fabric_out , fabric_reg_out , fabric_sc_out , fabric_cout , ccff_tail , VDD , VSS , - p_abuf0 , p_abuf1 , p0 , p2 , p3 ) ; + p_abuf0 , p_abuf1 , p2 , p3 ) ; input [0:0] pReset ; input [0:0] prog_clk ; input [0:0] Test_en ; @@ -49284,7 +49272,6 @@ input VDD ; input VSS ; output p_abuf0 ; output p_abuf1 ; -input p0 ; input p2 ; input p3 ; @@ -49313,7 +49300,7 @@ grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ .frac_logic_cout ( { SYNOPSYS_UNCONNECTED_1 } ) , .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) , .p2 ( p2 ) ) ; + .VDD ( VDD ) , .VSS ( VSS ) , .p2 ( p2 ) ) ; grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_8 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( .Test_en ( Test_en ) , .ff_D ( mux_tree_size2_2_out ) , .ff_DI ( fabric_sc_in ) , .ff_reset ( fabric_reset ) , @@ -49332,7 +49319,7 @@ grid_clb_mux_tree_size2_26 mux_fabric_out_0 ( .sram ( mux_tree_size2_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 } ) , .out ( fabric_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p_abuf0 ( p_abuf0 ) , .p0 ( p0 ) ) ; + .p_abuf0 ( p_abuf0 ) , .p3 ( p3 ) ) ; grid_clb_mux_tree_size2_27 mux_fabric_out_1 ( .in ( { fabric_sc_out[0] , logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] @@ -49347,7 +49334,7 @@ grid_clb_mux_tree_size2_28 mux_ff_0_D_0 ( fabric_reg_in[0] } ) , .sram ( mux_tree_size2_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_6 , SYNOPSYS_UNCONNECTED_7 } ) , - .out ( mux_tree_size2_2_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; + .out ( mux_tree_size2_2_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p2 ( p2 ) ) ; grid_clb_mux_tree_size2_29 mux_ff_1_D_0 ( .in ( { logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] , @@ -49355,7 +49342,7 @@ grid_clb_mux_tree_size2_29 mux_ff_1_D_0 ( } ) , .sram ( mux_tree_size2_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_8 , SYNOPSYS_UNCONNECTED_9 } ) , - .out ( mux_tree_size2_3_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; + .out ( mux_tree_size2_3_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p3 ( p3 ) ) ; grid_clb_mux_tree_size2_mem_26 mem_fabric_out_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , @@ -49381,7 +49368,7 @@ endmodule module grid_clb_logical_tile_clb_mode_default__fle_4 ( pReset , prog_clk , Test_en , fle_in , fle_reg_in , fle_sc_in , fle_cin , fle_reset , fle_clk , ccff_head , fle_out , fle_reg_out , fle_sc_out , fle_cout , - ccff_tail , VDD , VSS , p_abuf0 , p_abuf1 , p0 , p2 , p3 ) ; + ccff_tail , VDD , VSS , p_abuf0 , p_abuf1 , p2 , p3 ) ; input [0:0] pReset ; input [0:0] prog_clk ; input [0:0] Test_en ; @@ -49401,7 +49388,6 @@ input VDD ; input VSS ; output p_abuf0 ; output p_abuf1 ; -input p0 ; input p2 ; input p3 ; @@ -49418,8 +49404,7 @@ grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_4 logical_tile .fabric_reg_out ( fle_reg_out ) , .fabric_sc_out ( fle_sc_out ) , .fabric_cout ( { SYNOPSYS_UNCONNECTED_2 } ) , .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , .p0 ( p0 ) , .p2 ( p2 ) , - .p3 ( p3 ) ) ; + .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , .p2 ( p2 ) , .p3 ( p3 ) ) ; endmodule @@ -49586,12 +49571,12 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( aps_rename_512_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_105 ( .A ( BUF_net_107 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_2 BINV_R_106 ( .A ( BUF_net_108 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_106 ( .A ( BUF_net_107 ) , .Y ( p_abuf0 ) , +sky130_fd_sc_hd__inv_8 BINV_R_107 ( .A ( BUF_net_108 ) , .Y ( p_abuf0 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_107 ( .A ( aps_rename_512_ ) , - .Y ( BUF_net_107 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_108 ( .A ( aps_rename_512_ ) , + .Y ( BUF_net_108 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -49616,12 +49601,12 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( aps_rename_511_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_102 ( .A ( BUF_net_104 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_2 BINV_R_103 ( .A ( BUF_net_105 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_103 ( .A ( BUF_net_104 ) , .Y ( p_abuf0 ) , +sky130_fd_sc_hd__inv_8 BINV_R_104 ( .A ( BUF_net_105 ) , .Y ( p_abuf0 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_104 ( .A ( aps_rename_511_ ) , - .Y ( BUF_net_104 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_105 ( .A ( aps_rename_511_ ) , + .Y ( BUF_net_105 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -50404,7 +50389,7 @@ endmodule module grid_clb_mux_tree_size2_15 ( in , sram , sram_inv , out , VDD , VSS , - p_abuf0 , p1 ) ; + p_abuf0 , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -50412,7 +50397,7 @@ output [0:0] out ; input VDD ; input VSS ; output p_abuf0 ; -input p1 ; +input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; supply1 VDD ; @@ -50421,15 +50406,15 @@ supply0 VSS ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p1 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( aps_rename_510_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_99 ( .A ( BUF_net_101 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_2 BINV_R_100 ( .A ( BUF_net_102 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_100 ( .A ( BUF_net_101 ) , .Y ( p_abuf0 ) , +sky130_fd_sc_hd__inv_8 BINV_R_101 ( .A ( BUF_net_102 ) , .Y ( p_abuf0 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_101 ( .A ( aps_rename_510_ ) , - .Y ( BUF_net_101 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_102 ( .A ( aps_rename_510_ ) , + .Y ( BUF_net_102 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -50454,12 +50439,12 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p4 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( aps_rename_509_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_96 ( .A ( BUF_net_98 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_2 BINV_R_97 ( .A ( BUF_net_99 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_97 ( .A ( BUF_net_98 ) , .Y ( p_abuf0 ) , +sky130_fd_sc_hd__inv_8 BINV_R_98 ( .A ( BUF_net_99 ) , .Y ( p_abuf0 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_98 ( .A ( aps_rename_509_ ) , - .Y ( BUF_net_98 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_99 ( .A ( aps_rename_509_ ) , + .Y ( BUF_net_99 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -50577,14 +50562,14 @@ endmodule module grid_clb_mux_tree_size2_12 ( in , sram , sram_inv , out , VDD , VSS , - p2 ) ; + p4 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; input VDD ; input VSS ; -input p2 ; +input p4 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; supply1 VDD ; @@ -50593,7 +50578,7 @@ supply0 VSS ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p4 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -50872,7 +50857,7 @@ endmodule module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_2 ( pReset , prog_clk , frac_logic_in , frac_logic_cin , ccff_head , - frac_logic_out , frac_logic_cout , ccff_tail , VDD , VSS , p2 , p4 ) ; + frac_logic_out , frac_logic_cout , ccff_tail , VDD , VSS , p4 ) ; input [0:0] pReset ; input [0:0] prog_clk ; input [0:3] frac_logic_in ; @@ -50883,7 +50868,6 @@ output [0:0] frac_logic_cout ; output [0:0] ccff_tail ; input VDD ; input VSS ; -input p2 ; input p4 ; wire [0:0] direct_interc_5_out ; @@ -50924,7 +50908,7 @@ grid_clb_mux_tree_size2_12 mux_frac_logic_out_0 ( } ) , .sram ( mux_tree_size2_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 } ) , - .out ( frac_logic_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , .p2 ( p2 ) ) ; + .out ( frac_logic_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , .p4 ( p4 ) ) ; grid_clb_mux_tree_size2_13 mux_frac_lut4_0_in_2 ( .in ( { frac_logic_cin[0] , frac_logic_in[2] } ) , .sram ( mux_tree_size2_1_sram ) , @@ -50946,7 +50930,7 @@ module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_2 ( pReset , prog_clk , Test_en , fabric_in , fabric_reg_in , fabric_sc_in , fabric_cin , fabric_reset , fabric_clk , ccff_head , fabric_out , fabric_reg_out , fabric_sc_out , fabric_cout , ccff_tail , VDD , VSS , - p_abuf0 , p_abuf1 , p1 , p2 , p4 ) ; + p_abuf0 , p_abuf1 , p0 , p2 , p4 ) ; input [0:0] pReset ; input [0:0] prog_clk ; input [0:0] Test_en ; @@ -50966,7 +50950,7 @@ input VDD ; input VSS ; output p_abuf0 ; output p_abuf1 ; -input p1 ; +input p0 ; input p2 ; input p4 ; @@ -50995,7 +50979,7 @@ grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ .frac_logic_cout ( { SYNOPSYS_UNCONNECTED_1 } ) , .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p2 ( p2 ) , .p4 ( p4 ) ) ; + .VDD ( VDD ) , .VSS ( VSS ) , .p4 ( p4 ) ) ; grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_4 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( .Test_en ( Test_en ) , .ff_D ( mux_tree_size2_2_out ) , .ff_DI ( fabric_sc_in ) , .ff_reset ( fabric_reset ) , @@ -51022,7 +51006,7 @@ grid_clb_mux_tree_size2_15 mux_fabric_out_1 ( .sram ( mux_tree_size2_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 } ) , .out ( fabric_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p_abuf0 ( p_abuf1 ) , .p1 ( p1 ) ) ; + .p_abuf0 ( p_abuf1 ) , .p0 ( p0 ) ) ; grid_clb_mux_tree_size2_16 mux_ff_0_D_0 ( .in ( { logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] , @@ -51063,7 +51047,7 @@ endmodule module grid_clb_logical_tile_clb_mode_default__fle_2 ( pReset , prog_clk , Test_en , fle_in , fle_reg_in , fle_sc_in , fle_cin , fle_reset , fle_clk , ccff_head , fle_out , fle_reg_out , fle_sc_out , fle_cout , - ccff_tail , VDD , VSS , p_abuf0 , p_abuf1 , p1 , p2 , p4 ) ; + ccff_tail , VDD , VSS , p_abuf0 , p_abuf1 , p0 , p2 , p4 ) ; input [0:0] pReset ; input [0:0] prog_clk ; input [0:0] Test_en ; @@ -51083,7 +51067,7 @@ input VDD ; input VSS ; output p_abuf0 ; output p_abuf1 ; -input p1 ; +input p0 ; input p2 ; input p4 ; @@ -51100,7 +51084,7 @@ grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_2 logical_tile .fabric_reg_out ( fle_reg_out ) , .fabric_sc_out ( fle_sc_out ) , .fabric_cout ( { SYNOPSYS_UNCONNECTED_2 } ) , .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , .p1 ( p1 ) , .p2 ( p2 ) , + .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , .p0 ( p0 ) , .p2 ( p2 ) , .p4 ( p4 ) ) ; endmodule @@ -51225,14 +51209,14 @@ endmodule module grid_clb_mux_tree_size2_10 ( in , sram , sram_inv , out , VDD , VSS , - p1 ) ; + p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; input VDD ; input VSS ; -input p1 ; +input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; supply1 VDD ; @@ -51241,7 +51225,7 @@ supply0 VSS ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p1 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -51268,17 +51252,17 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( aps_rename_508_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_93 ( .A ( BUF_net_95 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_2 BINV_R_94 ( .A ( BUF_net_96 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_94 ( .A ( BUF_net_95 ) , .Y ( p_abuf0 ) , +sky130_fd_sc_hd__inv_8 BINV_R_95 ( .A ( BUF_net_96 ) , .Y ( p_abuf0 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_95 ( .A ( aps_rename_508_ ) , - .Y ( BUF_net_95 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_96 ( .A ( aps_rename_508_ ) , + .Y ( BUF_net_96 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module grid_clb_mux_tree_size2_8 ( in , sram , sram_inv , out , VDD , VSS , - p_abuf0 , p1 ) ; + p_abuf0 , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -51286,7 +51270,7 @@ output [0:0] out ; input VDD ; input VSS ; output p_abuf0 ; -input p1 ; +input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; supply1 VDD ; @@ -51295,15 +51279,15 @@ supply0 VSS ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p1 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( aps_rename_507_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_90 ( .A ( BUF_net_92 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_2 BINV_R_91 ( .A ( BUF_net_93 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_91 ( .A ( BUF_net_92 ) , .Y ( p_abuf0 ) , +sky130_fd_sc_hd__inv_8 BINV_R_92 ( .A ( BUF_net_93 ) , .Y ( p_abuf0 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_92 ( .A ( aps_rename_507_ ) , - .Y ( BUF_net_92 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_93 ( .A ( aps_rename_507_ ) , + .Y ( BUF_net_93 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -51856,7 +51840,7 @@ grid_clb_mux_tree_size2_8 mux_fabric_out_0 ( .sram ( mux_tree_size2_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 } ) , .out ( fabric_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p_abuf0 ( p_abuf0 ) , .p1 ( p1 ) ) ; + .p_abuf0 ( p_abuf0 ) , .p0 ( p0 ) ) ; grid_clb_mux_tree_size2_9 mux_fabric_out_1 ( .in ( { fabric_sc_out[0] , logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] @@ -51871,7 +51855,7 @@ grid_clb_mux_tree_size2_10 mux_ff_0_D_0 ( fabric_reg_in[0] } ) , .sram ( mux_tree_size2_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_6 , SYNOPSYS_UNCONNECTED_7 } ) , - .out ( mux_tree_size2_2_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p1 ( p1 ) ) ; + .out ( mux_tree_size2_2_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; grid_clb_mux_tree_size2_11 mux_ff_1_D_0 ( .in ( { logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] , @@ -52108,12 +52092,12 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p1 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( aps_rename_506_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_87 ( .A ( BUF_net_89 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_2 BINV_R_88 ( .A ( BUF_net_90 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_88 ( .A ( BUF_net_89 ) , .Y ( p_abuf0 ) , +sky130_fd_sc_hd__inv_8 BINV_R_89 ( .A ( BUF_net_90 ) , .Y ( p_abuf0 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_89 ( .A ( aps_rename_506_ ) , - .Y ( BUF_net_89 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_90 ( .A ( aps_rename_506_ ) , + .Y ( BUF_net_90 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -52138,12 +52122,12 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p1 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( aps_rename_505_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_84 ( .A ( BUF_net_86 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_2 BINV_R_85 ( .A ( BUF_net_87 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_85 ( .A ( BUF_net_86 ) , .Y ( p_abuf0 ) , +sky130_fd_sc_hd__inv_8 BINV_R_86 ( .A ( BUF_net_87 ) , .Y ( p_abuf0 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_86 ( .A ( aps_rename_505_ ) , - .Y ( BUF_net_86 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_87 ( .A ( aps_rename_505_ ) , + .Y ( BUF_net_87 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -52333,7 +52317,7 @@ input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_200 ) , +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_201 ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , @@ -52386,20 +52370,20 @@ sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_16_ ( .D ( mem_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[16] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1607 ( .A ( ccff_head[0] ) , - .X ( copt_net_188 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1608 ( .A ( copt_net_191 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1630 ( .A ( ccff_head[0] ) , .X ( copt_net_189 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1609 ( .A ( copt_net_192 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1631 ( .A ( copt_net_194 ) , .X ( copt_net_190 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1610 ( .A ( copt_net_190 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1632 ( .A ( copt_net_190 ) , .X ( copt_net_191 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1611 ( .A ( copt_net_188 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1633 ( .A ( copt_net_189 ) , .X ( copt_net_192 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1612 ( .A ( copt_net_189 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1634 ( .A ( copt_net_192 ) , .X ( copt_net_193 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 ropt_h_inst_1619 ( .A ( copt_net_193 ) , - .X ( ropt_net_200 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1635 ( .A ( copt_net_193 ) , + .X ( copt_net_194 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 ropt_h_inst_1642 ( .A ( copt_net_191 ) , + .X ( ropt_net_201 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -52932,7 +52916,7 @@ grid_clb_logical_tile_clb_mode_default__fle_2 logical_tile_clb_mode_default__fle .fle_cout ( { SYNOPSYS_UNCONNECTED_6 } ) , .ccff_tail ( logical_tile_clb_mode_default__fle_2_ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( p_abuf5 ) , - .p_abuf1 ( p_abuf6 ) , .p1 ( p2 ) , .p2 ( p3 ) , .p4 ( p5 ) ) ; + .p_abuf1 ( p_abuf6 ) , .p0 ( p0 ) , .p2 ( p3 ) , .p4 ( p5 ) ) ; grid_clb_logical_tile_clb_mode_default__fle_3 logical_tile_clb_mode_default__fle_3 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .fle_in ( { clb_I3[0] , clb_I3[1] , clb_I3i[0] , clb_I3i[1] } ) , @@ -52962,7 +52946,7 @@ grid_clb_logical_tile_clb_mode_default__fle_4 logical_tile_clb_mode_default__fle .fle_cout ( { SYNOPSYS_UNCONNECTED_10 } ) , .ccff_tail ( logical_tile_clb_mode_default__fle_4_ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( p_abuf9 ) , - .p_abuf1 ( p_abuf10 ) , .p0 ( p0 ) , .p2 ( p3 ) , .p3 ( p4 ) ) ; + .p_abuf1 ( p_abuf10 ) , .p2 ( p3 ) , .p3 ( p4 ) ) ; grid_clb_logical_tile_clb_mode_default__fle_5 logical_tile_clb_mode_default__fle_5 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .fle_in ( { clb_I5[0] , clb_I5[1] , clb_I5i[0] , clb_I5i[1] } ) , @@ -52977,7 +52961,7 @@ grid_clb_logical_tile_clb_mode_default__fle_5 logical_tile_clb_mode_default__fle .fle_cout ( { SYNOPSYS_UNCONNECTED_12 } ) , .ccff_tail ( logical_tile_clb_mode_default__fle_5_ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( p_abuf11 ) , - .p_abuf1 ( p_abuf12 ) , .p0 ( p0 ) , .p3 ( p4 ) ) ; + .p_abuf1 ( p_abuf12 ) , .p3 ( p4 ) ) ; grid_clb_logical_tile_clb_mode_default__fle_6 logical_tile_clb_mode_default__fle_6 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .fle_in ( { clb_I6[0] , clb_I6[1] , clb_I6i[0] , clb_I6i[1] } ) , @@ -53005,7 +52989,7 @@ grid_clb_logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_7 .fle_reg_out ( clb_reg_out ) , .fle_sc_out ( clb_sc_out ) , .fle_cout ( clb_cout ) , .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf15 ) , - .p_abuf2 ( p_abuf16 ) , .p1 ( p1 ) ) ; + .p_abuf2 ( p_abuf16 ) , .p0 ( p0 ) , .p1 ( p1 ) ) ; endmodule @@ -53242,9 +53226,9 @@ grid_clb_logical_tile_clb_mode_clb_ logical_tile_clb_mode_clb__0 ( .p_abuf13 ( right_width_0_height_0__pin_49_lower[0] ) , .p_abuf14 ( right_width_0_height_0__pin_48_lower[0] ) , .p_abuf15 ( right_width_0_height_0__pin_51_lower[0] ) , - .p_abuf16 ( p_abuf16 ) , .p0 ( optlc_net_178 ) , .p1 ( optlc_net_179 ) , - .p2 ( optlc_net_180 ) , .p3 ( optlc_net_181 ) , .p4 ( optlc_net_182 ) , - .p5 ( optlc_net_183 ) ) ; + .p_abuf16 ( p_abuf16 ) , .p0 ( optlc_net_179 ) , .p1 ( optlc_net_180 ) , + .p2 ( optlc_net_181 ) , .p3 ( optlc_net_182 ) , .p4 ( optlc_net_183 ) , + .p5 ( optlc_net_184 ) ) ; sky130_fd_sc_hd__buf_2 Test_en_FTB00 ( .A ( Test_en_W_in ) , .X ( Test_en[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_1 Test_en_W_FTB01 ( .A ( Test_en_W_in ) , @@ -53262,13 +53246,13 @@ sky130_fd_sc_hd__buf_1 Reset_E_FTB01 ( .A ( Reset_W_in ) , sky130_fd_sc_hd__buf_6 prog_clk_0_FTB00 ( .A ( prog_clk_0_S_in ) , .X ( prog_clk_0 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__clkbuf_1 prog_clk_0_S_FTB01 ( .A ( prog_clk_0_S_in ) , - .X ( ctsbuf_net_1184 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__clkbuf_1 prog_clk_0_E_FTB01 ( .A ( prog_clk_0_S_in ) , - .X ( ctsbuf_net_2185 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__clkbuf_1 prog_clk_0_W_FTB01 ( .A ( prog_clk_0_S_in ) , - .X ( ctsbuf_net_3186 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .X ( ctsbuf_net_1185 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_4 prog_clk_0_E_FTB01 ( .A ( prog_clk_0_S_in ) , + .X ( ctsbuf_net_2186 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_4 prog_clk_0_W_FTB01 ( .A ( prog_clk_0_S_in ) , + .X ( ctsbuf_net_3187 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__clkbuf_1 prog_clk_0_N_FTB01 ( .A ( prog_clk_0_S_in ) , - .X ( ctsbuf_net_4187 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .X ( ctsbuf_net_4188 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_1 clk_0_FTB00 ( .A ( clk_0_S_in ) , .X ( clk[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_6 FTB_65__64 ( .A ( aps_rename_522_ ) , @@ -53321,39 +53305,39 @@ sky130_fd_sc_hd__buf_6 FTB_80__79 ( .A ( aps_rename_537_ ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_6 FTB_81__80 ( .A ( aps_rename_538_ ) , .X ( SC_OUT_TOP ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_132 ( .A ( BUF_net_133 ) , +sky130_fd_sc_hd__inv_8 BINV_R_133 ( .A ( BUF_net_134 ) , .Y ( Test_en_W_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_133 ( .A ( aps_rename_539_ ) , - .Y ( BUF_net_133 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_134 ( .A ( BUF_net_135 ) , +sky130_fd_sc_hd__inv_1 BINV_R_134 ( .A ( aps_rename_539_ ) , + .Y ( BUF_net_134 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_135 ( .A ( BUF_net_136 ) , .Y ( Test_en_E_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_135 ( .A ( aps_rename_540_ ) , - .Y ( BUF_net_135 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_136 ( .A ( BUF_net_137 ) , .Y ( Reset_W_out ) , +sky130_fd_sc_hd__inv_1 BINV_R_136 ( .A ( aps_rename_540_ ) , + .Y ( BUF_net_136 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_137 ( .A ( BUF_net_138 ) , .Y ( Reset_W_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_137 ( .A ( aps_rename_541_ ) , - .Y ( BUF_net_137 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_140 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_178 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_142 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , +sky130_fd_sc_hd__inv_1 BINV_R_138 ( .A ( aps_rename_541_ ) , + .Y ( BUF_net_138 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_141 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , .HI ( optlc_net_179 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_144 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , +sky130_fd_sc_hd__conb_1 optlc_143 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , .HI ( optlc_net_180 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_146 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , +sky130_fd_sc_hd__conb_1 optlc_145 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , .HI ( optlc_net_181 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_148 ( .LO ( SYNOPSYS_UNCONNECTED_6 ) , +sky130_fd_sc_hd__conb_1 optlc_147 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , .HI ( optlc_net_182 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_150 ( .LO ( SYNOPSYS_UNCONNECTED_7 ) , +sky130_fd_sc_hd__conb_1 optlc_149 ( .LO ( SYNOPSYS_UNCONNECTED_6 ) , .HI ( optlc_net_183 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 ZBUF_6_f_inst_151 ( .A ( aps_rename_542_ ) , +sky130_fd_sc_hd__conb_1 optlc_151 ( .LO ( SYNOPSYS_UNCONNECTED_7 ) , + .HI ( optlc_net_184 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_6_f_inst_152 ( .A ( aps_rename_542_ ) , .X ( Reset_E_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 cts_buf_3981324 ( .A ( ctsbuf_net_1184 ) , +sky130_fd_sc_hd__buf_6 cts_buf_3981325 ( .A ( ctsbuf_net_1185 ) , .X ( prog_clk_0_S_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__clkbuf_8 cts_buf_4031329 ( .A ( ctsbuf_net_2185 ) , +sky130_fd_sc_hd__bufbuf_16 cts_buf_4031330 ( .A ( ctsbuf_net_2186 ) , .X ( prog_clk_0_E_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 cts_buf_4081334 ( .A ( ctsbuf_net_3186 ) , +sky130_fd_sc_hd__buf_6 cts_buf_4081335 ( .A ( ctsbuf_net_3187 ) , .X ( prog_clk_0_W_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 cts_buf_4131339 ( .A ( ctsbuf_net_4187 ) , +sky130_fd_sc_hd__buf_6 cts_buf_4131340 ( .A ( ctsbuf_net_4188 ) , .X ( prog_clk_0_N_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -110444,15 +110428,15 @@ endmodule module fpga_top ( vdda1 , vdda2 , vssa1 , vssa2 , vccd1 , vccd2 , vssd1 , vssd2 , wb_clk_i , wb_rst_i , wbs_stb_i , wbs_cyc_i , wbs_we_i , wbs_sel_i , wbs_dat_i , wbs_adr_i , wbs_ack_o , wbs_dat_o , la_data_in , - la_data_out , la_oen , io_in , io_out , io_oeb , VDD , VSS , - analog_io_0_ , analog_io_10_ , analog_io_11_ , analog_io_12_ , - analog_io_13_ , analog_io_14_ , analog_io_15_ , analog_io_16_ , - analog_io_17_ , analog_io_18_ , analog_io_19_ , analog_io_1_ , - analog_io_20_ , analog_io_21_ , analog_io_22_ , analog_io_23_ , - analog_io_24_ , analog_io_25_ , analog_io_26_ , analog_io_27_ , - analog_io_28_ , analog_io_29_ , analog_io_2_ , analog_io_30_ , - analog_io_3_ , analog_io_4_ , analog_io_5_ , analog_io_6_ , analog_io_7_ , - analog_io_8_ , analog_io_9_ , user_clock2 ) ; + la_data_out , la_oen , io_in , io_out , io_oeb , analog_io_0_ , + analog_io_10_ , analog_io_11_ , analog_io_12_ , analog_io_13_ , + analog_io_14_ , analog_io_15_ , analog_io_16_ , analog_io_17_ , + analog_io_18_ , analog_io_19_ , analog_io_1_ , analog_io_20_ , + analog_io_21_ , analog_io_22_ , analog_io_23_ , analog_io_24_ , + analog_io_25_ , analog_io_26_ , analog_io_27_ , analog_io_28_ , + analog_io_29_ , analog_io_2_ , analog_io_30_ , analog_io_3_ , + analog_io_4_ , analog_io_5_ , analog_io_6_ , analog_io_7_ , analog_io_8_ , + analog_io_9_ , user_clock2 , VDD , VSS ) ; inout vdda1 ; inout vdda2 ; inout vssa1 ; @@ -110477,8 +110461,6 @@ input [127:0] la_oen ; input [37:0] io_in ; output [37:0] io_out ; output [37:0] io_oeb ; -input VDD ; -input VSS ; inout analog_io_0_ ; inout analog_io_10_ ; inout analog_io_11_ ; @@ -110511,6 +110493,8 @@ inout analog_io_7_ ; inout analog_io_8_ ; inout analog_io_9_ ; input user_clock2 ; +input VDD ; +input VSS ; wire [0:143] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ; wire [0:143] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ; diff --git a/FPGA1212_QLSOFA_HD_PNR/fpga_top/fpga_top_icv_in_design.nominal_25.spef b/FPGA1212_QLSOFA_HD_PNR/fpga_top/fpga_top_icv_in_design.nominal_25.spef deleted file mode 100644 index e9595c3..0000000 --- a/FPGA1212_QLSOFA_HD_PNR/fpga_top/fpga_top_icv_in_design.nominal_25.spef +++ /dev/null @@ -1,3 +0,0 @@ -version https://git-lfs.github.com/spec/v1 -oid sha256:a5283079014bf5109c5fef3ae7327e703bd5319d251b1cd7646a5ec706aa8c8a -size 38343791 diff --git a/FPGA1212_QLSOFA_HD_PNR/fpga_top/fpga_top_icv_in_design.nominal_25.spef.gz b/FPGA1212_QLSOFA_HD_PNR/fpga_top/fpga_top_icv_in_design.nominal_25.spef.gz new file mode 100644 index 0000000..345aba3 Binary files /dev/null and b/FPGA1212_QLSOFA_HD_PNR/fpga_top/fpga_top_icv_in_design.nominal_25.spef.gz differ diff --git a/FPGA1212_QLSOFA_HD_PNR/fpga_top/fpga_top_icv_in_design.pt.v b/FPGA1212_QLSOFA_HD_PNR/fpga_top/fpga_top_icv_in_design.pt.v index 3784305..daadd83 100644 --- a/FPGA1212_QLSOFA_HD_PNR/fpga_top/fpga_top_icv_in_design.pt.v +++ b/FPGA1212_QLSOFA_HD_PNR/fpga_top/fpga_top_icv_in_design.pt.v @@ -12,19 +12,17 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:0] mem_out ; -wire copt_net_103 ; +wire copt_net_102 ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( copt_net_103 ) ) ; -sky130_fd_sc_hd__buf_8 FTB_18__17 ( .A ( mem_out[0] ) , .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__buf_1 ropt_h_inst_1347 ( .A ( ropt_net_114 ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( copt_net_102 ) ) ; +sky130_fd_sc_hd__buf_1 FTB_18__17 ( .A ( mem_out[0] ) , .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1338 ( .A ( copt_net_105 ) , .X ( mem_out[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1338 ( .A ( copt_net_106 ) , - .X ( copt_net_104 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1340 ( .A ( copt_net_103 ) , - .X ( copt_net_106 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1341 ( .A ( copt_net_104 ) , - .X ( ropt_net_114 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1339 ( .A ( copt_net_107 ) , + .X ( copt_net_105 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1341 ( .A ( copt_net_102 ) , + .X ( copt_net_107 ) ) ; endmodule @@ -284,6 +282,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -313,8 +313,6 @@ sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_89 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , - .X ( out[0] ) ) ; endmodule @@ -851,7 +849,7 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_113 ) , +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_110 ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; @@ -860,23 +858,25 @@ sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1330 ( .A ( ccff_head[0] ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1329 ( .A ( ccff_head[0] ) , + .X ( copt_net_95 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1330 ( .A ( ropt_net_113 ) , .X ( copt_net_96 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1331 ( .A ( copt_net_96 ) , +sky130_fd_sc_hd__dlygate4sd2_1 copt_h_inst_1331 ( .A ( copt_net_99 ) , .X ( copt_net_97 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1332 ( .A ( copt_net_97 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1332 ( .A ( ropt_net_111 ) , .X ( copt_net_98 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1333 ( .A ( copt_net_98 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1333 ( .A ( copt_net_96 ) , .X ( copt_net_99 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1334 ( .A ( copt_net_99 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1334 ( .A ( copt_net_97 ) , .X ( copt_net_100 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 copt_h_inst_1335 ( .A ( copt_net_100 ) , - .X ( copt_net_101 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1344 ( .A ( copt_net_101 ) , +sky130_fd_sc_hd__buf_1 ropt_h_inst_1343 ( .A ( copt_net_98 ) , + .X ( ropt_net_110 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1344 ( .A ( ropt_net_112 ) , .X ( ropt_net_111 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 ropt_h_inst_1345 ( .A ( ropt_net_111 ) , +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1345 ( .A ( copt_net_100 ) , .X ( ropt_net_112 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1346 ( .A ( ropt_net_112 ) , +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1346 ( .A ( copt_net_95 ) , .X ( ropt_net_113 ) ) ; endmodule @@ -1517,7 +1517,7 @@ cby_2__1__mux_tree_tapbuf_size12_0 mux_left_ipin_0 ( .sram ( mux_tree_tapbuf_size12_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , - .out ( right_grid_pin_0_ ) , .p0 ( optlc_net_91 ) ) ; + .out ( right_grid_pin_0_ ) , .p0 ( optlc_net_90 ) ) ; cby_2__1__mux_tree_tapbuf_size12_1 mux_right_ipin_0 ( .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[4] , chany_bottom_out[4] , chany_top_out[7] , chany_bottom_out[7] , @@ -1526,7 +1526,7 @@ cby_2__1__mux_tree_tapbuf_size12_1 mux_right_ipin_0 ( .sram ( mux_tree_tapbuf_size12_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) , - .out ( left_grid_pin_16_ ) , .p0 ( optlc_net_92 ) ) ; + .out ( left_grid_pin_16_ ) , .p0 ( optlc_net_91 ) ) ; cby_2__1__mux_tree_tapbuf_size12_2 mux_right_ipin_2 ( .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[3] , chany_bottom_out[3] , chany_top_out[9] , chany_bottom_out[9] , @@ -1535,7 +1535,7 @@ cby_2__1__mux_tree_tapbuf_size12_2 mux_right_ipin_2 ( .sram ( mux_tree_tapbuf_size12_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , - .out ( left_grid_pin_18_ ) , .p0 ( optlc_net_93 ) ) ; + .out ( left_grid_pin_18_ ) , .p0 ( optlc_net_92 ) ) ; cby_2__1__mux_tree_tapbuf_size12_3 mux_right_ipin_4 ( .in ( { chany_top_out[2] , chany_bottom_out[2] , chany_top_out[5] , chany_bottom_out[5] , chany_top_out[11] , chany_bottom_out[11] , @@ -1544,7 +1544,7 @@ cby_2__1__mux_tree_tapbuf_size12_3 mux_right_ipin_4 ( .sram ( mux_tree_tapbuf_size12_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) , - .out ( left_grid_pin_20_ ) , .p0 ( optlc_net_90 ) ) ; + .out ( left_grid_pin_20_ ) , .p0 ( optlc_net_89 ) ) ; cby_2__1__mux_tree_tapbuf_size12_4 mux_right_ipin_6 ( .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[4] , chany_bottom_out[4] , chany_top_out[7] , chany_bottom_out[7] , @@ -1553,7 +1553,7 @@ cby_2__1__mux_tree_tapbuf_size12_4 mux_right_ipin_6 ( .sram ( mux_tree_tapbuf_size12_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 , SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) , - .out ( left_grid_pin_22_ ) , .p0 ( optlc_net_92 ) ) ; + .out ( left_grid_pin_22_ ) , .p0 ( optlc_net_91 ) ) ; cby_2__1__mux_tree_tapbuf_size12_5 mux_right_ipin_8 ( .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[3] , chany_bottom_out[3] , chany_top_out[9] , chany_bottom_out[9] , @@ -1562,7 +1562,7 @@ cby_2__1__mux_tree_tapbuf_size12_5 mux_right_ipin_8 ( .sram ( mux_tree_tapbuf_size12_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 , SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) , - .out ( left_grid_pin_24_ ) , .p0 ( optlc_net_93 ) ) ; + .out ( left_grid_pin_24_ ) , .p0 ( optlc_net_92 ) ) ; cby_2__1__mux_tree_tapbuf_size12_6 mux_right_ipin_10 ( .in ( { chany_top_out[2] , chany_bottom_out[2] , chany_top_out[5] , chany_bottom_out[5] , chany_top_out[11] , chany_bottom_out[11] , @@ -1571,7 +1571,7 @@ cby_2__1__mux_tree_tapbuf_size12_6 mux_right_ipin_10 ( .sram ( mux_tree_tapbuf_size12_6_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) , - .out ( left_grid_pin_26_ ) , .p0 ( optlc_net_90 ) ) ; + .out ( left_grid_pin_26_ ) , .p0 ( optlc_net_89 ) ) ; cby_2__1__mux_tree_tapbuf_size12_7 mux_right_ipin_12 ( .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[4] , chany_bottom_out[4] , chany_top_out[7] , chany_bottom_out[7] , @@ -1580,7 +1580,7 @@ cby_2__1__mux_tree_tapbuf_size12_7 mux_right_ipin_12 ( .sram ( mux_tree_tapbuf_size12_7_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 , SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) , - .out ( left_grid_pin_28_ ) , .p0 ( optlc_net_93 ) ) ; + .out ( left_grid_pin_28_ ) , .p0 ( optlc_net_92 ) ) ; cby_2__1__mux_tree_tapbuf_size12 mux_right_ipin_14 ( .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[3] , chany_bottom_out[3] , chany_top_out[9] , chany_bottom_out[9] , @@ -1589,7 +1589,7 @@ cby_2__1__mux_tree_tapbuf_size12 mux_right_ipin_14 ( .sram ( mux_tree_tapbuf_size12_8_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 , SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) , - .out ( left_grid_pin_30_ ) , .p0 ( optlc_net_93 ) ) ; + .out ( left_grid_pin_30_ ) , .p0 ( optlc_net_92 ) ) ; cby_2__1__mux_tree_tapbuf_size12_mem_0 mem_left_ipin_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size12_mem_0_ccff_tail ) , @@ -1642,7 +1642,7 @@ cby_2__1__mux_tree_tapbuf_size10_0 mux_right_ipin_1 ( .sram ( mux_tree_tapbuf_size10_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 , SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) , - .out ( left_grid_pin_17_ ) , .p0 ( optlc_net_91 ) ) ; + .out ( left_grid_pin_17_ ) , .p0 ( optlc_net_90 ) ) ; cby_2__1__mux_tree_tapbuf_size10_1 mux_right_ipin_3 ( .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[4] , chany_bottom_out[4] , chany_top_out[10] , chany_bottom_out[10] , @@ -1651,7 +1651,7 @@ cby_2__1__mux_tree_tapbuf_size10_1 mux_right_ipin_3 ( .sram ( mux_tree_tapbuf_size10_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 , SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) , - .out ( left_grid_pin_19_ ) , .p0 ( optlc_net_91 ) ) ; + .out ( left_grid_pin_19_ ) , .p0 ( optlc_net_90 ) ) ; cby_2__1__mux_tree_tapbuf_size10_2 mux_right_ipin_5 ( .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[3] , chany_bottom_out[3] , chany_top_out[6] , chany_bottom_out[6] , @@ -1660,7 +1660,7 @@ cby_2__1__mux_tree_tapbuf_size10_2 mux_right_ipin_5 ( .sram ( mux_tree_tapbuf_size10_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 , SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) , - .out ( left_grid_pin_21_ ) , .p0 ( optlc_net_92 ) ) ; + .out ( left_grid_pin_21_ ) , .p0 ( optlc_net_91 ) ) ; cby_2__1__mux_tree_tapbuf_size10_3 mux_right_ipin_7 ( .in ( { chany_top_out[2] , chany_bottom_out[2] , chany_top_out[5] , chany_bottom_out[5] , chany_top_out[8] , chany_bottom_out[8] , @@ -1669,7 +1669,7 @@ cby_2__1__mux_tree_tapbuf_size10_3 mux_right_ipin_7 ( .sram ( mux_tree_tapbuf_size10_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 , SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) , - .out ( left_grid_pin_23_ ) , .p0 ( optlc_net_92 ) ) ; + .out ( left_grid_pin_23_ ) , .p0 ( optlc_net_91 ) ) ; cby_2__1__mux_tree_tapbuf_size10_4 mux_right_ipin_9 ( .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[4] , chany_bottom_out[4] , chany_top_out[10] , chany_bottom_out[10] , @@ -1678,7 +1678,7 @@ cby_2__1__mux_tree_tapbuf_size10_4 mux_right_ipin_9 ( .sram ( mux_tree_tapbuf_size10_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 , SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) , - .out ( left_grid_pin_25_ ) , .p0 ( optlc_net_92 ) ) ; + .out ( left_grid_pin_25_ ) , .p0 ( optlc_net_91 ) ) ; cby_2__1__mux_tree_tapbuf_size10_5 mux_right_ipin_11 ( .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[3] , chany_bottom_out[3] , chany_top_out[12] , chany_bottom_out[12] , @@ -1687,7 +1687,7 @@ cby_2__1__mux_tree_tapbuf_size10_5 mux_right_ipin_11 ( .sram ( mux_tree_tapbuf_size10_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 , SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) , - .out ( left_grid_pin_27_ ) , .p0 ( optlc_net_92 ) ) ; + .out ( left_grid_pin_27_ ) , .p0 ( optlc_net_91 ) ) ; cby_2__1__mux_tree_tapbuf_size10_6 mux_right_ipin_13 ( .in ( { chany_top_out[2] , chany_bottom_out[2] , chany_top_out[5] , chany_bottom_out[5] , chany_top_out[14] , chany_bottom_out[14] , @@ -1696,7 +1696,7 @@ cby_2__1__mux_tree_tapbuf_size10_6 mux_right_ipin_13 ( .sram ( mux_tree_tapbuf_size10_6_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 , SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) , - .out ( left_grid_pin_29_ ) , .p0 ( optlc_net_91 ) ) ; + .out ( left_grid_pin_29_ ) , .p0 ( optlc_net_90 ) ) ; cby_2__1__mux_tree_tapbuf_size10 mux_right_ipin_15 ( .in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[4] , chany_bottom_out[4] , chany_top_out[7] , chany_bottom_out[7] , @@ -1705,7 +1705,7 @@ cby_2__1__mux_tree_tapbuf_size10 mux_right_ipin_15 ( .sram ( mux_tree_tapbuf_size10_7_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 , SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 } ) , - .out ( left_grid_pin_31_ ) , .p0 ( optlc_net_93 ) ) ; + .out ( left_grid_pin_31_ ) , .p0 ( optlc_net_92 ) ) ; cby_2__1__mux_tree_tapbuf_size10_mem_0 mem_right_ipin_1 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size12_mem_1_ccff_tail ) , @@ -1753,15 +1753,15 @@ cby_2__1__logical_tile_io_mode_io_ logical_tile_io_mode_io__0 ( .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) , .io_outpad ( left_width_0_height_0__pin_0_ ) , .ccff_head ( { ccff_tail_mid } ) , - .io_inpad ( left_width_0_height_0__pin_1_lower ) , - .ccff_tail ( ccff_tail ) ) ; + .io_inpad ( left_width_0_height_0__pin_1_lower ) , + .ccff_tail ( { ropt_net_108 } ) ) ; sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_S_in ) , .X ( pReset[0] ) ) ; sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_W_in ) , .X ( prog_clk[0] ) ) ; sky130_fd_sc_hd__clkbuf_1 prog_clk_0_S_FTB01 ( .A ( prog_clk_0_W_in ) , - .X ( ctsbuf_net_194 ) ) ; + .X ( ctsbuf_net_193 ) ) ; sky130_fd_sc_hd__clkbuf_1 prog_clk_0_N_FTB01 ( .A ( prog_clk_0_W_in ) , - .X ( ctsbuf_net_295 ) ) ; + .X ( ctsbuf_net_294 ) ) ; sky130_fd_sc_hd__buf_8 FTB_19__18 ( .A ( chany_bottom_in[0] ) , .X ( chany_top_out[0] ) ) ; sky130_fd_sc_hd__buf_8 FTB_20__19 ( .A ( chany_bottom_in[1] ) , @@ -1885,17 +1885,19 @@ sky130_fd_sc_hd__buf_8 FTB_78__77 ( .A ( chany_top_in[29] ) , sky130_fd_sc_hd__buf_6 FTB_79__78 ( .A ( left_width_0_height_0__pin_1_lower[0] ) , .X ( left_width_0_height_0__pin_1_upper[0] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_92 ( .LO ( SYNOPSYS_UNCONNECTED_69 ) , +sky130_fd_sc_hd__conb_1 optlc_91 ( .LO ( SYNOPSYS_UNCONNECTED_69 ) , + .HI ( optlc_net_89 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_93 ( .LO ( SYNOPSYS_UNCONNECTED_70 ) , .HI ( optlc_net_90 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_94 ( .LO ( SYNOPSYS_UNCONNECTED_70 ) , +sky130_fd_sc_hd__conb_1 optlc_95 ( .LO ( SYNOPSYS_UNCONNECTED_71 ) , .HI ( optlc_net_91 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_96 ( .LO ( SYNOPSYS_UNCONNECTED_71 ) , +sky130_fd_sc_hd__conb_1 optlc_97 ( .LO ( SYNOPSYS_UNCONNECTED_72 ) , .HI ( optlc_net_92 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_98 ( .LO ( SYNOPSYS_UNCONNECTED_72 ) , - .HI ( optlc_net_93 ) ) ; -sky130_fd_sc_hd__buf_6 cts_buf_3591232 ( .A ( ctsbuf_net_194 ) , +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1342 ( .A ( ropt_net_108 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__buf_6 cts_buf_3591231 ( .A ( ctsbuf_net_193 ) , .X ( prog_clk_0_S_out ) ) ; -sky130_fd_sc_hd__buf_6 cts_buf_3641237 ( .A ( ctsbuf_net_295 ) , +sky130_fd_sc_hd__clkbuf_8 cts_buf_3641236 ( .A ( ctsbuf_net_294 ) , .X ( prog_clk_0_N_out ) ) ; endmodule @@ -1908,6 +1910,8 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; +wire copt_net_115 ; + sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , @@ -1915,14 +1919,14 @@ sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , - .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( copt_net_115 ) ) ; sky130_fd_sc_hd__buf_6 FTB_16__15 ( .A ( copt_net_118 ) , .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1352 ( .A ( mem_out[3] ) , - .X ( copt_net_115 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1352 ( .A ( copt_net_115 ) , + .X ( mem_out[3] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1355 ( .A ( copt_net_120 ) , .X ( copt_net_118 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1356 ( .A ( copt_net_115 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1356 ( .A ( mem_out[3] ) , .X ( copt_net_119 ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1357 ( .A ( copt_net_119 ) , .X ( copt_net_120 ) ) ; @@ -2634,7 +2638,7 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_130 ) , +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_129 ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; @@ -2655,10 +2659,12 @@ sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1359 ( .A ( copt_net_117 ) , .X ( copt_net_122 ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1360 ( .A ( copt_net_122 ) , .X ( copt_net_123 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1367 ( .A ( ropt_net_131 ) , +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1365 ( .A ( copt_net_123 ) , + .X ( ropt_net_128 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 ropt_h_inst_1366 ( .A ( ropt_net_130 ) , + .X ( ropt_net_129 ) ) ; +sky130_fd_sc_hd__buf_1 ropt_h_inst_1367 ( .A ( ropt_net_128 ) , .X ( ropt_net_130 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 ropt_h_inst_1368 ( .A ( copt_net_123 ) , - .X ( ropt_net_131 ) ) ; endmodule @@ -3527,7 +3533,7 @@ sky130_fd_sc_hd__buf_8 FTB_19__18 ( .A ( chany_bottom_in[2] ) , .X ( chany_top_out[2] ) ) ; sky130_fd_sc_hd__buf_8 FTB_20__19 ( .A ( chany_bottom_in[3] ) , .X ( chany_top_out[3] ) ) ; -sky130_fd_sc_hd__buf_12 FTB_21__20 ( .A ( chany_bottom_in[4] ) , +sky130_fd_sc_hd__buf_8 FTB_21__20 ( .A ( chany_bottom_in[4] ) , .X ( chany_top_out[4] ) ) ; sky130_fd_sc_hd__buf_8 FTB_22__21 ( .A ( chany_bottom_in[5] ) , .X ( chany_top_out[5] ) ) ; @@ -3685,23 +3691,23 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:0] mem_out ; -wire copt_net_78 ; +wire copt_net_74 ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , - .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( copt_net_78 ) ) ; + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( copt_net_74 ) ) ; sky130_fd_sc_hd__buf_6 FTB_2__1 ( .A ( mem_out[0] ) , .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1217 ( .A ( copt_net_78 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1217 ( .A ( copt_net_75 ) , .X ( copt_net_73 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1218 ( .A ( copt_net_73 ) , - .X ( copt_net_74 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1218 ( .A ( copt_net_78 ) , + .X ( mem_out[0] ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1219 ( .A ( copt_net_74 ) , .X ( copt_net_75 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1220 ( .A ( copt_net_75 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1220 ( .A ( copt_net_73 ) , .X ( copt_net_76 ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1221 ( .A ( copt_net_76 ) , .X ( copt_net_77 ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1222 ( .A ( copt_net_77 ) , - .X ( mem_out[0] ) ) ; + .X ( copt_net_78 ) ) ; endmodule @@ -3792,7 +3798,7 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( copt_net_72 ) , +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( copt_net_71 ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; @@ -3809,9 +3815,9 @@ sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1213 ( .A ( copt_net_68 ) , .X ( copt_net_69 ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1214 ( .A ( copt_net_69 ) , .X ( copt_net_70 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1215 ( .A ( copt_net_70 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1215 ( .A ( copt_net_72 ) , .X ( copt_net_71 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1216 ( .A ( copt_net_71 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1216 ( .A ( copt_net_70 ) , .X ( copt_net_72 ) ) ; endmodule @@ -3900,20 +3906,20 @@ output [0:0] right_width_0_height_0__pin_1_lower ; input pReset_N_in ; input prog_clk_0_E_in ; -wire ropt_net_134 ; -wire ropt_net_128 ; -wire ropt_net_129 ; -wire ropt_net_133 ; -wire ropt_net_127 ; -wire ropt_net_122 ; -wire ropt_net_124 ; -wire ropt_net_132 ; -wire ropt_net_123 ; wire ropt_net_120 ; -wire ropt_net_138 ; -wire ropt_net_125 ; -wire ropt_net_137 ; +wire ropt_net_118 ; +wire ropt_net_136 ; +wire ropt_net_117 ; wire ropt_net_121 ; +wire ropt_net_125 ; +wire ropt_net_124 ; +wire ropt_net_122 ; +wire ropt_net_115 ; +wire ropt_net_116 ; +wire ropt_net_126 ; +wire ropt_net_119 ; +wire ropt_net_123 ; +wire ropt_net_114 ; wire [0:0] prog_clk ; wire prog_clk_0 ; wire [0:3] mux_tree_tapbuf_size12_0_sram ; @@ -3948,21 +3954,21 @@ sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_E_in ) , sky130_fd_sc_hd__buf_8 FTB_3__2 ( .A ( chany_bottom_in[0] ) , .X ( chany_top_out[0] ) ) ; sky130_fd_sc_hd__buf_6 FTB_4__3 ( .A ( chany_bottom_in[1] ) , - .X ( ropt_net_134 ) ) ; -sky130_fd_sc_hd__buf_8 FTB_5__4 ( .A ( chany_bottom_in[2] ) , - .X ( chany_top_out[2] ) ) ; + .X ( chany_top_out[1] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_5__4 ( .A ( chany_bottom_in[2] ) , + .X ( ropt_net_120 ) ) ; sky130_fd_sc_hd__buf_8 FTB_6__5 ( .A ( chany_bottom_in[3] ) , .X ( chany_top_out[3] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_7__6 ( .A ( chany_bottom_in[4] ) , +sky130_fd_sc_hd__buf_6 FTB_7__6 ( .A ( chany_bottom_in[4] ) , .X ( chany_top_out[4] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_8__7 ( .A ( chany_bottom_in[5] ) , - .X ( chany_top_out[5] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_8__7 ( .A ( chany_bottom_in[5] ) , + .X ( ropt_net_118 ) ) ; sky130_fd_sc_hd__buf_8 FTB_9__8 ( .A ( chany_bottom_in[6] ) , .X ( chany_top_out[6] ) ) ; sky130_fd_sc_hd__buf_8 FTB_10__9 ( .A ( chany_bottom_in[7] ) , .X ( chany_top_out[7] ) ) ; sky130_fd_sc_hd__buf_6 FTB_11__10 ( .A ( chany_bottom_in[8] ) , - .X ( ropt_net_128 ) ) ; + .X ( ropt_net_136 ) ) ; sky130_fd_sc_hd__buf_8 FTB_12__11 ( .A ( chany_bottom_in[9] ) , .X ( chany_top_out[9] ) ) ; sky130_fd_sc_hd__buf_8 FTB_13__12 ( .A ( chany_bottom_in[10] ) , @@ -3971,50 +3977,50 @@ sky130_fd_sc_hd__buf_6 FTB_14__13 ( .A ( chany_bottom_in[11] ) , .X ( chany_top_out[11] ) ) ; sky130_fd_sc_hd__buf_8 FTB_15__14 ( .A ( chany_bottom_in[12] ) , .X ( chany_top_out[12] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_16__15 ( .A ( chany_bottom_in[13] ) , - .X ( chany_top_out[13] ) ) ; -sky130_fd_sc_hd__buf_6 FTB_17__16 ( .A ( chany_bottom_in[14] ) , - .X ( ropt_net_129 ) ) ; +sky130_fd_sc_hd__buf_6 FTB_16__15 ( .A ( chany_bottom_in[13] ) , + .X ( ropt_net_117 ) ) ; +sky130_fd_sc_hd__buf_8 FTB_17__16 ( .A ( chany_bottom_in[14] ) , + .X ( chany_top_out[14] ) ) ; sky130_fd_sc_hd__buf_6 FTB_18__17 ( .A ( chany_bottom_in[15] ) , - .X ( ropt_net_133 ) ) ; -sky130_fd_sc_hd__buf_8 FTB_19__18 ( .A ( chany_bottom_in[16] ) , - .X ( chany_top_out[16] ) ) ; + .X ( ropt_net_121 ) ) ; +sky130_fd_sc_hd__buf_6 FTB_19__18 ( .A ( chany_bottom_in[16] ) , + .X ( ropt_net_125 ) ) ; sky130_fd_sc_hd__buf_6 FTB_20__19 ( .A ( chany_bottom_in[17] ) , .X ( chany_top_out[17] ) ) ; sky130_fd_sc_hd__buf_8 FTB_21__20 ( .A ( chany_bottom_in[18] ) , .X ( chany_top_out[18] ) ) ; sky130_fd_sc_hd__buf_6 FTB_22__21 ( .A ( chany_bottom_in[19] ) , - .X ( ropt_net_127 ) ) ; + .X ( chany_top_out[19] ) ) ; sky130_fd_sc_hd__buf_6 FTB_23__22 ( .A ( chany_bottom_in[20] ) , - .X ( chany_top_out[20] ) ) ; + .X ( ropt_net_124 ) ) ; sky130_fd_sc_hd__buf_8 FTB_24__23 ( .A ( chany_bottom_in[21] ) , .X ( chany_top_out[21] ) ) ; -sky130_fd_sc_hd__buf_6 FTB_25__24 ( .A ( chany_bottom_in[22] ) , - .X ( ropt_net_122 ) ) ; +sky130_fd_sc_hd__buf_8 FTB_25__24 ( .A ( chany_bottom_in[22] ) , + .X ( chany_top_out[22] ) ) ; sky130_fd_sc_hd__buf_6 FTB_26__25 ( .A ( chany_bottom_in[23] ) , - .X ( ropt_net_124 ) ) ; + .X ( ropt_net_122 ) ) ; sky130_fd_sc_hd__buf_8 FTB_27__26 ( .A ( chany_bottom_in[24] ) , .X ( chany_top_out[24] ) ) ; sky130_fd_sc_hd__buf_8 FTB_28__27 ( .A ( chany_bottom_in[25] ) , .X ( chany_top_out[25] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_29__28 ( .A ( chany_bottom_in[26] ) , +sky130_fd_sc_hd__buf_6 FTB_29__28 ( .A ( chany_bottom_in[26] ) , .X ( chany_top_out[26] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_30__29 ( .A ( chany_bottom_in[27] ) , - .X ( chany_top_out[27] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_30__29 ( .A ( chany_bottom_in[27] ) , + .X ( ropt_net_115 ) ) ; sky130_fd_sc_hd__buf_8 FTB_31__30 ( .A ( chany_bottom_in[28] ) , .X ( chany_top_out[28] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_32__31 ( .A ( chany_bottom_in[29] ) , +sky130_fd_sc_hd__buf_6 FTB_32__31 ( .A ( chany_bottom_in[29] ) , .X ( chany_top_out[29] ) ) ; sky130_fd_sc_hd__buf_8 FTB_33__32 ( .A ( chany_top_in[0] ) , .X ( chany_bottom_out[0] ) ) ; sky130_fd_sc_hd__buf_6 FTB_34__33 ( .A ( chany_top_in[1] ) , .X ( chany_bottom_out[1] ) ) ; -sky130_fd_sc_hd__buf_6 FTB_35__34 ( .A ( chany_top_in[2] ) , - .X ( ropt_net_132 ) ) ; +sky130_fd_sc_hd__buf_8 FTB_35__34 ( .A ( chany_top_in[2] ) , + .X ( chany_bottom_out[2] ) ) ; sky130_fd_sc_hd__buf_8 FTB_36__35 ( .A ( chany_top_in[3] ) , .X ( chany_bottom_out[3] ) ) ; -sky130_fd_sc_hd__buf_6 FTB_37__36 ( .A ( chany_top_in[4] ) , - .X ( ropt_net_123 ) ) ; +sky130_fd_sc_hd__buf_8 FTB_37__36 ( .A ( chany_top_in[4] ) , + .X ( chany_bottom_out[4] ) ) ; sky130_fd_sc_hd__buf_8 FTB_38__37 ( .A ( chany_top_in[5] ) , .X ( chany_bottom_out[5] ) ) ; sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chany_top_in[6] ) , @@ -4032,37 +4038,37 @@ sky130_fd_sc_hd__buf_6 FTB_44__43 ( .A ( chany_top_in[11] ) , sky130_fd_sc_hd__buf_8 FTB_45__44 ( .A ( chany_top_in[12] ) , .X ( chany_bottom_out[12] ) ) ; sky130_fd_sc_hd__buf_6 FTB_46__45 ( .A ( chany_top_in[13] ) , - .X ( ropt_net_120 ) ) ; + .X ( ropt_net_116 ) ) ; sky130_fd_sc_hd__buf_6 FTB_47__46 ( .A ( chany_top_in[14] ) , - .X ( ropt_net_138 ) ) ; + .X ( ropt_net_126 ) ) ; sky130_fd_sc_hd__buf_8 FTB_48__47 ( .A ( chany_top_in[15] ) , .X ( chany_bottom_out[15] ) ) ; sky130_fd_sc_hd__buf_8 FTB_49__48 ( .A ( chany_top_in[16] ) , .X ( chany_bottom_out[16] ) ) ; sky130_fd_sc_hd__buf_6 FTB_50__49 ( .A ( chany_top_in[17] ) , - .X ( ropt_net_125 ) ) ; + .X ( ropt_net_119 ) ) ; sky130_fd_sc_hd__buf_8 FTB_51__50 ( .A ( chany_top_in[18] ) , .X ( chany_bottom_out[18] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_52__51 ( .A ( chany_top_in[19] ) , +sky130_fd_sc_hd__buf_6 FTB_52__51 ( .A ( chany_top_in[19] ) , .X ( chany_bottom_out[19] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_53__52 ( .A ( chany_top_in[20] ) , - .X ( chany_bottom_out[20] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_53__52 ( .A ( chany_top_in[20] ) , + .X ( ropt_net_123 ) ) ; sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chany_top_in[21] ) , .X ( chany_bottom_out[21] ) ) ; sky130_fd_sc_hd__buf_6 FTB_55__54 ( .A ( chany_top_in[22] ) , - .X ( ropt_net_137 ) ) ; + .X ( chany_bottom_out[22] ) ) ; sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chany_top_in[23] ) , .X ( chany_bottom_out[23] ) ) ; sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chany_top_in[24] ) , .X ( chany_bottom_out[24] ) ) ; -sky130_fd_sc_hd__buf_6 FTB_58__57 ( .A ( chany_top_in[25] ) , +sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chany_top_in[25] ) , .X ( chany_bottom_out[25] ) ) ; sky130_fd_sc_hd__buf_6 FTB_59__58 ( .A ( chany_top_in[26] ) , .X ( chany_bottom_out[26] ) ) ; sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( chany_top_in[27] ) , .X ( chany_bottom_out[27] ) ) ; sky130_fd_sc_hd__buf_6 FTB_61__60 ( .A ( chany_top_in[28] ) , - .X ( ropt_net_121 ) ) ; + .X ( ropt_net_114 ) ) ; sky130_fd_sc_hd__buf_8 FTB_62__61 ( .A ( chany_top_in[29] ) , .X ( chany_bottom_out[29] ) ) ; sky130_fd_sc_hd__buf_6 FTB_63__62 ( @@ -4070,34 +4076,34 @@ sky130_fd_sc_hd__buf_6 FTB_63__62 ( .X ( right_width_0_height_0__pin_1_upper[0] ) ) ; sky130_fd_sc_hd__conb_1 optlc_67 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , .HI ( optlc_net_66 ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1263 ( .A ( ropt_net_120 ) , - .X ( chany_bottom_out[13] ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1264 ( .A ( ropt_net_121 ) , +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1258 ( .A ( ropt_net_114 ) , .X ( chany_bottom_out[28] ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1265 ( .A ( ropt_net_122 ) , - .X ( chany_top_out[22] ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1266 ( .A ( ropt_net_123 ) , - .X ( chany_bottom_out[4] ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1267 ( .A ( ropt_net_124 ) , - .X ( chany_top_out[23] ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1268 ( .A ( ropt_net_125 ) , +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1259 ( .A ( ropt_net_115 ) , + .X ( chany_top_out[27] ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1260 ( .A ( ropt_net_116 ) , + .X ( chany_bottom_out[13] ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1261 ( .A ( ropt_net_117 ) , + .X ( chany_top_out[13] ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1262 ( .A ( ropt_net_118 ) , + .X ( chany_top_out[5] ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1263 ( .A ( ropt_net_119 ) , .X ( chany_bottom_out[17] ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1270 ( .A ( ropt_net_127 ) , - .X ( chany_top_out[19] ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1271 ( .A ( ropt_net_128 ) , - .X ( chany_top_out[8] ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1272 ( .A ( ropt_net_129 ) , - .X ( chany_top_out[14] ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1275 ( .A ( ropt_net_132 ) , - .X ( chany_bottom_out[2] ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1276 ( .A ( ropt_net_133 ) , +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1264 ( .A ( ropt_net_120 ) , + .X ( chany_top_out[2] ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1265 ( .A ( ropt_net_121 ) , .X ( chany_top_out[15] ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1277 ( .A ( ropt_net_134 ) , - .X ( chany_top_out[1] ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1280 ( .A ( ropt_net_137 ) , - .X ( chany_bottom_out[22] ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1281 ( .A ( ropt_net_138 ) , +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1266 ( .A ( ropt_net_122 ) , + .X ( chany_top_out[23] ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1267 ( .A ( ropt_net_123 ) , + .X ( chany_bottom_out[20] ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1268 ( .A ( ropt_net_124 ) , + .X ( chany_top_out[20] ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1269 ( .A ( ropt_net_125 ) , + .X ( chany_top_out[16] ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1270 ( .A ( ropt_net_126 ) , .X ( chany_bottom_out[14] ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1280 ( .A ( ropt_net_136 ) , + .X ( chany_top_out[8] ) ) ; endmodule @@ -6250,7 +6256,7 @@ sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_87 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_88 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -6273,7 +6279,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; @@ -6325,8 +6331,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -6356,6 +6360,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_87 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .X ( out[0] ) ) ; endmodule @@ -6377,7 +6383,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; @@ -6429,6 +6435,59 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_85 ( .A ( BUF_net_86 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_86 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .Y ( BUF_net_86 ) ) ; +endmodule + + +module cbx_1__1__mux_tree_tapbuf_size10_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , @@ -6463,58 +6522,6 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( endmodule -module cbx_1__1__mux_tree_tapbuf_size10_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_86 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , - .X ( out[0] ) ) ; -endmodule - - module cbx_1__1__mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , p0 ) ; input [0:9] in ; input [0:3] sram ; @@ -6715,7 +6722,7 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( copt_net_107 ) , +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( copt_net_101 ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; @@ -6724,22 +6731,16 @@ sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1326 ( .A ( copt_net_101 ) , - .X ( copt_net_100 ) ) ; -sky130_fd_sc_hd__buf_2 copt_h_inst_1327 ( .A ( ccff_head[0] ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1323 ( .A ( ccff_head[0] ) , + .X ( copt_net_95 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1324 ( .A ( copt_net_95 ) , + .X ( copt_net_96 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1325 ( .A ( copt_net_96 ) , + .X ( copt_net_97 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1326 ( .A ( copt_net_97 ) , + .X ( copt_net_98 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1329 ( .A ( copt_net_98 ) , .X ( copt_net_101 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1328 ( .A ( copt_net_100 ) , - .X ( copt_net_102 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 copt_h_inst_1329 ( .A ( copt_net_102 ) , - .X ( copt_net_103 ) ) ; -sky130_fd_sc_hd__buf_1 copt_h_inst_1333 ( .A ( copt_net_103 ) , - .X ( copt_net_104 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1334 ( .A ( copt_net_106 ) , - .X ( copt_net_105 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 copt_h_inst_1335 ( .A ( copt_net_104 ) , - .X ( copt_net_106 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1346 ( .A ( copt_net_105 ) , - .X ( copt_net_107 ) ) ; endmodule @@ -6798,9 +6799,9 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_84 ( .A ( BUF_net_85 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_85 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , - .Y ( BUF_net_85 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_83 ( .A ( BUF_net_84 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_84 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , + .Y ( BUF_net_84 ) ) ; endmodule @@ -6859,7 +6860,7 @@ sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_83 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_82 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -6884,7 +6885,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; @@ -6979,7 +6980,7 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_82 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_81 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -7159,9 +7160,8 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_91 ( .A ( BUF_net_92 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_4 BINV_R_92 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , - .Y ( BUF_net_92 ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_80 ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , + .X ( out[0] ) ) ; endmodule @@ -7185,7 +7185,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( +sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; @@ -7305,11 +7305,6 @@ input clk_3_E_in ; output clk_3_E_out ; output clk_3_W_out ; -wire ropt_net_130 ; -wire ropt_net_121 ; -wire ropt_net_132 ; -wire ropt_net_124 ; -wire ropt_net_125 ; wire [0:0] prog_clk ; wire prog_clk_0 ; wire [0:3] mux_tree_tapbuf_size10_0_sram ; @@ -7361,7 +7356,7 @@ cbx_1__1__mux_tree_tapbuf_size12_0 mux_top_ipin_0 ( .sram ( mux_tree_tapbuf_size12_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , - .out ( bottom_grid_pin_0_ ) , .p0 ( optlc_net_96 ) ) ; + .out ( bottom_grid_pin_0_ ) , .p0 ( optlc_net_92 ) ) ; cbx_1__1__mux_tree_tapbuf_size12_1 mux_top_ipin_2 ( .in ( { chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[5] , chanx_left_out[5] , chanx_right_out[8] , chanx_left_out[8] , @@ -7370,7 +7365,7 @@ cbx_1__1__mux_tree_tapbuf_size12_1 mux_top_ipin_2 ( .sram ( mux_tree_tapbuf_size12_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 , SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) , - .out ( bottom_grid_pin_2_ ) , .p0 ( optlc_net_95 ) ) ; + .out ( bottom_grid_pin_2_ ) , .p0 ( optlc_net_91 ) ) ; cbx_1__1__mux_tree_tapbuf_size12_2 mux_top_ipin_4 ( .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[4] , chanx_left_out[4] , chanx_right_out[10] , chanx_left_out[10] , @@ -7379,7 +7374,7 @@ cbx_1__1__mux_tree_tapbuf_size12_2 mux_top_ipin_4 ( .sram ( mux_tree_tapbuf_size12_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , - .out ( bottom_grid_pin_4_ ) , .p0 ( optlc_net_93 ) ) ; + .out ( bottom_grid_pin_4_ ) , .p0 ( optlc_net_89 ) ) ; cbx_1__1__mux_tree_tapbuf_size12_3 mux_top_ipin_6 ( .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] , chanx_left_out[3] , chanx_right_out[6] , chanx_left_out[6] , @@ -7388,7 +7383,7 @@ cbx_1__1__mux_tree_tapbuf_size12_3 mux_top_ipin_6 ( .sram ( mux_tree_tapbuf_size12_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) , - .out ( bottom_grid_pin_6_ ) , .p0 ( optlc_net_97 ) ) ; + .out ( bottom_grid_pin_6_ ) , .p0 ( optlc_net_92 ) ) ; cbx_1__1__mux_tree_tapbuf_size12_4 mux_top_ipin_8 ( .in ( { chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[5] , chanx_left_out[5] , chanx_right_out[8] , chanx_left_out[8] , @@ -7397,7 +7392,7 @@ cbx_1__1__mux_tree_tapbuf_size12_4 mux_top_ipin_8 ( .sram ( mux_tree_tapbuf_size12_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 , SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) , - .out ( bottom_grid_pin_8_ ) , .p0 ( optlc_net_95 ) ) ; + .out ( bottom_grid_pin_8_ ) , .p0 ( optlc_net_89 ) ) ; cbx_1__1__mux_tree_tapbuf_size12_5 mux_top_ipin_10 ( .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[4] , chanx_left_out[4] , chanx_right_out[10] , chanx_left_out[10] , @@ -7406,7 +7401,7 @@ cbx_1__1__mux_tree_tapbuf_size12_5 mux_top_ipin_10 ( .sram ( mux_tree_tapbuf_size12_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 , SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) , - .out ( bottom_grid_pin_10_ ) , .p0 ( optlc_net_93 ) ) ; + .out ( bottom_grid_pin_10_ ) , .p0 ( optlc_net_89 ) ) ; cbx_1__1__mux_tree_tapbuf_size12_6 mux_top_ipin_12 ( .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] , chanx_left_out[3] , chanx_right_out[6] , chanx_left_out[6] , @@ -7415,7 +7410,7 @@ cbx_1__1__mux_tree_tapbuf_size12_6 mux_top_ipin_12 ( .sram ( mux_tree_tapbuf_size12_6_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) , - .out ( bottom_grid_pin_12_ ) , .p0 ( optlc_net_97 ) ) ; + .out ( bottom_grid_pin_12_ ) , .p0 ( optlc_net_92 ) ) ; cbx_1__1__mux_tree_tapbuf_size12 mux_top_ipin_14 ( .in ( { chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[5] , chanx_left_out[5] , chanx_right_out[8] , chanx_left_out[8] , @@ -7424,7 +7419,7 @@ cbx_1__1__mux_tree_tapbuf_size12 mux_top_ipin_14 ( .sram ( mux_tree_tapbuf_size12_7_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 , SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) , - .out ( bottom_grid_pin_14_ ) , .p0 ( optlc_net_93 ) ) ; + .out ( bottom_grid_pin_14_ ) , .p0 ( optlc_net_91 ) ) ; cbx_1__1__mux_tree_tapbuf_size12_mem_0 mem_top_ipin_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size12_mem_0_ccff_tail ) , @@ -7472,7 +7467,7 @@ cbx_1__1__mux_tree_tapbuf_size10_0 mux_top_ipin_1 ( .sram ( mux_tree_tapbuf_size10_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 , SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) , - .out ( bottom_grid_pin_1_ ) , .p0 ( optlc_net_93 ) ) ; + .out ( bottom_grid_pin_1_ ) , .p0 ( optlc_net_89 ) ) ; cbx_1__1__mux_tree_tapbuf_size10_1 mux_top_ipin_3 ( .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] , chanx_left_out[3] , chanx_right_out[9] , chanx_left_out[9] , @@ -7481,7 +7476,7 @@ cbx_1__1__mux_tree_tapbuf_size10_1 mux_top_ipin_3 ( .sram ( mux_tree_tapbuf_size10_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 , SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) , - .out ( bottom_grid_pin_3_ ) , .p0 ( optlc_net_93 ) ) ; + .out ( bottom_grid_pin_3_ ) , .p0 ( optlc_net_92 ) ) ; cbx_1__1__mux_tree_tapbuf_size10_2 mux_top_ipin_5 ( .in ( { chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[5] , chanx_left_out[5] , chanx_right_out[11] , chanx_left_out[11] , @@ -7490,7 +7485,7 @@ cbx_1__1__mux_tree_tapbuf_size10_2 mux_top_ipin_5 ( .sram ( mux_tree_tapbuf_size10_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 , SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) , - .out ( bottom_grid_pin_5_ ) , .p0 ( optlc_net_95 ) ) ; + .out ( bottom_grid_pin_5_ ) , .p0 ( optlc_net_91 ) ) ; cbx_1__1__mux_tree_tapbuf_size10_3 mux_top_ipin_7 ( .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[4] , chanx_left_out[4] , chanx_right_out[7] , chanx_left_out[7] , @@ -7499,7 +7494,7 @@ cbx_1__1__mux_tree_tapbuf_size10_3 mux_top_ipin_7 ( .sram ( mux_tree_tapbuf_size10_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 , SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) , - .out ( bottom_grid_pin_7_ ) , .p0 ( optlc_net_93 ) ) ; + .out ( bottom_grid_pin_7_ ) , .p0 ( optlc_net_91 ) ) ; cbx_1__1__mux_tree_tapbuf_size10_4 mux_top_ipin_9 ( .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] , chanx_left_out[3] , chanx_right_out[9] , chanx_left_out[9] , @@ -7508,7 +7503,7 @@ cbx_1__1__mux_tree_tapbuf_size10_4 mux_top_ipin_9 ( .sram ( mux_tree_tapbuf_size10_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 , SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) , - .out ( bottom_grid_pin_9_ ) , .p0 ( optlc_net_96 ) ) ; + .out ( bottom_grid_pin_9_ ) , .p0 ( optlc_net_92 ) ) ; cbx_1__1__mux_tree_tapbuf_size10_5 mux_top_ipin_11 ( .in ( { chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[5] , chanx_left_out[5] , chanx_right_out[11] , chanx_left_out[11] , @@ -7517,7 +7512,7 @@ cbx_1__1__mux_tree_tapbuf_size10_5 mux_top_ipin_11 ( .sram ( mux_tree_tapbuf_size10_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 , SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) , - .out ( bottom_grid_pin_11_ ) , .p0 ( optlc_net_94 ) ) ; + .out ( bottom_grid_pin_11_ ) , .p0 ( optlc_net_90 ) ) ; cbx_1__1__mux_tree_tapbuf_size10_6 mux_top_ipin_13 ( .in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[4] , chanx_left_out[4] , chanx_right_out[13] , chanx_left_out[13] , @@ -7526,7 +7521,7 @@ cbx_1__1__mux_tree_tapbuf_size10_6 mux_top_ipin_13 ( .sram ( mux_tree_tapbuf_size10_6_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 , SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) , - .out ( bottom_grid_pin_13_ ) , .p0 ( optlc_net_94 ) ) ; + .out ( bottom_grid_pin_13_ ) , .p0 ( optlc_net_90 ) ) ; cbx_1__1__mux_tree_tapbuf_size10 mux_top_ipin_15 ( .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] , chanx_left_out[3] , chanx_right_out[6] , chanx_left_out[6] , @@ -7535,7 +7530,7 @@ cbx_1__1__mux_tree_tapbuf_size10 mux_top_ipin_15 ( .sram ( mux_tree_tapbuf_size10_7_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 , SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) , - .out ( bottom_grid_pin_15_ ) , .p0 ( optlc_net_97 ) ) ; + .out ( bottom_grid_pin_15_ ) , .p0 ( optlc_net_92 ) ) ; cbx_1__1__mux_tree_tapbuf_size10_mem_0 mem_top_ipin_1 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size12_mem_0_ccff_tail ) , @@ -7574,19 +7569,19 @@ cbx_1__1__mux_tree_tapbuf_size10_mem_6 mem_top_ipin_13 ( .pReset ( pReset ) , cbx_1__1__mux_tree_tapbuf_size10_mem mem_top_ipin_15 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size12_mem_7_ccff_tail ) , - .ccff_tail ( { copt_net_108 } ) , + .ccff_tail ( { copt_net_100 } ) , .mem_out ( mux_tree_tapbuf_size10_7_sram ) ) ; sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_W_in ) , .X ( pReset[0] ) ) ; sky130_fd_sc_hd__buf_4 pReset_W_FTB01 ( .A ( pReset_W_in ) , .X ( pReset_W_out ) ) ; -sky130_fd_sc_hd__bufbuf_16 pReset_S_FTB01 ( .A ( pReset_W_in ) , +sky130_fd_sc_hd__buf_4 pReset_S_FTB01 ( .A ( pReset_W_in ) , .X ( pReset_S_out ) ) ; sky130_fd_sc_hd__buf_4 pReset_E_FTB01 ( .A ( pReset_W_in ) , .X ( pReset_E_out ) ) ; sky130_fd_sc_hd__buf_2 prog_clk_0_FTB00 ( .A ( prog_clk_0_N_in ) , .X ( prog_clk[0] ) ) ; sky130_fd_sc_hd__clkbuf_1 prog_clk_0_W_FTB01 ( .A ( prog_clk_0_N_in ) , - .X ( ctsbuf_net_198 ) ) ; + .X ( ctsbuf_net_193 ) ) ; sky130_fd_sc_hd__bufbuf_16 prog_clk_1_N_FTB01 ( .A ( prog_clk_1_E_in ) , .X ( prog_clk_1_N_out ) ) ; sky130_fd_sc_hd__buf_4 prog_clk_1_S_FTB01 ( .A ( prog_clk_1_E_in ) , @@ -7594,21 +7589,23 @@ sky130_fd_sc_hd__buf_4 prog_clk_1_S_FTB01 ( .A ( prog_clk_1_E_in ) , sky130_fd_sc_hd__buf_4 prog_clk_2_W_FTB01 ( .A ( prog_clk_2_W_in ) , .X ( prog_clk_2_W_out ) ) ; sky130_fd_sc_hd__buf_4 prog_clk_2_E_FTB01 ( .A ( prog_clk_2_W_in ) , - .X ( prog_clk_2_E_out ) ) ; + .X ( aps_rename_505_ ) ) ; sky130_fd_sc_hd__buf_4 prog_clk_3_E_FTB01 ( .A ( prog_clk_3_E_in ) , - .X ( prog_clk_3_E_out ) ) ; + .X ( aps_rename_506_ ) ) ; sky130_fd_sc_hd__buf_4 prog_clk_3_W_FTB01 ( .A ( prog_clk_3_E_in ) , .X ( prog_clk_3_W_out ) ) ; sky130_fd_sc_hd__bufbuf_16 clk_1_N_FTB01 ( .A ( clk_1_E_in ) , .X ( clk_1_N_out ) ) ; -sky130_fd_sc_hd__buf_1 clk_1_S_FTB01 ( .A ( clk_1_E_in ) , .X ( net_net_88 ) ) ; +sky130_fd_sc_hd__buf_4 clk_1_S_FTB01 ( .A ( clk_1_E_in ) , + .X ( clk_1_S_out ) ) ; sky130_fd_sc_hd__buf_4 clk_2_W_FTB01 ( .A ( clk_2_W_in ) , .X ( clk_2_W_out ) ) ; sky130_fd_sc_hd__buf_4 clk_2_E_FTB01 ( .A ( clk_2_W_in ) , - .X ( clk_2_E_out ) ) ; + .X ( aps_rename_507_ ) ) ; sky130_fd_sc_hd__buf_4 clk_3_E_FTB01 ( .A ( clk_3_E_in ) , - .X ( clk_3_E_out ) ) ; -sky130_fd_sc_hd__buf_4 clk_3_W_FTB01 ( .A ( clk_3_E_in ) , .X ( ZBUF_39_0 ) ) ; + .X ( aps_rename_508_ ) ) ; +sky130_fd_sc_hd__buf_4 clk_3_W_FTB01 ( .A ( clk_3_E_in ) , + .X ( clk_3_W_out ) ) ; sky130_fd_sc_hd__buf_8 FTB_17__16 ( .A ( chanx_left_in[0] ) , .X ( chanx_right_out[0] ) ) ; sky130_fd_sc_hd__buf_8 FTB_18__17 ( .A ( chanx_left_in[1] ) , @@ -7627,8 +7624,8 @@ sky130_fd_sc_hd__buf_8 FTB_24__23 ( .A ( chanx_left_in[7] ) , .X ( chanx_right_out[7] ) ) ; sky130_fd_sc_hd__buf_8 FTB_25__24 ( .A ( chanx_left_in[8] ) , .X ( chanx_right_out[8] ) ) ; -sky130_fd_sc_hd__buf_6 FTB_26__25 ( .A ( chanx_left_in[9] ) , - .X ( ropt_net_130 ) ) ; +sky130_fd_sc_hd__buf_8 FTB_26__25 ( .A ( chanx_left_in[9] ) , + .X ( chanx_right_out[9] ) ) ; sky130_fd_sc_hd__buf_8 FTB_27__26 ( .A ( chanx_left_in[10] ) , .X ( chanx_right_out[10] ) ) ; sky130_fd_sc_hd__buf_8 FTB_28__27 ( .A ( chanx_left_in[11] ) , @@ -7655,8 +7652,8 @@ sky130_fd_sc_hd__buf_8 FTB_38__37 ( .A ( chanx_left_in[21] ) , .X ( chanx_right_out[21] ) ) ; sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chanx_left_in[22] ) , .X ( chanx_right_out[22] ) ) ; -sky130_fd_sc_hd__buf_1 FTB_40__39 ( .A ( chanx_left_in[23] ) , - .X ( ropt_net_121 ) ) ; +sky130_fd_sc_hd__buf_6 FTB_40__39 ( .A ( chanx_left_in[23] ) , + .X ( chanx_right_out[23] ) ) ; sky130_fd_sc_hd__buf_8 FTB_41__40 ( .A ( chanx_left_in[24] ) , .X ( chanx_right_out[24] ) ) ; sky130_fd_sc_hd__buf_8 FTB_42__41 ( .A ( chanx_left_in[25] ) , @@ -7715,8 +7712,8 @@ sky130_fd_sc_hd__buf_8 FTB_68__67 ( .A ( chanx_right_in[21] ) , .X ( chanx_left_out[21] ) ) ; sky130_fd_sc_hd__buf_8 FTB_69__68 ( .A ( chanx_right_in[22] ) , .X ( chanx_left_out[22] ) ) ; -sky130_fd_sc_hd__buf_1 FTB_70__69 ( .A ( chanx_right_in[23] ) , - .X ( ropt_net_132 ) ) ; +sky130_fd_sc_hd__buf_6 FTB_70__69 ( .A ( chanx_right_in[23] ) , + .X ( chanx_left_out[23] ) ) ; sky130_fd_sc_hd__buf_8 FTB_71__70 ( .A ( chanx_right_in[24] ) , .X ( chanx_left_out[24] ) ) ; sky130_fd_sc_hd__buf_8 FTB_72__71 ( .A ( chanx_right_in[25] ) , @@ -7729,55 +7726,34 @@ sky130_fd_sc_hd__buf_8 FTB_75__74 ( .A ( chanx_right_in[28] ) , .X ( chanx_left_out[28] ) ) ; sky130_fd_sc_hd__buf_8 FTB_76__75 ( .A ( chanx_right_in[29] ) , .X ( chanx_left_out[29] ) ) ; -sky130_fd_sc_hd__buf_1 FTB_77__76 ( .A ( SC_IN_TOP ) , .X ( ropt_net_124 ) ) ; +sky130_fd_sc_hd__buf_8 FTB_77__76 ( .A ( SC_IN_TOP ) , .X ( SC_OUT_BOT ) ) ; sky130_fd_sc_hd__buf_6 FTB_78__77 ( .A ( SC_IN_BOT ) , .X ( SC_OUT_TOP ) ) ; sky130_fd_sc_hd__buf_6 FTB_79__78 ( .A ( REGIN_FEEDTHROUGH ) , .X ( REGOUT_FEEDTHROUGH ) ) ; -sky130_fd_sc_hd__buf_1 FTB_80__79 ( .A ( CIN_FEEDTHROUGH ) , - .X ( ropt_net_125 ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_88 ( .A ( net_net_88 ) , .X ( clk_1_S_out ) ) ; -sky130_fd_sc_hd__conb_1 optlc_95 ( .LO ( SYNOPSYS_UNCONNECTED_65 ) , - .HI ( optlc_net_93 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_97 ( .LO ( SYNOPSYS_UNCONNECTED_66 ) , - .HI ( optlc_net_94 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_100 ( .LO ( SYNOPSYS_UNCONNECTED_67 ) , - .HI ( optlc_net_95 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_102 ( .LO ( SYNOPSYS_UNCONNECTED_68 ) , - .HI ( optlc_net_96 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_104 ( .LO ( SYNOPSYS_UNCONNECTED_69 ) , - .HI ( optlc_net_97 ) ) ; -sky130_fd_sc_hd__buf_6 ZBUF_39_inst_1345 ( .A ( ZBUF_39_0 ) , - .X ( clk_3_W_out ) ) ; -sky130_fd_sc_hd__buf_6 cts_buf_3531232 ( .A ( ctsbuf_net_198 ) , - .X ( prog_clk_0_W_out ) ) ; -sky130_fd_sc_hd__bufbuf_8 copt_h_inst_1353 ( .A ( copt_net_109 ) , - .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1354 ( .A ( ropt_net_133 ) , - .X ( copt_net_109 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1355 ( .A ( copt_net_111 ) , - .X ( copt_net_110 ) ) ; -sky130_fd_sc_hd__buf_2 copt_h_inst_1356 ( .A ( copt_net_108 ) , - .X ( copt_net_111 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1357 ( .A ( copt_net_110 ) , - .X ( copt_net_112 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1358 ( .A ( ropt_net_135 ) , - .X ( copt_net_113 ) ) ; -sky130_fd_sc_hd__buf_6 ropt_mt_inst_1371 ( .A ( ropt_net_124 ) , - .X ( SC_OUT_BOT ) ) ; -sky130_fd_sc_hd__buf_6 ropt_mt_inst_1372 ( .A ( ropt_net_125 ) , +sky130_fd_sc_hd__buf_6 FTB_80__79 ( .A ( CIN_FEEDTHROUGH ) , .X ( COUT_FEEDTHROUGH ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1377 ( .A ( ropt_net_130 ) , - .X ( chanx_right_out[9] ) ) ; -sky130_fd_sc_hd__buf_6 ropt_mt_inst_1379 ( .A ( ropt_net_132 ) , - .X ( chanx_left_out[23] ) ) ; -sky130_fd_sc_hd__buf_1 ropt_h_inst_1380 ( .A ( copt_net_113 ) , - .X ( ropt_net_133 ) ) ; -sky130_fd_sc_hd__buf_1 ropt_h_inst_1381 ( .A ( copt_net_112 ) , - .X ( ropt_net_134 ) ) ; -sky130_fd_sc_hd__buf_6 ropt_mt_inst_1367 ( .A ( ropt_net_121 ) , - .X ( chanx_right_out[23] ) ) ; -sky130_fd_sc_hd__buf_1 ropt_h_inst_1382 ( .A ( ropt_net_134 ) , - .X ( ropt_net_135 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_91 ( .LO ( SYNOPSYS_UNCONNECTED_65 ) , + .HI ( optlc_net_89 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_93 ( .LO ( SYNOPSYS_UNCONNECTED_66 ) , + .HI ( optlc_net_90 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_95 ( .LO ( SYNOPSYS_UNCONNECTED_67 ) , + .HI ( optlc_net_91 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_97 ( .LO ( SYNOPSYS_UNCONNECTED_68 ) , + .HI ( optlc_net_92 ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_6_f_inst_602 ( .A ( aps_rename_507_ ) , + .X ( clk_2_E_out ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_6_f_inst_603 ( .A ( aps_rename_505_ ) , + .X ( prog_clk_2_E_out ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_240_f_inst_604 ( .A ( aps_rename_508_ ) , + .X ( clk_3_E_out ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_39_inst_605 ( .A ( aps_rename_506_ ) , + .X ( prog_clk_3_E_out ) ) ; +sky130_fd_sc_hd__buf_6 copt_h_inst_1328 ( .A ( copt_net_102 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__buf_6 cts_buf_3531229 ( .A ( ctsbuf_net_193 ) , + .X ( prog_clk_0_W_out ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1330 ( .A ( copt_net_100 ) , + .X ( copt_net_102 ) ) ; endmodule @@ -8549,7 +8525,7 @@ sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) , .TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) ) ; sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) , .TE_B ( SOC_DIR ) , .Z ( SOC_OUT ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_89 ( .A ( net_net_89 ) , .X ( SOC_DIR ) ) ; +sky130_fd_sc_hd__buf_8 BUFT_RR_89 ( .A ( net_net_89 ) , .X ( SOC_DIR ) ) ; endmodule @@ -9714,7 +9690,7 @@ sky130_fd_sc_hd__buf_8 FTB_37__36 ( .A ( chanx_left_in[18] ) , .X ( chanx_right_out[18] ) ) ; sky130_fd_sc_hd__buf_8 FTB_38__37 ( .A ( chanx_left_in[19] ) , .X ( chanx_right_out[19] ) ) ; -sky130_fd_sc_hd__buf_12 FTB_39__38 ( .A ( chanx_left_in[20] ) , +sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chanx_left_in[20] ) , .X ( chanx_right_out[20] ) ) ; sky130_fd_sc_hd__buf_8 FTB_40__39 ( .A ( chanx_left_in[21] ) , .X ( chanx_right_out[21] ) ) ; @@ -9925,9 +9901,9 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_131 ( .A ( BUF_net_132 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_132 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .Y ( BUF_net_132 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_139 ( .A ( BUF_net_140 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_140 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .Y ( BUF_net_140 ) ) ; endmodule @@ -9966,8 +9942,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , @@ -9976,6 +9950,9 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_137 ( .A ( BUF_net_138 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_138 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .Y ( BUF_net_138 ) ) ; endmodule @@ -9998,9 +9975,9 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_129 ( .A ( BUF_net_130 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_130 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .Y ( BUF_net_130 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_135 ( .A ( BUF_net_136 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_136 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .Y ( BUF_net_136 ) ) ; endmodule @@ -10012,15 +9989,14 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -wire copt_net_172 ; - sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( copt_net_172 ) ) ; -sky130_fd_sc_hd__buf_6 FTB_49__48 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1348 ( .A ( copt_net_172 ) , - .X ( mem_out[1] ) ) ; + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_49__48 ( .A ( copt_net_165 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1335 ( .A ( mem_out[1] ) , + .X ( copt_net_165 ) ) ; endmodule @@ -10610,13 +10586,14 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_134 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_134 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_149 ( .A ( BUF_net_134 ) , .Y ( out[0] ) ) ; endmodule @@ -10655,9 +10632,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_128 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_128 ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_151 ( .A ( BUF_net_128 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_131 ( .A ( BUF_net_132 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_132 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_132 ) ) ; endmodule @@ -10676,9 +10653,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_149 ( .A ( BUF_net_150 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_150 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_150 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_129 ( .A ( BUF_net_130 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_130 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_130 ) ) ; endmodule @@ -10697,9 +10674,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_147 ( .A ( BUF_net_148 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_148 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_148 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_127 ( .A ( BUF_net_128 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_128 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_128 ) ) ; endmodule @@ -10713,6 +10690,48 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_125 ( .A ( BUF_net_126 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_126 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_126 ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_30 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_123 ( .A ( BUF_net_124 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_124 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_124 ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_29 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , @@ -10724,7 +10743,7 @@ sky130_fd_sc_hd__inv_1 BINV_R_122 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , endmodule -module sb_2__2__mux_tree_tapbuf_size2_30 ( in , sram , sram_inv , out , p0 ) ; +module sb_2__2__mux_tree_tapbuf_size2_28 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -10745,48 +10764,6 @@ sky130_fd_sc_hd__inv_1 BINV_R_120 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , endmodule -module sb_2__2__mux_tree_tapbuf_size2_29 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_117 ( .A ( BUF_net_118 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_118 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_118 ) ) ; -endmodule - - -module sb_2__2__mux_tree_tapbuf_size2_28 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_145 ( .A ( BUF_net_146 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_146 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_146 ) ) ; -endmodule - - module sb_2__2__mux_tree_tapbuf_size2_27 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; @@ -10822,9 +10799,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_113 ( .A ( BUF_net_114 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_114 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_114 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_117 ( .A ( BUF_net_118 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_118 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_118 ) ) ; endmodule @@ -10843,9 +10820,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_111 ( .A ( BUF_net_112 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_112 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_112 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_115 ( .A ( BUF_net_116 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_116 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_116 ) ) ; endmodule @@ -10864,9 +10841,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_109 ( .A ( BUF_net_110 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_110 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_110 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_113 ( .A ( BUF_net_114 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_114 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_114 ) ) ; endmodule @@ -10880,13 +10857,14 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_147 ( .A ( BUF_net_148 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_148 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_148 ) ) ; endmodule @@ -10900,13 +10878,13 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_108 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .X ( out[0] ) ) ; endmodule @@ -10920,6 +10898,26 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_110 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) ) ; +endmodule + + +module sb_2__2__mux_tree_tapbuf_size2_20 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , @@ -10930,26 +10928,6 @@ sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module sb_2__2__mux_tree_tapbuf_size2_20 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_107 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .X ( out[0] ) ) ; -endmodule - - module sb_2__2__mux_tree_tapbuf_size2_19 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; @@ -10965,9 +10943,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_105 ( .A ( BUF_net_106 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_106 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_106 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_108 ( .A ( BUF_net_109 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_109 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_109 ) ) ; endmodule @@ -10986,9 +10964,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_103 ( .A ( BUF_net_104 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_104 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_104 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_106 ( .A ( BUF_net_107 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_107 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_107 ) ) ; endmodule @@ -11007,9 +10985,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_101 ( .A ( BUF_net_102 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_102 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_102 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_104 ( .A ( BUF_net_105 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_105 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_105 ) ) ; endmodule @@ -11043,13 +11021,14 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_102 ( .A ( BUF_net_103 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_103 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_103 ) ) ; endmodule @@ -11068,9 +11047,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_99 ( .A ( BUF_net_100 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_100 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_100 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_100 ( .A ( BUF_net_101 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_101 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_101 ) ) ; endmodule @@ -11089,9 +11068,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_97 ( .A ( BUF_net_98 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_98 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_98 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_98 ( .A ( BUF_net_99 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_99 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_99 ) ) ; endmodule @@ -11110,9 +11089,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_95 ( .A ( BUF_net_96 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_96 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_96 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_96 ( .A ( BUF_net_97 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_97 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_97 ) ) ; endmodule @@ -11126,13 +11105,14 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_94 ( .A ( BUF_net_95 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_95 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_95 ) ) ; endmodule @@ -11146,14 +11126,13 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_93 ( .A ( BUF_net_94 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_94 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_94 ) ) ; endmodule @@ -11167,13 +11146,13 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_93 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) ) ; endmodule @@ -11192,9 +11171,8 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_91 ( .A ( BUF_net_92 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_92 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_92 ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_92 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) ) ; endmodule @@ -11213,9 +11191,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_89 ( .A ( BUF_net_90 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_90 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_90 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_90 ( .A ( BUF_net_91 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_91 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_91 ) ) ; endmodule @@ -11234,9 +11212,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_87 ( .A ( BUF_net_88 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_88 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_88 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_88 ( .A ( BUF_net_89 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_89 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_89 ) ) ; endmodule @@ -11255,9 +11233,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_85 ( .A ( BUF_net_86 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_86 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_86 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_86 ( .A ( BUF_net_87 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_87 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_87 ) ) ; endmodule @@ -11276,9 +11254,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_83 ( .A ( BUF_net_84 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_84 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_84 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_84 ( .A ( BUF_net_85 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_85 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_85 ) ) ; endmodule @@ -11297,9 +11275,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_81 ( .A ( BUF_net_82 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_82 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_82 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_82 ( .A ( BUF_net_83 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_83 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_83 ) ) ; endmodule @@ -11318,9 +11296,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_79 ( .A ( BUF_net_80 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_80 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_80 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_80 ( .A ( BUF_net_81 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_81 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_81 ) ) ; endmodule @@ -11339,7 +11317,7 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_78 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_79 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -11354,13 +11332,13 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_77 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .X ( out[0] ) ) ; endmodule @@ -11570,35 +11548,35 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_207 ) , +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_195 ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1339 ( .A ( copt_net_166 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1326 ( .A ( ccff_head[0] ) , + .X ( copt_net_156 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1327 ( .A ( copt_net_156 ) , + .X ( copt_net_157 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1328 ( .A ( copt_net_157 ) , + .X ( copt_net_158 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1329 ( .A ( copt_net_158 ) , + .X ( copt_net_159 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1330 ( .A ( ropt_net_198 ) , + .X ( copt_net_160 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1331 ( .A ( copt_net_160 ) , .X ( copt_net_161 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1340 ( .A ( ccff_head[0] ) , - .X ( copt_net_162 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1341 ( .A ( copt_net_161 ) , - .X ( copt_net_163 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1342 ( .A ( copt_net_162 ) , - .X ( copt_net_164 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1343 ( .A ( copt_net_163 ) , - .X ( copt_net_165 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1344 ( .A ( copt_net_164 ) , - .X ( copt_net_166 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1378 ( .A ( copt_net_165 ) , - .X ( ropt_net_203 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1379 ( .A ( ropt_net_205 ) , - .X ( ropt_net_204 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1380 ( .A ( ropt_net_203 ) , - .X ( ropt_net_205 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1381 ( .A ( ropt_net_204 ) , - .X ( ropt_net_206 ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 ropt_h_inst_1382 ( .A ( ropt_net_206 ) , - .X ( ropt_net_207 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1365 ( .A ( copt_net_161 ) , + .X ( ropt_net_195 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1366 ( .A ( copt_net_159 ) , + .X ( ropt_net_196 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1367 ( .A ( ropt_net_196 ) , + .X ( ropt_net_197 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1368 ( .A ( ropt_net_199 ) , + .X ( ropt_net_198 ) ) ; +sky130_fd_sc_hd__buf_1 ropt_h_inst_1369 ( .A ( ropt_net_197 ) , + .X ( ropt_net_199 ) ) ; endmodule @@ -11653,9 +11631,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_143 ( .A ( BUF_net_144 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_144 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .Y ( BUF_net_144 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_77 ( .A ( BUF_net_78 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_78 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_78 ) ) ; endmodule @@ -11682,9 +11660,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_73 ( .A ( BUF_net_74 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_74 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .Y ( BUF_net_74 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_75 ( .A ( BUF_net_76 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_76 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_76 ) ) ; endmodule @@ -11700,8 +11678,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , @@ -11709,10 +11685,13 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_74 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_74 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_141 ( .A ( BUF_net_74 ) , .Y ( out[0] ) ) ; endmodule @@ -11824,8 +11803,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_69 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .X ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_68 ( .A ( BUF_net_69 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_69 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_69 ) ) ; endmodule @@ -11852,9 +11832,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_67 ( .A ( BUF_net_68 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_68 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .Y ( BUF_net_68 ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_67 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .X ( out[0] ) ) ; endmodule @@ -11986,7 +11965,7 @@ output SC_OUT_BOT ; input pReset_W_in ; input prog_clk_0_S_in ; -wire ropt_net_182 ; +wire ropt_net_177 ; wire [0:0] prog_clk ; wire prog_clk_0 ; wire [0:1] mux_tree_tapbuf_size2_0_sram ; @@ -12103,84 +12082,84 @@ sb_2__2__mux_tree_tapbuf_size4_0 mux_bottom_track_1 ( .sram ( mux_tree_tapbuf_size4_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 } ) , - .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_153 ) ) ; + .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_154 ) ) ; sb_2__2__mux_tree_tapbuf_size4_1 mux_bottom_track_3 ( .in ( { bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_47_[0] , bottom_left_grid_pin_50_[0] , chanx_left_in[2] } ) , .sram ( mux_tree_tapbuf_size4_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 } ) , - .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_153 ) ) ; + .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_154 ) ) ; sb_2__2__mux_tree_tapbuf_size4_2 mux_bottom_track_5 ( .in ( { bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_48_[0] , bottom_left_grid_pin_51_[0] , chanx_left_in[3] } ) , .sram ( mux_tree_tapbuf_size4_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 , SYNOPSYS_UNCONNECTED_9 } ) , - .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_153 ) ) ; + .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_154 ) ) ; sb_2__2__mux_tree_tapbuf_size4_3 mux_bottom_track_7 ( .in ( { bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_46_[0] , bottom_left_grid_pin_49_[0] , chanx_left_in[4] } ) , .sram ( mux_tree_tapbuf_size4_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , - .out ( chany_bottom_out[3] ) , .p0 ( optlc_net_153 ) ) ; + .out ( chany_bottom_out[3] ) , .p0 ( optlc_net_154 ) ) ; sb_2__2__mux_tree_tapbuf_size4_4 mux_bottom_track_9 ( .in ( { bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_47_[0] , bottom_left_grid_pin_50_[0] , chanx_left_in[5] } ) , .sram ( mux_tree_tapbuf_size4_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , SYNOPSYS_UNCONNECTED_15 } ) , - .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_158 ) ) ; + .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_155 ) ) ; sb_2__2__mux_tree_tapbuf_size4_5 mux_bottom_track_11 ( .in ( { bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_48_[0] , bottom_left_grid_pin_51_[0] , chanx_left_in[6] } ) , .sram ( mux_tree_tapbuf_size4_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_16 , SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 } ) , - .out ( chany_bottom_out[5] ) , .p0 ( optlc_net_153 ) ) ; + .out ( chany_bottom_out[5] ) , .p0 ( optlc_net_155 ) ) ; sb_2__2__mux_tree_tapbuf_size4_6 mux_left_track_1 ( .in ( { chany_bottom_in[29] , left_top_grid_pin_1_[0] , left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size4_6_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 , SYNOPSYS_UNCONNECTED_21 } ) , - .out ( chanx_left_out[0] ) , .p0 ( optlc_net_154 ) ) ; + .out ( chanx_left_out[0] ) , .p0 ( optlc_net_151 ) ) ; sb_2__2__mux_tree_tapbuf_size4_7 mux_left_track_3 ( .in ( { chany_bottom_in[0] , left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_42_[0] } ) , .sram ( mux_tree_tapbuf_size4_7_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_22 , SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) , - .out ( chanx_left_out[1] ) , .p0 ( optlc_net_156 ) ) ; + .out ( chanx_left_out[1] ) , .p0 ( optlc_net_151 ) ) ; sb_2__2__mux_tree_tapbuf_size4_8 mux_left_track_5 ( .in ( { chany_bottom_in[1] , left_bottom_grid_pin_37_[0] , left_bottom_grid_pin_40_[0] , left_bottom_grid_pin_43_[0] } ) , .sram ( mux_tree_tapbuf_size4_8_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , SYNOPSYS_UNCONNECTED_27 } ) , - .out ( chanx_left_out[2] ) , .p0 ( optlc_net_159 ) ) ; + .out ( chanx_left_out[2] ) , .p0 ( optlc_net_151 ) ) ; sb_2__2__mux_tree_tapbuf_size4_9 mux_left_track_7 ( .in ( { chany_bottom_in[2] , left_top_grid_pin_1_[0] , left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size4_9_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_28 , SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 } ) , - .out ( chanx_left_out[3] ) , .p0 ( optlc_net_155 ) ) ; + .out ( chanx_left_out[3] ) , .p0 ( optlc_net_151 ) ) ; sb_2__2__mux_tree_tapbuf_size4_10 mux_left_track_9 ( .in ( { chany_bottom_in[3] , left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_42_[0] } ) , .sram ( mux_tree_tapbuf_size4_10_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 , SYNOPSYS_UNCONNECTED_33 } ) , - .out ( chanx_left_out[4] ) , .p0 ( optlc_net_156 ) ) ; + .out ( chanx_left_out[4] ) , .p0 ( optlc_net_151 ) ) ; sb_2__2__mux_tree_tapbuf_size4 mux_left_track_11 ( .in ( { chany_bottom_in[4] , left_bottom_grid_pin_37_[0] , left_bottom_grid_pin_40_[0] , left_bottom_grid_pin_43_[0] } ) , .sram ( mux_tree_tapbuf_size4_11_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_34 , SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) , - .out ( chanx_left_out[5] ) , .p0 ( optlc_net_159 ) ) ; + .out ( chanx_left_out[5] ) , .p0 ( optlc_net_151 ) ) ; sb_2__2__mux_tree_tapbuf_size4_mem_0 mem_bottom_track_1 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , @@ -12244,187 +12223,187 @@ sb_2__2__mux_tree_tapbuf_size2_0 mux_bottom_track_13 ( .in ( { bottom_right_grid_pin_1_[0] , chanx_left_in[7] } ) , .sram ( mux_tree_tapbuf_size2_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 } ) , - .out ( chany_bottom_out[6] ) , .p0 ( optlc_net_157 ) ) ; + .out ( chany_bottom_out[6] ) , .p0 ( optlc_net_152 ) ) ; sb_2__2__mux_tree_tapbuf_size2_1 mux_bottom_track_15 ( .in ( { bottom_left_grid_pin_44_[0] , chanx_left_in[8] } ) , .sram ( mux_tree_tapbuf_size2_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) , - .out ( chany_bottom_out[7] ) , .p0 ( optlc_net_158 ) ) ; + .out ( chany_bottom_out[7] ) , .p0 ( optlc_net_152 ) ) ; sb_2__2__mux_tree_tapbuf_size2_2 mux_bottom_track_17 ( .in ( { bottom_left_grid_pin_45_[0] , chanx_left_in[9] } ) , .sram ( mux_tree_tapbuf_size2_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 } ) , - .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_155 ) ) ; + .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_151 ) ) ; sb_2__2__mux_tree_tapbuf_size2_3 mux_bottom_track_19 ( .in ( { bottom_left_grid_pin_46_[0] , chanx_left_in[10] } ) , .sram ( mux_tree_tapbuf_size2_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) , - .out ( chany_bottom_out[9] ) , .p0 ( optlc_net_155 ) ) ; + .out ( chany_bottom_out[9] ) , .p0 ( optlc_net_151 ) ) ; sb_2__2__mux_tree_tapbuf_size2_4 mux_bottom_track_21 ( .in ( { bottom_left_grid_pin_47_[0] , chanx_left_in[11] } ) , .sram ( mux_tree_tapbuf_size2_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 } ) , - .out ( chany_bottom_out[10] ) , .p0 ( optlc_net_154 ) ) ; + .out ( chany_bottom_out[10] ) , .p0 ( optlc_net_151 ) ) ; sb_2__2__mux_tree_tapbuf_size2_5 mux_bottom_track_23 ( .in ( { bottom_left_grid_pin_48_[0] , chanx_left_in[12] } ) , .sram ( mux_tree_tapbuf_size2_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) , - .out ( chany_bottom_out[11] ) , .p0 ( optlc_net_153 ) ) ; + .out ( chany_bottom_out[11] ) , .p0 ( optlc_net_154 ) ) ; sb_2__2__mux_tree_tapbuf_size2_6 mux_bottom_track_25 ( .in ( { bottom_left_grid_pin_49_[0] , chanx_left_in[13] } ) , .sram ( mux_tree_tapbuf_size2_6_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 } ) , - .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_153 ) ) ; + .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_151 ) ) ; sb_2__2__mux_tree_tapbuf_size2_7 mux_bottom_track_27 ( .in ( { bottom_left_grid_pin_50_[0] , chanx_left_in[14] } ) , .sram ( mux_tree_tapbuf_size2_7_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) , - .out ( chany_bottom_out[13] ) , .p0 ( optlc_net_155 ) ) ; + .out ( chany_bottom_out[13] ) , .p0 ( optlc_net_151 ) ) ; sb_2__2__mux_tree_tapbuf_size2_8 mux_bottom_track_39 ( .in ( { bottom_left_grid_pin_44_[0] , chanx_left_in[20] } ) , .sram ( mux_tree_tapbuf_size2_8_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 } ) , - .out ( chany_bottom_out[19] ) , .p0 ( optlc_net_154 ) ) ; + .out ( chany_bottom_out[19] ) , .p0 ( optlc_net_152 ) ) ; sb_2__2__mux_tree_tapbuf_size2_9 mux_bottom_track_41 ( .in ( { bottom_left_grid_pin_45_[0] , chanx_left_in[21] } ) , .sram ( mux_tree_tapbuf_size2_9_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) , - .out ( chany_bottom_out[20] ) , .p0 ( optlc_net_153 ) ) ; + .out ( chany_bottom_out[20] ) , .p0 ( optlc_net_152 ) ) ; sb_2__2__mux_tree_tapbuf_size2_10 mux_bottom_track_43 ( .in ( { bottom_left_grid_pin_46_[0] , chanx_left_in[22] } ) , .sram ( mux_tree_tapbuf_size2_10_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 } ) , - .out ( chany_bottom_out[21] ) , .p0 ( optlc_net_157 ) ) ; + .out ( chany_bottom_out[21] ) , .p0 ( optlc_net_152 ) ) ; sb_2__2__mux_tree_tapbuf_size2_11 mux_bottom_track_47 ( .in ( { bottom_left_grid_pin_48_[0] , chanx_left_in[24] } ) , .sram ( mux_tree_tapbuf_size2_11_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) , - .out ( chany_bottom_out[23] ) , .p0 ( optlc_net_153 ) ) ; + .out ( chany_bottom_out[23] ) , .p0 ( optlc_net_155 ) ) ; sb_2__2__mux_tree_tapbuf_size2_12 mux_bottom_track_49 ( .in ( { bottom_left_grid_pin_49_[0] , chanx_left_in[25] } ) , .sram ( mux_tree_tapbuf_size2_12_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 } ) , - .out ( chany_bottom_out[24] ) , .p0 ( optlc_net_153 ) ) ; + .out ( chany_bottom_out[24] ) , .p0 ( optlc_net_154 ) ) ; sb_2__2__mux_tree_tapbuf_size2_13 mux_bottom_track_51 ( .in ( { bottom_left_grid_pin_50_[0] , chanx_left_in[26] } ) , .sram ( mux_tree_tapbuf_size2_13_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) , - .out ( chany_bottom_out[25] ) , .p0 ( optlc_net_155 ) ) ; + .out ( chany_bottom_out[25] ) , .p0 ( optlc_net_151 ) ) ; sb_2__2__mux_tree_tapbuf_size2_14 mux_bottom_track_53 ( .in ( { bottom_left_grid_pin_51_[0] , chanx_left_in[27] } ) , .sram ( mux_tree_tapbuf_size2_14_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 } ) , - .out ( chany_bottom_out[26] ) , .p0 ( optlc_net_155 ) ) ; + .out ( chany_bottom_out[26] ) , .p0 ( optlc_net_151 ) ) ; sb_2__2__mux_tree_tapbuf_size2_15 mux_left_track_13 ( .in ( { chany_bottom_in[5] , left_top_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size2_15_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 } ) , - .out ( chanx_left_out[6] ) , .p0 ( optlc_net_160 ) ) ; + .out ( chanx_left_out[6] ) , .p0 ( optlc_net_153 ) ) ; sb_2__2__mux_tree_tapbuf_size2_16 mux_left_track_15 ( .in ( { chany_bottom_in[6] , left_bottom_grid_pin_36_[0] } ) , .sram ( mux_tree_tapbuf_size2_16_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_69 , SYNOPSYS_UNCONNECTED_70 } ) , - .out ( chanx_left_out[7] ) , .p0 ( optlc_net_156 ) ) ; + .out ( chanx_left_out[7] ) , .p0 ( optlc_net_152 ) ) ; sb_2__2__mux_tree_tapbuf_size2_17 mux_left_track_17 ( .in ( { chany_bottom_in[7] , left_bottom_grid_pin_37_[0] } ) , .sram ( mux_tree_tapbuf_size2_17_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_71 , SYNOPSYS_UNCONNECTED_72 } ) , - .out ( chanx_left_out[8] ) , .p0 ( optlc_net_156 ) ) ; + .out ( chanx_left_out[8] ) , .p0 ( optlc_net_153 ) ) ; sb_2__2__mux_tree_tapbuf_size2_18 mux_left_track_19 ( .in ( { chany_bottom_in[8] , left_bottom_grid_pin_38_[0] } ) , .sram ( mux_tree_tapbuf_size2_18_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_73 , SYNOPSYS_UNCONNECTED_74 } ) , - .out ( chanx_left_out[9] ) , .p0 ( optlc_net_157 ) ) ; + .out ( chanx_left_out[9] ) , .p0 ( optlc_net_152 ) ) ; sb_2__2__mux_tree_tapbuf_size2_19 mux_left_track_21 ( .in ( { chany_bottom_in[9] , left_bottom_grid_pin_39_[0] } ) , .sram ( mux_tree_tapbuf_size2_19_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_75 , SYNOPSYS_UNCONNECTED_76 } ) , - .out ( chanx_left_out[10] ) , .p0 ( optlc_net_157 ) ) ; + .out ( chanx_left_out[10] ) , .p0 ( optlc_net_152 ) ) ; sb_2__2__mux_tree_tapbuf_size2_20 mux_left_track_23 ( .in ( { chany_bottom_in[10] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_tree_tapbuf_size2_20_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_77 , SYNOPSYS_UNCONNECTED_78 } ) , - .out ( chanx_left_out[11] ) , .p0 ( optlc_net_157 ) ) ; + .out ( chanx_left_out[11] ) , .p0 ( optlc_net_152 ) ) ; sb_2__2__mux_tree_tapbuf_size2_21 mux_left_track_25 ( .in ( { chany_bottom_in[11] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size2_21_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_79 , SYNOPSYS_UNCONNECTED_80 } ) , - .out ( chanx_left_out[12] ) , .p0 ( optlc_net_158 ) ) ; + .out ( chanx_left_out[12] ) , .p0 ( optlc_net_152 ) ) ; sb_2__2__mux_tree_tapbuf_size2_22 mux_left_track_27 ( .in ( { chany_bottom_in[12] , left_bottom_grid_pin_42_[0] } ) , .sram ( mux_tree_tapbuf_size2_22_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_81 , SYNOPSYS_UNCONNECTED_82 } ) , - .out ( chanx_left_out[13] ) , .p0 ( optlc_net_157 ) ) ; + .out ( chanx_left_out[13] ) , .p0 ( optlc_net_152 ) ) ; sb_2__2__mux_tree_tapbuf_size2_23 mux_left_track_31 ( .in ( { chany_bottom_in[14] , left_bottom_grid_pin_36_[0] } ) , .sram ( mux_tree_tapbuf_size2_23_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_83 , SYNOPSYS_UNCONNECTED_84 } ) , - .out ( chanx_left_out[15] ) , .p0 ( optlc_net_157 ) ) ; + .out ( chanx_left_out[15] ) , .p0 ( optlc_net_152 ) ) ; sb_2__2__mux_tree_tapbuf_size2_24 mux_left_track_33 ( .in ( { chany_bottom_in[15] , left_bottom_grid_pin_37_[0] } ) , .sram ( mux_tree_tapbuf_size2_24_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_85 , SYNOPSYS_UNCONNECTED_86 } ) , - .out ( chanx_left_out[16] ) , .p0 ( optlc_net_160 ) ) ; + .out ( chanx_left_out[16] ) , .p0 ( optlc_net_153 ) ) ; sb_2__2__mux_tree_tapbuf_size2_25 mux_left_track_35 ( .in ( { chany_bottom_in[16] , left_bottom_grid_pin_38_[0] } ) , .sram ( mux_tree_tapbuf_size2_25_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_87 , SYNOPSYS_UNCONNECTED_88 } ) , - .out ( chanx_left_out[17] ) , .p0 ( optlc_net_160 ) ) ; + .out ( chanx_left_out[17] ) , .p0 ( optlc_net_153 ) ) ; sb_2__2__mux_tree_tapbuf_size2_26 mux_left_track_37 ( .in ( { chany_bottom_in[17] , left_bottom_grid_pin_39_[0] } ) , .sram ( mux_tree_tapbuf_size2_26_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_89 , SYNOPSYS_UNCONNECTED_90 } ) , - .out ( chanx_left_out[18] ) , .p0 ( optlc_net_160 ) ) ; + .out ( chanx_left_out[18] ) , .p0 ( optlc_net_153 ) ) ; sb_2__2__mux_tree_tapbuf_size2_27 mux_left_track_39 ( .in ( { chany_bottom_in[18] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_tree_tapbuf_size2_27_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_91 , SYNOPSYS_UNCONNECTED_92 } ) , - .out ( chanx_left_out[19] ) , .p0 ( optlc_net_157 ) ) ; + .out ( chanx_left_out[19] ) , .p0 ( optlc_net_152 ) ) ; sb_2__2__mux_tree_tapbuf_size2_28 mux_left_track_41 ( .in ( { chany_bottom_in[19] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size2_28_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_93 , SYNOPSYS_UNCONNECTED_94 } ) , - .out ( chanx_left_out[20] ) , .p0 ( optlc_net_154 ) ) ; + .out ( chanx_left_out[20] ) , .p0 ( optlc_net_152 ) ) ; sb_2__2__mux_tree_tapbuf_size2_29 mux_left_track_43 ( .in ( { chany_bottom_in[20] , left_bottom_grid_pin_42_[0] } ) , .sram ( mux_tree_tapbuf_size2_29_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_95 , SYNOPSYS_UNCONNECTED_96 } ) , - .out ( chanx_left_out[21] ) , .p0 ( optlc_net_154 ) ) ; + .out ( chanx_left_out[21] ) , .p0 ( optlc_net_152 ) ) ; sb_2__2__mux_tree_tapbuf_size2_30 mux_left_track_45 ( .in ( { chany_bottom_in[21] , left_top_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size2_30_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_97 , SYNOPSYS_UNCONNECTED_98 } ) , - .out ( chanx_left_out[22] ) , .p0 ( optlc_net_154 ) ) ; + .out ( chanx_left_out[22] ) , .p0 ( optlc_net_153 ) ) ; sb_2__2__mux_tree_tapbuf_size2_31 mux_left_track_47 ( .in ( { chany_bottom_in[22] , left_bottom_grid_pin_36_[0] } ) , .sram ( mux_tree_tapbuf_size2_31_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_99 , SYNOPSYS_UNCONNECTED_100 } ) , - .out ( chanx_left_out[23] ) , .p0 ( optlc_net_156 ) ) ; + .out ( chanx_left_out[23] ) , .p0 ( optlc_net_153 ) ) ; sb_2__2__mux_tree_tapbuf_size2_32 mux_left_track_49 ( .in ( { chany_bottom_in[23] , left_bottom_grid_pin_37_[0] } ) , .sram ( mux_tree_tapbuf_size2_32_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_101 , SYNOPSYS_UNCONNECTED_102 } ) , - .out ( chanx_left_out[24] ) , .p0 ( optlc_net_156 ) ) ; + .out ( chanx_left_out[24] ) , .p0 ( optlc_net_151 ) ) ; sb_2__2__mux_tree_tapbuf_size2_33 mux_left_track_51 ( .in ( { chany_bottom_in[24] , left_bottom_grid_pin_38_[0] } ) , .sram ( mux_tree_tapbuf_size2_33_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_103 , SYNOPSYS_UNCONNECTED_104 } ) , - .out ( chanx_left_out[25] ) , .p0 ( optlc_net_154 ) ) ; + .out ( chanx_left_out[25] ) , .p0 ( optlc_net_151 ) ) ; sb_2__2__mux_tree_tapbuf_size2_34 mux_left_track_55 ( .in ( { chany_bottom_in[26] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_tree_tapbuf_size2_34_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_105 , SYNOPSYS_UNCONNECTED_106 } ) , - .out ( chanx_left_out[27] ) , .p0 ( optlc_net_154 ) ) ; + .out ( chanx_left_out[27] ) , .p0 ( optlc_net_151 ) ) ; sb_2__2__mux_tree_tapbuf_size2_35 mux_left_track_57 ( .in ( { chany_bottom_in[27] , left_bottom_grid_pin_41_[0] } ) , .sram ( mux_tree_tapbuf_size2_35_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_107 , SYNOPSYS_UNCONNECTED_108 } ) , - .out ( chanx_left_out[28] ) , .p0 ( optlc_net_158 ) ) ; + .out ( chanx_left_out[28] ) , .p0 ( optlc_net_155 ) ) ; sb_2__2__mux_tree_tapbuf_size2 mux_left_track_59 ( .in ( { chany_bottom_in[28] , left_bottom_grid_pin_42_[0] } ) , .sram ( mux_tree_tapbuf_size2_36_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_109 , SYNOPSYS_UNCONNECTED_110 } ) , - .out ( chanx_left_out[29] ) , .p0 ( optlc_net_158 ) ) ; + .out ( chanx_left_out[29] ) , .p0 ( optlc_net_155 ) ) ; sb_2__2__mux_tree_tapbuf_size2_mem_0 mem_bottom_track_13 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) , @@ -12614,25 +12593,25 @@ sb_2__2__mux_tree_tapbuf_size3_0 mux_bottom_track_29 ( chanx_left_in[15] } ) , .sram ( mux_tree_tapbuf_size3_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_111 , SYNOPSYS_UNCONNECTED_112 } ) , - .out ( chany_bottom_out[14] ) , .p0 ( optlc_net_155 ) ) ; + .out ( chany_bottom_out[14] ) , .p0 ( optlc_net_154 ) ) ; sb_2__2__mux_tree_tapbuf_size3_1 mux_bottom_track_45 ( .in ( { bottom_right_grid_pin_1_[0] , bottom_left_grid_pin_47_[0] , chanx_left_in[23] } ) , .sram ( mux_tree_tapbuf_size3_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_113 , SYNOPSYS_UNCONNECTED_114 } ) , - .out ( chany_bottom_out[22] ) , .p0 ( optlc_net_153 ) ) ; + .out ( chany_bottom_out[22] ) , .p0 ( optlc_net_155 ) ) ; sb_2__2__mux_tree_tapbuf_size3_2 mux_left_track_29 ( .in ( { chany_bottom_in[13] , left_top_grid_pin_1_[0] , left_bottom_grid_pin_43_[0] } ) , .sram ( mux_tree_tapbuf_size3_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_115 , SYNOPSYS_UNCONNECTED_116 } ) , - .out ( chanx_left_out[14] ) , .p0 ( optlc_net_154 ) ) ; + .out ( chanx_left_out[14] ) , .p0 ( optlc_net_153 ) ) ; sb_2__2__mux_tree_tapbuf_size3 mux_left_track_53 ( .in ( { chany_bottom_in[25] , left_bottom_grid_pin_39_[0] , left_bottom_grid_pin_43_[0] } ) , .sram ( mux_tree_tapbuf_size3_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_117 , SYNOPSYS_UNCONNECTED_118 } ) , - .out ( chanx_left_out[26] ) , .p0 ( optlc_net_156 ) ) ; + .out ( chanx_left_out[26] ) , .p0 ( optlc_net_151 ) ) ; sb_2__2__mux_tree_tapbuf_size3_mem_0 mem_bottom_track_29 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , @@ -12656,10 +12635,10 @@ sb_2__2__mux_tree_tapbuf_size3_mem mem_left_track_53 ( .pReset ( pReset ) , sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_W_in ) , .X ( pReset[0] ) ) ; sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_S_in ) , .X ( prog_clk[0] ) ) ; -sky130_fd_sc_hd__buf_6 FTB_54__53 ( .A ( chanx_left_in[0] ) , - .X ( ropt_net_182 ) ) ; -sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chanx_left_in[16] ) , - .X ( chany_bottom_out[15] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chanx_left_in[0] ) , + .X ( chany_bottom_out[29] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_55__54 ( .A ( chanx_left_in[16] ) , + .X ( ropt_net_177 ) ) ; sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chanx_left_in[17] ) , .X ( chany_bottom_out[16] ) ) ; sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chanx_left_in[18] ) , @@ -12671,24 +12650,18 @@ sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( chanx_left_in[28] ) , sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( chanx_left_in[29] ) , .X ( chany_bottom_out[28] ) ) ; sky130_fd_sc_hd__buf_6 FTB_61__60 ( .A ( SC_IN_BOT ) , .X ( SC_OUT_BOT ) ) ; -sky130_fd_sc_hd__conb_1 optlc_157 ( .LO ( SYNOPSYS_UNCONNECTED_119 ) , +sky130_fd_sc_hd__conb_1 optlc_153 ( .LO ( SYNOPSYS_UNCONNECTED_119 ) , + .HI ( optlc_net_151 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_158 ( .LO ( SYNOPSYS_UNCONNECTED_120 ) , + .HI ( optlc_net_152 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_160 ( .LO ( SYNOPSYS_UNCONNECTED_121 ) , .HI ( optlc_net_153 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_161 ( .LO ( SYNOPSYS_UNCONNECTED_120 ) , +sky130_fd_sc_hd__conb_1 optlc_162 ( .LO ( SYNOPSYS_UNCONNECTED_122 ) , .HI ( optlc_net_154 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_164 ( .LO ( SYNOPSYS_UNCONNECTED_121 ) , +sky130_fd_sc_hd__conb_1 optlc_164 ( .LO ( SYNOPSYS_UNCONNECTED_123 ) , .HI ( optlc_net_155 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_168 ( .LO ( SYNOPSYS_UNCONNECTED_122 ) , - .HI ( optlc_net_156 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_170 ( .LO ( SYNOPSYS_UNCONNECTED_123 ) , - .HI ( optlc_net_157 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_173 ( .LO ( SYNOPSYS_UNCONNECTED_124 ) , - .HI ( optlc_net_158 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_175 ( .LO ( SYNOPSYS_UNCONNECTED_125 ) , - .HI ( optlc_net_159 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_177 ( .LO ( SYNOPSYS_UNCONNECTED_126 ) , - .HI ( optlc_net_160 ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1359 ( .A ( ropt_net_182 ) , - .X ( chany_bottom_out[29] ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1347 ( .A ( ropt_net_177 ) , + .X ( chany_bottom_out[15] ) ) ; endmodule @@ -14971,7 +14944,7 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:3] mem_out ; -sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_166 ) , +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_172 ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; @@ -14990,16 +14963,16 @@ sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1322 ( .A ( copt_net_145 ) , .X ( copt_net_148 ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1323 ( .A ( ccff_head[0] ) , .X ( copt_net_149 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1324 ( .A ( ropt_net_168 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1324 ( .A ( ropt_net_174 ) , .X ( copt_net_150 ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1332 ( .A ( copt_net_147 ) , .X ( copt_net_158 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 ropt_h_inst_1337 ( .A ( copt_net_150 ) , - .X ( ropt_net_166 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1338 ( .A ( copt_net_158 ) , - .X ( ropt_net_167 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1339 ( .A ( ropt_net_167 ) , - .X ( ropt_net_168 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 ropt_h_inst_1343 ( .A ( copt_net_150 ) , + .X ( ropt_net_172 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1344 ( .A ( copt_net_158 ) , + .X ( ropt_net_173 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1345 ( .A ( ropt_net_173 ) , + .X ( ropt_net_174 ) ) ; endmodule @@ -15235,6 +15208,7 @@ input pReset_W_in ; output pReset_N_out ; input prog_clk_0_N_in ; +wire ropt_net_162 ; wire [0:0] prog_clk ; wire prog_clk_0 ; wire [0:3] mux_tree_tapbuf_size10_0_sram ; @@ -15501,7 +15475,7 @@ sb_2__1__mux_tree_tapbuf_size9_1 mux_top_track_10 ( SYNOPSYS_UNCONNECTED_44 , SYNOPSYS_UNCONNECTED_45 } ) , .out ( chany_top_out[5] ) , .p0 ( optlc_net_142 ) ) ; sb_2__1__mux_tree_tapbuf_size9 mux_bottom_track_11 ( - .in ( { chany_bottom_out[11] , chany_bottom_out[25] , + .in ( { ropt_net_162 , chany_bottom_out[25] , bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_46_[0] , bottom_left_grid_pin_48_[0] , bottom_left_grid_pin_50_[0] , chanx_left_in[5] , chanx_left_in[16] , chanx_left_in[27] } ) , @@ -15644,7 +15618,7 @@ sb_2__1__mux_tree_tapbuf_size6_3 mux_left_track_7 ( SYNOPSYS_UNCONNECTED_83 } ) , .out ( chanx_left_out[3] ) , .p0 ( optlc_net_143 ) ) ; sb_2__1__mux_tree_tapbuf_size6 mux_left_track_9 ( - .in ( { chany_bottom_out[11] , chany_bottom_in[4] , chany_top_out[11] , + .in ( { ropt_net_162 , chany_bottom_in[4] , chany_top_out[11] , left_bottom_grid_pin_37_[0] , left_bottom_grid_pin_40_[0] , left_bottom_grid_pin_43_[0] } ) , .sram ( mux_tree_tapbuf_size6_4_sram ) , @@ -15944,8 +15918,8 @@ sky130_fd_sc_hd__buf_8 FTB_53__52 ( .A ( chany_top_in[7] ) , .X ( chany_bottom_out[8] ) ) ; sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chany_top_in[8] ) , .X ( chany_bottom_out[9] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chany_top_in[10] ) , - .X ( chany_bottom_out[11] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_55__54 ( .A ( chany_top_in[10] ) , + .X ( ropt_net_162 ) ) ; sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chany_top_in[11] ) , .X ( chany_bottom_out[12] ) ) ; sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chany_top_in[12] ) , @@ -16026,6 +16000,8 @@ sky130_fd_sc_hd__conb_1 optlc_149 ( .LO ( SYNOPSYS_UNCONNECTED_144 ) , .HI ( optlc_net_143 ) ) ; sky130_fd_sc_hd__conb_1 optlc_151 ( .LO ( SYNOPSYS_UNCONNECTED_145 ) , .HI ( optlc_net_144 ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1336 ( .A ( ropt_net_162 ) , + .X ( chany_bottom_out[11] ) ) ; endmodule @@ -16037,14 +16013,14 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -wire copt_net_164 ; +wire copt_net_181 ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( copt_net_164 ) ) ; + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( copt_net_181 ) ) ; sky130_fd_sc_hd__buf_6 FTB_53__52 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1327 ( .A ( copt_net_164 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1345 ( .A ( copt_net_181 ) , .X ( mem_out[1] ) ) ; endmodule @@ -16624,9 +16600,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_119 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_119 ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_142 ( .A ( BUF_net_119 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_124 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_124 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_159 ( .A ( BUF_net_124 ) , .Y ( out[0] ) ) ; endmodule @@ -16645,9 +16621,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_117 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_117 ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_148 ( .A ( BUF_net_117 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_121 ( .A ( BUF_net_122 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_122 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_122 ) ) ; endmodule @@ -16666,7 +16642,7 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_115 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_120 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -16686,9 +16662,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_113 ( .A ( BUF_net_114 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_114 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_114 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_118 ( .A ( BUF_net_119 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_119 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_119 ) ) ; endmodule @@ -16704,12 +16680,11 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_111 ( .A ( BUF_net_112 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_112 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_112 ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_117 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) ) ; endmodule @@ -16747,7 +16722,7 @@ sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; endmodule @@ -16768,9 +16743,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_109 ( .A ( BUF_net_110 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_110 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_110 ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_116 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_116 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_157 ( .A ( BUF_net_116 ) , .Y ( out[0] ) ) ; endmodule @@ -16784,13 +16759,13 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_114 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) ) ; endmodule @@ -16809,9 +16784,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_108 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_108 ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_140 ( .A ( BUF_net_108 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_113 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_113 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_155 ( .A ( BUF_net_113 ) , .Y ( out[0] ) ) ; endmodule @@ -16847,11 +16822,12 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_106 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .X ( out[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_111 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_111 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_153 ( .A ( BUF_net_111 ) , .Y ( out[0] ) ) ; endmodule @@ -16870,7 +16846,7 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_105 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_109 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -16907,11 +16883,12 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_104 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .X ( out[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_108 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_108 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_151 ( .A ( BUF_net_108 ) , .Y ( out[0] ) ) ; endmodule @@ -16930,9 +16907,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_102 ( .A ( BUF_net_103 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_103 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_103 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_105 ( .A ( BUF_net_106 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_106 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_106 ) ) ; endmodule @@ -16946,13 +16923,13 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_104 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) ) ; endmodule @@ -16971,9 +16948,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_101 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_101 ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_138 ( .A ( BUF_net_101 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_103 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_103 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_149 ( .A ( BUF_net_103 ) , .Y ( out[0] ) ) ; endmodule @@ -17009,11 +16986,12 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_99 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .X ( out[0] ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_100 ( .A ( BUF_net_101 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_101 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_101 ) ) ; endmodule @@ -17032,9 +17010,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_98 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_98 ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_136 ( .A ( BUF_net_98 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_99 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_99 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_147 ( .A ( BUF_net_99 ) , .Y ( out[0] ) ) ; endmodule @@ -17048,13 +17026,14 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_97 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_97 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_145 ( .A ( BUF_net_97 ) , .Y ( out[0] ) ) ; endmodule @@ -17108,14 +17087,13 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_96 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_96 ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_134 ( .A ( BUF_net_96 ) , .Y ( out[0] ) ) ; endmodule @@ -17134,9 +17112,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_94 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_94 ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_146 ( .A ( BUF_net_94 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_95 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_95 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_143 ( .A ( BUF_net_95 ) , .Y ( out[0] ) ) ; endmodule @@ -17155,9 +17133,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_91 ( .A ( BUF_net_92 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_92 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_92 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_92 ( .A ( BUF_net_93 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_93 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_93 ) ) ; endmodule @@ -17196,9 +17174,8 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_89 ( .A ( BUF_net_90 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_90 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_90 ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_91 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) ) ; endmodule @@ -17257,8 +17234,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_88 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .X ( out[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_90 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_90 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_141 ( .A ( BUF_net_90 ) , .Y ( out[0] ) ) ; endmodule @@ -17272,13 +17250,14 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_87 ( .A ( BUF_net_88 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_88 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_88 ) ) ; endmodule @@ -17297,9 +17276,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_87 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_87 ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_132 ( .A ( BUF_net_87 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_86 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_86 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_139 ( .A ( BUF_net_86 ) , .Y ( out[0] ) ) ; endmodule @@ -17318,9 +17297,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_85 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_85 ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_130 ( .A ( BUF_net_85 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_84 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_84 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_137 ( .A ( BUF_net_84 ) , .Y ( out[0] ) ) ; endmodule @@ -17339,9 +17318,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_83 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_83 ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_128 ( .A ( BUF_net_83 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_82 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_82 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_135 ( .A ( BUF_net_82 ) , .Y ( out[0] ) ) ; endmodule @@ -17444,9 +17423,9 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_81 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .Y ( BUF_net_81 ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_126 ( .A ( BUF_net_81 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_79 ( .A ( BUF_net_80 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_80 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .Y ( BUF_net_80 ) ) ; endmodule @@ -17461,6 +17440,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , @@ -17469,8 +17450,6 @@ sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_79 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .X ( out[0] ) ) ; endmodule @@ -17495,7 +17474,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; sky130_fd_sc_hd__inv_2 BINV_R_78 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .Y ( BUF_net_78 ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_124 ( .A ( BUF_net_78 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_133 ( .A ( BUF_net_78 ) , .Y ( out[0] ) ) ; endmodule @@ -17534,8 +17513,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , @@ -17544,6 +17521,9 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_76 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .Y ( BUF_net_76 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_131 ( .A ( BUF_net_76 ) , .Y ( out[0] ) ) ; endmodule @@ -17753,35 +17733,35 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( copt_net_156 ) , +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_201 ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1318 ( .A ( copt_net_158 ) , - .X ( copt_net_154 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1319 ( .A ( copt_net_154 ) , - .X ( copt_net_155 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1320 ( .A ( copt_net_155 ) , - .X ( copt_net_156 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1321 ( .A ( ccff_head[0] ) , - .X ( copt_net_157 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1322 ( .A ( ropt_net_192 ) , - .X ( copt_net_158 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1323 ( .A ( copt_net_157 ) , - .X ( copt_net_159 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1393 ( .A ( ropt_net_196 ) , - .X ( ropt_net_192 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1394 ( .A ( copt_net_159 ) , - .X ( ropt_net_193 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1395 ( .A ( ropt_net_193 ) , - .X ( ropt_net_194 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1396 ( .A ( ropt_net_194 ) , - .X ( ropt_net_195 ) ) ; -sky130_fd_sc_hd__buf_1 ropt_h_inst_1397 ( .A ( ropt_net_195 ) , - .X ( ropt_net_196 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1336 ( .A ( ccff_head[0] ) , + .X ( copt_net_170 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1337 ( .A ( copt_net_172 ) , + .X ( copt_net_171 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1338 ( .A ( copt_net_170 ) , + .X ( copt_net_172 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1339 ( .A ( copt_net_175 ) , + .X ( copt_net_173 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1340 ( .A ( copt_net_173 ) , + .X ( copt_net_174 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1341 ( .A ( copt_net_171 ) , + .X ( copt_net_175 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1361 ( .A ( copt_net_174 ) , + .X ( ropt_net_197 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1362 ( .A ( ropt_net_197 ) , + .X ( ropt_net_198 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1363 ( .A ( ropt_net_198 ) , + .X ( ropt_net_199 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1364 ( .A ( ropt_net_199 ) , + .X ( ropt_net_200 ) ) ; +sky130_fd_sc_hd__buf_1 ropt_h_inst_1365 ( .A ( ropt_net_200 ) , + .X ( ropt_net_201 ) ) ; endmodule @@ -17808,9 +17788,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_76 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .Y ( BUF_net_76 ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_122 ( .A ( BUF_net_76 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_74 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_74 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_129 ( .A ( BUF_net_74 ) , .Y ( out[0] ) ) ; endmodule @@ -17833,13 +17813,12 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_73 ( .A ( BUF_net_74 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_74 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .Y ( BUF_net_74 ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_72 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .X ( out[0] ) ) ; endmodule @@ -17866,9 +17845,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_71 ( .A ( BUF_net_72 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_72 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .Y ( BUF_net_72 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_163 ( .A ( BUF_net_164 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_164 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_164 ) ) ; endmodule @@ -17895,9 +17874,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_69 ( .A ( BUF_net_70 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_70 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .Y ( BUF_net_70 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_68 ( .A ( BUF_net_69 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_69 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_69 ) ) ; endmodule @@ -17924,9 +17903,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_67 ( .A ( BUF_net_68 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_68 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .Y ( BUF_net_68 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_66 ( .A ( BUF_net_67 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_67 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_67 ) ) ; endmodule @@ -17942,6 +17921,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , @@ -17949,13 +17930,10 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_65 ( .A ( BUF_net_66 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_66 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .Y ( BUF_net_66 ) ) ; endmodule @@ -17982,7 +17960,7 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_64 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_65 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -18010,8 +17988,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_63 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .X ( out[0] ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_63 ( .A ( BUF_net_64 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_64 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_64 ) ) ; endmodule @@ -18066,9 +18045,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_62 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .Y ( BUF_net_62 ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_144 ( .A ( BUF_net_62 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_62 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .X ( out[0] ) ) ; endmodule @@ -18095,8 +18073,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_60 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .X ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_61 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_61 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_161 ( .A ( BUF_net_61 ) , .Y ( out[0] ) ) ; endmodule @@ -18167,7 +18146,6 @@ input pReset_W_in ; output pReset_N_out ; input prog_clk_0_N_in ; -wire ropt_net_174 ; wire [0:0] prog_clk ; wire prog_clk_0 ; wire [0:1] mux_tree_tapbuf_size2_0_sram ; @@ -18284,84 +18262,84 @@ sb_2__0__mux_tree_tapbuf_size4_0 mux_top_track_0 ( .sram ( mux_tree_tapbuf_size4_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 } ) , - .out ( chany_top_out[0] ) , .p0 ( optlc_net_152 ) ) ; + .out ( chany_top_out[0] ) , .p0 ( optlc_net_166 ) ) ; sb_2__0__mux_tree_tapbuf_size4_1 mux_top_track_2 ( .in ( { top_left_grid_pin_45_[0] , top_left_grid_pin_48_[0] , top_left_grid_pin_51_[0] , chanx_left_in[29] } ) , .sram ( mux_tree_tapbuf_size4_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 } ) , - .out ( chany_top_out[1] ) , .p0 ( optlc_net_151 ) ) ; + .out ( chany_top_out[1] ) , .p0 ( optlc_net_169 ) ) ; sb_2__0__mux_tree_tapbuf_size4_2 mux_top_track_4 ( .in ( { top_left_grid_pin_46_[0] , top_left_grid_pin_49_[0] , top_right_grid_pin_1_[0] , chanx_left_in[28] } ) , .sram ( mux_tree_tapbuf_size4_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 , SYNOPSYS_UNCONNECTED_9 } ) , - .out ( chany_top_out[2] ) , .p0 ( optlc_net_152 ) ) ; + .out ( chany_top_out[2] ) , .p0 ( optlc_net_166 ) ) ; sb_2__0__mux_tree_tapbuf_size4_3 mux_top_track_6 ( .in ( { top_left_grid_pin_44_[0] , top_left_grid_pin_47_[0] , top_left_grid_pin_50_[0] , chanx_left_in[27] } ) , .sram ( mux_tree_tapbuf_size4_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , - .out ( chany_top_out[3] ) , .p0 ( optlc_net_152 ) ) ; + .out ( chany_top_out[3] ) , .p0 ( optlc_net_166 ) ) ; sb_2__0__mux_tree_tapbuf_size4_4 mux_top_track_8 ( .in ( { top_left_grid_pin_45_[0] , top_left_grid_pin_48_[0] , top_left_grid_pin_51_[0] , chanx_left_in[26] } ) , .sram ( mux_tree_tapbuf_size4_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , SYNOPSYS_UNCONNECTED_15 } ) , - .out ( chany_top_out[4] ) , .p0 ( optlc_net_151 ) ) ; + .out ( chany_top_out[4] ) , .p0 ( optlc_net_169 ) ) ; sb_2__0__mux_tree_tapbuf_size4_5 mux_top_track_10 ( .in ( { top_left_grid_pin_46_[0] , top_left_grid_pin_49_[0] , top_right_grid_pin_1_[0] , chanx_left_in[25] } ) , .sram ( mux_tree_tapbuf_size4_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_16 , SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 } ) , - .out ( chany_top_out[5] ) , .p0 ( optlc_net_151 ) ) ; + .out ( chany_top_out[5] ) , .p0 ( optlc_net_169 ) ) ; sb_2__0__mux_tree_tapbuf_size4_6 mux_left_track_1 ( .in ( { chany_top_in[0] , left_bottom_grid_pin_1_[0] , left_bottom_grid_pin_7_[0] , left_bottom_grid_pin_13_[0] } ) , .sram ( mux_tree_tapbuf_size4_6_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 , SYNOPSYS_UNCONNECTED_21 } ) , - .out ( chanx_left_out[0] ) , .p0 ( optlc_net_153 ) ) ; + .out ( chanx_left_out[0] ) , .p0 ( optlc_net_165 ) ) ; sb_2__0__mux_tree_tapbuf_size4_7 mux_left_track_3 ( .in ( { chany_top_in[29] , left_bottom_grid_pin_3_[0] , left_bottom_grid_pin_9_[0] , left_bottom_grid_pin_15_[0] } ) , .sram ( mux_tree_tapbuf_size4_7_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_22 , SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) , - .out ( chanx_left_out[1] ) , .p0 ( optlc_net_153 ) ) ; + .out ( chanx_left_out[1] ) , .p0 ( optlc_net_165 ) ) ; sb_2__0__mux_tree_tapbuf_size4_8 mux_left_track_5 ( .in ( { chany_top_in[28] , left_bottom_grid_pin_5_[0] , left_bottom_grid_pin_11_[0] , left_bottom_grid_pin_17_[0] } ) , .sram ( mux_tree_tapbuf_size4_8_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , SYNOPSYS_UNCONNECTED_27 } ) , - .out ( chanx_left_out[2] ) , .p0 ( optlc_net_153 ) ) ; + .out ( chanx_left_out[2] ) , .p0 ( optlc_net_167 ) ) ; sb_2__0__mux_tree_tapbuf_size4_9 mux_left_track_7 ( .in ( { chany_top_in[27] , left_bottom_grid_pin_1_[0] , left_bottom_grid_pin_7_[0] , left_bottom_grid_pin_13_[0] } ) , .sram ( mux_tree_tapbuf_size4_9_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_28 , SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 } ) , - .out ( chanx_left_out[3] ) , .p0 ( optlc_net_153 ) ) ; + .out ( chanx_left_out[3] ) , .p0 ( optlc_net_165 ) ) ; sb_2__0__mux_tree_tapbuf_size4_10 mux_left_track_9 ( .in ( { chany_top_in[26] , left_bottom_grid_pin_3_[0] , left_bottom_grid_pin_9_[0] , left_bottom_grid_pin_15_[0] } ) , .sram ( mux_tree_tapbuf_size4_10_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 , SYNOPSYS_UNCONNECTED_33 } ) , - .out ( chanx_left_out[4] ) , .p0 ( optlc_net_150 ) ) ; + .out ( chanx_left_out[4] ) , .p0 ( optlc_net_168 ) ) ; sb_2__0__mux_tree_tapbuf_size4 mux_left_track_11 ( .in ( { chany_top_in[25] , left_bottom_grid_pin_5_[0] , left_bottom_grid_pin_11_[0] , left_bottom_grid_pin_17_[0] } ) , .sram ( mux_tree_tapbuf_size4_11_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_34 , SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) , - .out ( chanx_left_out[5] ) , .p0 ( optlc_net_150 ) ) ; + .out ( chanx_left_out[5] ) , .p0 ( optlc_net_168 ) ) ; sb_2__0__mux_tree_tapbuf_size4_mem_0 mem_top_track_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , @@ -18426,31 +18404,31 @@ sb_2__0__mux_tree_tapbuf_size3_0 mux_top_track_12 ( chanx_left_in[24] } ) , .sram ( mux_tree_tapbuf_size3_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 } ) , - .out ( chany_top_out[6] ) , .p0 ( optlc_net_151 ) ) ; + .out ( chany_top_out[6] ) , .p0 ( optlc_net_168 ) ) ; sb_2__0__mux_tree_tapbuf_size3_1 mux_top_track_44 ( .in ( { top_left_grid_pin_48_[0] , top_right_grid_pin_1_[0] , chanx_left_in[8] } ) , .sram ( mux_tree_tapbuf_size3_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) , - .out ( chany_top_out[22] ) , .p0 ( optlc_net_151 ) ) ; + .out ( chany_top_out[22] ) , .p0 ( optlc_net_169 ) ) ; sb_2__0__mux_tree_tapbuf_size3_2 mux_left_track_13 ( .in ( { chany_top_in[24] , left_bottom_grid_pin_1_[0] , left_bottom_grid_pin_17_[0] } ) , .sram ( mux_tree_tapbuf_size3_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 } ) , - .out ( chanx_left_out[6] ) , .p0 ( optlc_net_150 ) ) ; + .out ( chanx_left_out[6] ) , .p0 ( optlc_net_168 ) ) ; sb_2__0__mux_tree_tapbuf_size3_3 mux_left_track_29 ( .in ( { chany_top_in[16] , left_bottom_grid_pin_1_[0] , left_bottom_grid_pin_17_[0] } ) , .sram ( mux_tree_tapbuf_size3_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) , - .out ( chanx_left_out[14] ) , .p0 ( optlc_net_153 ) ) ; + .out ( chanx_left_out[14] ) , .p0 ( optlc_net_167 ) ) ; sb_2__0__mux_tree_tapbuf_size3 mux_left_track_45 ( .in ( { chany_top_in[8] , left_bottom_grid_pin_1_[0] , left_bottom_grid_pin_17_[0] } ) , .sram ( mux_tree_tapbuf_size3_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 } ) , - .out ( chanx_left_out[22] ) , .p0 ( optlc_net_153 ) ) ; + .out ( chanx_left_out[22] ) , .p0 ( optlc_net_167 ) ) ; sb_2__0__mux_tree_tapbuf_size3_mem_0 mem_top_track_12 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) , @@ -18480,182 +18458,182 @@ sb_2__0__mux_tree_tapbuf_size2_0 mux_top_track_14 ( .in ( { top_left_grid_pin_45_[0] , chanx_left_in[23] } ) , .sram ( mux_tree_tapbuf_size2_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) , - .out ( chany_top_out[7] ) , .p0 ( optlc_net_151 ) ) ; + .out ( chany_top_out[7] ) , .p0 ( optlc_net_169 ) ) ; sb_2__0__mux_tree_tapbuf_size2_1 mux_top_track_16 ( .in ( { top_left_grid_pin_46_[0] , chanx_left_in[22] } ) , .sram ( mux_tree_tapbuf_size2_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 } ) , - .out ( chany_top_out[8] ) , .p0 ( optlc_net_151 ) ) ; + .out ( chany_top_out[8] ) , .p0 ( optlc_net_169 ) ) ; sb_2__0__mux_tree_tapbuf_size2_2 mux_top_track_18 ( .in ( { top_left_grid_pin_47_[0] , chanx_left_in[21] } ) , .sram ( mux_tree_tapbuf_size2_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) , - .out ( chany_top_out[9] ) , .p0 ( optlc_net_151 ) ) ; + .out ( chany_top_out[9] ) , .p0 ( optlc_net_169 ) ) ; sb_2__0__mux_tree_tapbuf_size2_3 mux_top_track_20 ( .in ( { top_left_grid_pin_48_[0] , chanx_left_in[20] } ) , .sram ( mux_tree_tapbuf_size2_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 } ) , - .out ( chany_top_out[10] ) , .p0 ( optlc_net_151 ) ) ; + .out ( chany_top_out[10] ) , .p0 ( optlc_net_169 ) ) ; sb_2__0__mux_tree_tapbuf_size2_4 mux_top_track_22 ( .in ( { top_left_grid_pin_49_[0] , chanx_left_in[19] } ) , .sram ( mux_tree_tapbuf_size2_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) , - .out ( chany_top_out[11] ) , .p0 ( optlc_net_152 ) ) ; + .out ( chany_top_out[11] ) , .p0 ( optlc_net_166 ) ) ; sb_2__0__mux_tree_tapbuf_size2_5 mux_top_track_24 ( .in ( { top_left_grid_pin_50_[0] , chanx_left_in[18] } ) , .sram ( mux_tree_tapbuf_size2_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 } ) , - .out ( chany_top_out[12] ) , .p0 ( optlc_net_152 ) ) ; + .out ( chany_top_out[12] ) , .p0 ( optlc_net_166 ) ) ; sb_2__0__mux_tree_tapbuf_size2_6 mux_top_track_26 ( .in ( { top_left_grid_pin_51_[0] , chanx_left_in[17] } ) , .sram ( mux_tree_tapbuf_size2_6_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) , - .out ( chany_top_out[13] ) , .p0 ( optlc_net_152 ) ) ; + .out ( chany_top_out[13] ) , .p0 ( optlc_net_166 ) ) ; sb_2__0__mux_tree_tapbuf_size2_7 mux_top_track_28 ( .in ( { top_right_grid_pin_1_[0] , chanx_left_in[16] } ) , .sram ( mux_tree_tapbuf_size2_7_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 } ) , - .out ( chany_top_out[14] ) , .p0 ( optlc_net_152 ) ) ; + .out ( chany_top_out[14] ) , .p0 ( optlc_net_166 ) ) ; sb_2__0__mux_tree_tapbuf_size2_8 mux_top_track_36 ( .in ( { top_left_grid_pin_44_[0] , chanx_left_in[12] } ) , .sram ( mux_tree_tapbuf_size2_8_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) , - .out ( chany_top_out[18] ) , .p0 ( optlc_net_152 ) ) ; + .out ( chany_top_out[18] ) , .p0 ( optlc_net_166 ) ) ; sb_2__0__mux_tree_tapbuf_size2_9 mux_top_track_38 ( .in ( { top_left_grid_pin_45_[0] , chanx_left_in[11] } ) , .sram ( mux_tree_tapbuf_size2_9_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 } ) , - .out ( chany_top_out[19] ) , .p0 ( optlc_net_151 ) ) ; + .out ( chany_top_out[19] ) , .p0 ( optlc_net_169 ) ) ; sb_2__0__mux_tree_tapbuf_size2_10 mux_top_track_40 ( .in ( { top_left_grid_pin_46_[0] , chanx_left_in[10] } ) , .sram ( mux_tree_tapbuf_size2_10_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 } ) , - .out ( chany_top_out[20] ) , .p0 ( optlc_net_151 ) ) ; + .out ( chany_top_out[20] ) , .p0 ( optlc_net_166 ) ) ; sb_2__0__mux_tree_tapbuf_size2_11 mux_top_track_42 ( .in ( { top_left_grid_pin_47_[0] , chanx_left_in[9] } ) , .sram ( mux_tree_tapbuf_size2_11_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_69 , SYNOPSYS_UNCONNECTED_70 } ) , - .out ( chany_top_out[21] ) , .p0 ( optlc_net_151 ) ) ; + .out ( chany_top_out[21] ) , .p0 ( optlc_net_166 ) ) ; sb_2__0__mux_tree_tapbuf_size2_12 mux_top_track_46 ( .in ( { top_left_grid_pin_49_[0] , chanx_left_in[7] } ) , .sram ( mux_tree_tapbuf_size2_12_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_71 , SYNOPSYS_UNCONNECTED_72 } ) , - .out ( chany_top_out[23] ) , .p0 ( optlc_net_152 ) ) ; + .out ( chany_top_out[23] ) , .p0 ( optlc_net_166 ) ) ; sb_2__0__mux_tree_tapbuf_size2_13 mux_top_track_48 ( .in ( { top_left_grid_pin_50_[0] , chanx_left_in[6] } ) , .sram ( mux_tree_tapbuf_size2_13_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_73 , SYNOPSYS_UNCONNECTED_74 } ) , - .out ( chany_top_out[24] ) , .p0 ( optlc_net_152 ) ) ; + .out ( chany_top_out[24] ) , .p0 ( optlc_net_166 ) ) ; sb_2__0__mux_tree_tapbuf_size2_14 mux_top_track_50 ( .in ( { top_left_grid_pin_51_[0] , chanx_left_in[5] } ) , .sram ( mux_tree_tapbuf_size2_14_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_75 , SYNOPSYS_UNCONNECTED_76 } ) , - .out ( chany_top_out[25] ) , .p0 ( optlc_net_152 ) ) ; + .out ( chany_top_out[25] ) , .p0 ( optlc_net_166 ) ) ; sb_2__0__mux_tree_tapbuf_size2_15 mux_left_track_15 ( .in ( { chany_top_in[23] , left_bottom_grid_pin_3_[0] } ) , .sram ( mux_tree_tapbuf_size2_15_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_77 , SYNOPSYS_UNCONNECTED_78 } ) , - .out ( chanx_left_out[7] ) , .p0 ( optlc_net_150 ) ) ; + .out ( chanx_left_out[7] ) , .p0 ( optlc_net_168 ) ) ; sb_2__0__mux_tree_tapbuf_size2_16 mux_left_track_17 ( .in ( { chany_top_in[22] , left_bottom_grid_pin_5_[0] } ) , .sram ( mux_tree_tapbuf_size2_16_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_79 , SYNOPSYS_UNCONNECTED_80 } ) , - .out ( chanx_left_out[8] ) , .p0 ( optlc_net_150 ) ) ; + .out ( chanx_left_out[8] ) , .p0 ( optlc_net_169 ) ) ; sb_2__0__mux_tree_tapbuf_size2_17 mux_left_track_19 ( .in ( { chany_top_in[21] , left_bottom_grid_pin_7_[0] } ) , .sram ( mux_tree_tapbuf_size2_17_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_81 , SYNOPSYS_UNCONNECTED_82 } ) , - .out ( chanx_left_out[9] ) , .p0 ( optlc_net_151 ) ) ; + .out ( chanx_left_out[9] ) , .p0 ( optlc_net_169 ) ) ; sb_2__0__mux_tree_tapbuf_size2_18 mux_left_track_21 ( .in ( { chany_top_in[20] , left_bottom_grid_pin_9_[0] } ) , .sram ( mux_tree_tapbuf_size2_18_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_83 , SYNOPSYS_UNCONNECTED_84 } ) , - .out ( chanx_left_out[10] ) , .p0 ( optlc_net_151 ) ) ; + .out ( chanx_left_out[10] ) , .p0 ( optlc_net_169 ) ) ; sb_2__0__mux_tree_tapbuf_size2_19 mux_left_track_23 ( .in ( { chany_top_in[19] , left_bottom_grid_pin_11_[0] } ) , .sram ( mux_tree_tapbuf_size2_19_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_85 , SYNOPSYS_UNCONNECTED_86 } ) , - .out ( chanx_left_out[11] ) , .p0 ( optlc_net_153 ) ) ; + .out ( chanx_left_out[11] ) , .p0 ( optlc_net_167 ) ) ; sb_2__0__mux_tree_tapbuf_size2_20 mux_left_track_25 ( .in ( { chany_top_in[18] , left_bottom_grid_pin_13_[0] } ) , .sram ( mux_tree_tapbuf_size2_20_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_87 , SYNOPSYS_UNCONNECTED_88 } ) , - .out ( chanx_left_out[12] ) , .p0 ( optlc_net_152 ) ) ; + .out ( chanx_left_out[12] ) , .p0 ( optlc_net_167 ) ) ; sb_2__0__mux_tree_tapbuf_size2_21 mux_left_track_27 ( .in ( { chany_top_in[17] , left_bottom_grid_pin_15_[0] } ) , .sram ( mux_tree_tapbuf_size2_21_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_89 , SYNOPSYS_UNCONNECTED_90 } ) , - .out ( chanx_left_out[13] ) , .p0 ( optlc_net_153 ) ) ; + .out ( chanx_left_out[13] ) , .p0 ( optlc_net_167 ) ) ; sb_2__0__mux_tree_tapbuf_size2_22 mux_left_track_31 ( .in ( { chany_top_in[15] , left_bottom_grid_pin_3_[0] } ) , .sram ( mux_tree_tapbuf_size2_22_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_91 , SYNOPSYS_UNCONNECTED_92 } ) , - .out ( chanx_left_out[15] ) , .p0 ( optlc_net_152 ) ) ; + .out ( chanx_left_out[15] ) , .p0 ( optlc_net_166 ) ) ; sb_2__0__mux_tree_tapbuf_size2_23 mux_left_track_33 ( .in ( { chany_top_in[14] , left_bottom_grid_pin_5_[0] } ) , .sram ( mux_tree_tapbuf_size2_23_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_93 , SYNOPSYS_UNCONNECTED_94 } ) , - .out ( chanx_left_out[16] ) , .p0 ( optlc_net_152 ) ) ; + .out ( chanx_left_out[16] ) , .p0 ( optlc_net_166 ) ) ; sb_2__0__mux_tree_tapbuf_size2_24 mux_left_track_35 ( .in ( { chany_top_in[13] , left_bottom_grid_pin_7_[0] } ) , .sram ( mux_tree_tapbuf_size2_24_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_95 , SYNOPSYS_UNCONNECTED_96 } ) , - .out ( chanx_left_out[17] ) , .p0 ( optlc_net_151 ) ) ; + .out ( chanx_left_out[17] ) , .p0 ( optlc_net_169 ) ) ; sb_2__0__mux_tree_tapbuf_size2_25 mux_left_track_37 ( .in ( { chany_top_in[12] , left_bottom_grid_pin_9_[0] } ) , .sram ( mux_tree_tapbuf_size2_25_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_97 , SYNOPSYS_UNCONNECTED_98 } ) , - .out ( chanx_left_out[18] ) , .p0 ( optlc_net_150 ) ) ; + .out ( chanx_left_out[18] ) , .p0 ( optlc_net_167 ) ) ; sb_2__0__mux_tree_tapbuf_size2_26 mux_left_track_39 ( .in ( { chany_top_in[11] , left_bottom_grid_pin_11_[0] } ) , .sram ( mux_tree_tapbuf_size2_26_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_99 , SYNOPSYS_UNCONNECTED_100 } ) , - .out ( chanx_left_out[19] ) , .p0 ( optlc_net_153 ) ) ; + .out ( chanx_left_out[19] ) , .p0 ( optlc_net_167 ) ) ; sb_2__0__mux_tree_tapbuf_size2_27 mux_left_track_41 ( .in ( { chany_top_in[10] , left_bottom_grid_pin_13_[0] } ) , .sram ( mux_tree_tapbuf_size2_27_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_101 , SYNOPSYS_UNCONNECTED_102 } ) , - .out ( chanx_left_out[20] ) , .p0 ( optlc_net_150 ) ) ; + .out ( chanx_left_out[20] ) , .p0 ( optlc_net_165 ) ) ; sb_2__0__mux_tree_tapbuf_size2_28 mux_left_track_43 ( .in ( { chany_top_in[9] , left_bottom_grid_pin_15_[0] } ) , .sram ( mux_tree_tapbuf_size2_28_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_103 , SYNOPSYS_UNCONNECTED_104 } ) , - .out ( chanx_left_out[21] ) , .p0 ( optlc_net_153 ) ) ; + .out ( chanx_left_out[21] ) , .p0 ( optlc_net_165 ) ) ; sb_2__0__mux_tree_tapbuf_size2_29 mux_left_track_47 ( .in ( { chany_top_in[7] , left_bottom_grid_pin_3_[0] } ) , .sram ( mux_tree_tapbuf_size2_29_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_105 , SYNOPSYS_UNCONNECTED_106 } ) , - .out ( chanx_left_out[23] ) , .p0 ( optlc_net_152 ) ) ; + .out ( chanx_left_out[23] ) , .p0 ( optlc_net_167 ) ) ; sb_2__0__mux_tree_tapbuf_size2_30 mux_left_track_49 ( .in ( { chany_top_in[6] , left_bottom_grid_pin_5_[0] } ) , .sram ( mux_tree_tapbuf_size2_30_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_107 , SYNOPSYS_UNCONNECTED_108 } ) , - .out ( chanx_left_out[24] ) , .p0 ( optlc_net_153 ) ) ; + .out ( chanx_left_out[24] ) , .p0 ( optlc_net_167 ) ) ; sb_2__0__mux_tree_tapbuf_size2_31 mux_left_track_51 ( .in ( { chany_top_in[5] , left_bottom_grid_pin_7_[0] } ) , .sram ( mux_tree_tapbuf_size2_31_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_109 , SYNOPSYS_UNCONNECTED_110 } ) , - .out ( chanx_left_out[25] ) , .p0 ( optlc_net_153 ) ) ; + .out ( chanx_left_out[25] ) , .p0 ( optlc_net_165 ) ) ; sb_2__0__mux_tree_tapbuf_size2_32 mux_left_track_53 ( .in ( { chany_top_in[4] , left_bottom_grid_pin_9_[0] } ) , .sram ( mux_tree_tapbuf_size2_32_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_111 , SYNOPSYS_UNCONNECTED_112 } ) , - .out ( chanx_left_out[26] ) , .p0 ( optlc_net_150 ) ) ; + .out ( chanx_left_out[26] ) , .p0 ( optlc_net_168 ) ) ; sb_2__0__mux_tree_tapbuf_size2_33 mux_left_track_55 ( .in ( { chany_top_in[3] , left_bottom_grid_pin_11_[0] } ) , .sram ( mux_tree_tapbuf_size2_33_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_113 , SYNOPSYS_UNCONNECTED_114 } ) , - .out ( chanx_left_out[27] ) , .p0 ( optlc_net_150 ) ) ; + .out ( chanx_left_out[27] ) , .p0 ( optlc_net_168 ) ) ; sb_2__0__mux_tree_tapbuf_size2_34 mux_left_track_57 ( .in ( { chany_top_in[2] , left_bottom_grid_pin_13_[0] } ) , .sram ( mux_tree_tapbuf_size2_34_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_115 , SYNOPSYS_UNCONNECTED_116 } ) , - .out ( chanx_left_out[28] ) , .p0 ( optlc_net_150 ) ) ; + .out ( chanx_left_out[28] ) , .p0 ( optlc_net_168 ) ) ; sb_2__0__mux_tree_tapbuf_size2 mux_left_track_59 ( .in ( { chany_top_in[1] , left_bottom_grid_pin_15_[0] } ) , .sram ( mux_tree_tapbuf_size2_35_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_117 , SYNOPSYS_UNCONNECTED_118 } ) , - .out ( chanx_left_out[29] ) , .p0 ( optlc_net_150 ) ) ; + .out ( chanx_left_out[29] ) , .p0 ( optlc_net_168 ) ) ; sb_2__0__mux_tree_tapbuf_size2_mem_0 mem_top_track_14 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) , @@ -18836,12 +18814,12 @@ sb_2__0__mux_tree_tapbuf_size2_mem mem_left_track_59 ( .pReset ( pReset ) , .ccff_head ( mux_tree_tapbuf_size2_mem_34_ccff_tail ) , .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_35_sram ) ) ; sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_W_in ) , .X ( pReset[0] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_152 ( .LO ( SYNOPSYS_UNCONNECTED_119 ) , - .HI ( optlc_net_150 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_167 ( .LO ( SYNOPSYS_UNCONNECTED_119 ) , + .HI ( optlc_net_165 ) ) ; sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_N_in ) , .X ( prog_clk[0] ) ) ; -sky130_fd_sc_hd__buf_6 FTB_54__53 ( .A ( chanx_left_in[1] ) , - .X ( ropt_net_174 ) ) ; +sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chanx_left_in[1] ) , + .X ( chany_top_out[29] ) ) ; sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chanx_left_in[2] ) , .X ( chany_top_out[28] ) ) ; sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chanx_left_in[3] ) , @@ -18854,16 +18832,16 @@ sky130_fd_sc_hd__buf_6 FTB_59__58 ( .A ( chanx_left_in[14] ) , .X ( chany_top_out[16] ) ) ; sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( chanx_left_in[15] ) , .X ( chany_top_out[15] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_120 ( .A ( BUF_net_121 ) , .Y ( pReset_N_out ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_121 ( .A ( pReset_W_in ) , .Y ( BUF_net_121 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_154 ( .LO ( SYNOPSYS_UNCONNECTED_120 ) , - .HI ( optlc_net_151 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_156 ( .LO ( SYNOPSYS_UNCONNECTED_121 ) , - .HI ( optlc_net_152 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_158 ( .LO ( SYNOPSYS_UNCONNECTED_122 ) , - .HI ( optlc_net_153 ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1337 ( .A ( ropt_net_174 ) , - .X ( chany_top_out[29] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_125 ( .A ( BUF_net_126 ) , .Y ( pReset_N_out ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_126 ( .A ( pReset_W_in ) , .Y ( BUF_net_126 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_170 ( .LO ( SYNOPSYS_UNCONNECTED_120 ) , + .HI ( optlc_net_166 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_172 ( .LO ( SYNOPSYS_UNCONNECTED_121 ) , + .HI ( optlc_net_167 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_174 ( .LO ( SYNOPSYS_UNCONNECTED_122 ) , + .HI ( optlc_net_168 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_176 ( .LO ( SYNOPSYS_UNCONNECTED_123 ) , + .HI ( optlc_net_169 ) ) ; endmodule @@ -19058,7 +19036,7 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_138 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_136 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -19158,7 +19136,7 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_137 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_135 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -19175,11 +19153,12 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_136 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .X ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_133 ( .A ( BUF_net_134 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_134 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_134 ) ) ; endmodule @@ -19198,9 +19177,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_134 ( .A ( BUF_net_135 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_135 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_135 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_131 ( .A ( BUF_net_132 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_132 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_132 ) ) ; endmodule @@ -19219,7 +19198,7 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_133 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_130 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -19234,13 +19213,14 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_128 ( .A ( BUF_net_129 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_129 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_129 ) ) ; endmodule @@ -19259,7 +19239,7 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_132 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_127 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -19343,13 +19323,12 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_130 ( .A ( BUF_net_131 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_131 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .Y ( BUF_net_131 ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_126 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .X ( out[0] ) ) ; endmodule @@ -19392,13 +19371,12 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_128 ( .A ( BUF_net_129 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_129 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .Y ( BUF_net_129 ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_125 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .X ( out[0] ) ) ; endmodule @@ -19421,9 +19399,9 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_126 ( .A ( BUF_net_127 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_127 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .Y ( BUF_net_127 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_123 ( .A ( BUF_net_124 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_124 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .Y ( BUF_net_124 ) ) ; endmodule @@ -19530,9 +19508,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_124 ( .A ( BUF_net_125 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_125 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .Y ( BUF_net_125 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_121 ( .A ( BUF_net_122 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_122 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .Y ( BUF_net_122 ) ) ; endmodule @@ -19567,9 +19545,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_122 ( .A ( BUF_net_123 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_123 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .Y ( BUF_net_123 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_119 ( .A ( BUF_net_120 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_120 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .Y ( BUF_net_120 ) ) ; endmodule @@ -19604,9 +19582,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_120 ( .A ( BUF_net_121 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_121 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .Y ( BUF_net_121 ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_118 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .X ( out[0] ) ) ; endmodule @@ -19641,9 +19618,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_118 ( .A ( BUF_net_119 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_119 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .Y ( BUF_net_119 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_116 ( .A ( BUF_net_117 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_117 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , + .Y ( BUF_net_117 ) ) ; endmodule @@ -19661,7 +19638,20 @@ sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__buf_6 FTB_29__28 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_29__28 ( .A ( copt_net_158 ) , + .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1350 ( .A ( mem_out[2] ) , + .X ( copt_net_153 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1351 ( .A ( copt_net_153 ) , + .X ( copt_net_154 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1352 ( .A ( copt_net_154 ) , + .X ( copt_net_155 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1353 ( .A ( copt_net_155 ) , + .X ( copt_net_156 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1354 ( .A ( copt_net_156 ) , + .X ( copt_net_157 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1355 ( .A ( copt_net_157 ) , + .X ( copt_net_158 ) ) ; endmodule @@ -19803,6 +19793,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , @@ -19810,13 +19802,10 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_116 ( .A ( BUF_net_117 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_117 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .Y ( BUF_net_117 ) ) ; endmodule @@ -19867,12 +19856,13 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_115 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .X ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_114 ( .A ( BUF_net_115 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_115 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_115 ) ) ; endmodule @@ -19899,9 +19889,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_113 ( .A ( BUF_net_114 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_114 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .Y ( BUF_net_114 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_112 ( .A ( BUF_net_113 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_113 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_113 ) ) ; endmodule @@ -19928,9 +19918,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_111 ( .A ( BUF_net_112 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_112 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .Y ( BUF_net_112 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_144 ( .A ( BUF_net_145 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_145 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_145 ) ) ; endmodule @@ -19957,9 +19947,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_109 ( .A ( BUF_net_110 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_110 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .Y ( BUF_net_110 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_110 ( .A ( BUF_net_111 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_111 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_111 ) ) ; endmodule @@ -19982,13 +19972,12 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_107 ( .A ( BUF_net_108 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_108 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .Y ( BUF_net_108 ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_109 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .X ( out[0] ) ) ; endmodule @@ -20123,6 +20112,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -20133,13 +20124,10 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_105 ( .A ( BUF_net_106 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_106 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .Y ( BUF_net_106 ) ) ; endmodule @@ -20170,9 +20158,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_103 ( .A ( BUF_net_104 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_104 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .Y ( BUF_net_104 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_107 ( .A ( BUF_net_108 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_108 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .Y ( BUF_net_108 ) ) ; endmodule @@ -20199,13 +20187,12 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[4] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_101 ( .A ( BUF_net_102 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_102 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .Y ( BUF_net_102 ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_106 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .X ( out[0] ) ) ; endmodule @@ -20236,9 +20223,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_99 ( .A ( BUF_net_100 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_100 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .Y ( BUF_net_100 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_142 ( .A ( BUF_net_143 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_143 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .Y ( BUF_net_143 ) ) ; endmodule @@ -20357,9 +20344,9 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_97 ( .A ( BUF_net_98 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_98 ( .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .Y ( BUF_net_98 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_104 ( .A ( BUF_net_105 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_105 ( .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .Y ( BUF_net_105 ) ) ; endmodule @@ -20469,60 +20456,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , - .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -endmodule - - -module sb_1__2__mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , p0 ) ; -input [0:9] in ; -input [0:3] sram ; -input [0:3] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; - -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -20552,6 +20485,61 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_140 ( .A ( BUF_net_141 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_141 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .Y ( BUF_net_141 ) ) ; +endmodule + + +module sb_1__2__mux_tree_tapbuf_size10_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:9] in ; +input [0:3] sram ; +input [0:3] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( in[6] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[8] ) , .A1 ( in[7] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[9] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , + .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_103 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .X ( out[0] ) ) ; endmodule @@ -20631,8 +20619,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , @@ -20656,6 +20642,8 @@ sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_102 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .X ( out[0] ) ) ; endmodule @@ -20899,37 +20887,25 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_185 ) , +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_187 ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1329 ( .A ( ccff_head[0] ) , - .X ( copt_net_146 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1330 ( .A ( copt_net_146 ) , - .X ( copt_net_147 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1331 ( .A ( copt_net_147 ) , - .X ( copt_net_148 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1332 ( .A ( copt_net_150 ) , - .X ( copt_net_149 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1333 ( .A ( copt_net_148 ) , - .X ( copt_net_150 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1334 ( .A ( copt_net_149 ) , - .X ( copt_net_151 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1360 ( .A ( copt_net_151 ) , - .X ( ropt_net_180 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1361 ( .A ( ropt_net_180 ) , - .X ( ropt_net_181 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1362 ( .A ( ropt_net_181 ) , +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1415 ( .A ( ccff_head[0] ) , .X ( ropt_net_182 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1363 ( .A ( ropt_net_182 ) , +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1416 ( .A ( ropt_net_182 ) , .X ( ropt_net_183 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1364 ( .A ( ropt_net_183 ) , +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1417 ( .A ( ropt_net_185 ) , .X ( ropt_net_184 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1365 ( .A ( ropt_net_184 ) , +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1418 ( .A ( ropt_net_183 ) , .X ( ropt_net_185 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1419 ( .A ( ropt_net_184 ) , + .X ( ropt_net_186 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1420 ( .A ( ropt_net_186 ) , + .X ( ropt_net_187 ) ) ; endmodule @@ -20968,9 +20944,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_95 ( .A ( BUF_net_96 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_96 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .Y ( BUF_net_96 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_100 ( .A ( BUF_net_101 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_101 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .Y ( BUF_net_101 ) ) ; endmodule @@ -20989,8 +20965,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -21007,10 +20981,13 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_98 ( .A ( BUF_net_99 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_99 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .Y ( BUF_net_99 ) ) ; endmodule @@ -21049,9 +21026,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_93 ( .A ( BUF_net_94 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_94 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .Y ( BUF_net_94 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_96 ( .A ( BUF_net_97 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_97 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .Y ( BUF_net_97 ) ) ; endmodule @@ -21070,8 +21047,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -21092,6 +21067,8 @@ sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_95 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .X ( out[0] ) ) ; endmodule @@ -21210,9 +21187,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_91 ( .A ( BUF_net_92 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_92 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .Y ( BUF_net_92 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_93 ( .A ( BUF_net_94 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_94 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .Y ( BUF_net_94 ) ) ; endmodule @@ -21231,8 +21208,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -21253,6 +21228,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_91 ( .A ( BUF_net_92 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_92 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .Y ( BUF_net_92 ) ) ; endmodule @@ -21271,8 +21249,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -21293,6 +21269,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_138 ( .A ( BUF_net_139 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_139 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .Y ( BUF_net_139 ) ) ; endmodule @@ -21357,7 +21336,7 @@ output pReset_W_out ; output pReset_E_out ; input prog_clk_0_S_in ; -wire ropt_net_167 ; +wire ropt_net_166 ; wire [0:0] prog_clk ; wire prog_clk_0 ; wire [0:3] mux_tree_tapbuf_size10_0_sram ; @@ -21467,7 +21446,7 @@ sb_1__2__mux_tree_tapbuf_size7_0 mux_right_track_0 ( .sram ( mux_tree_tapbuf_size7_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 } ) , - .out ( chanx_right_out[0] ) , .p0 ( optlc_net_145 ) ) ; + .out ( chanx_right_out[0] ) , .p0 ( optlc_net_150 ) ) ; sb_1__2__mux_tree_tapbuf_size7_1 mux_right_track_2 ( .in ( { right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_39_[0] , right_bottom_grid_pin_42_[0] , chany_bottom_in[8] , @@ -21475,7 +21454,7 @@ sb_1__2__mux_tree_tapbuf_size7_1 mux_right_track_2 ( .sram ( mux_tree_tapbuf_size7_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 } ) , - .out ( chanx_right_out[1] ) , .p0 ( optlc_net_145 ) ) ; + .out ( chanx_right_out[1] ) , .p0 ( optlc_net_150 ) ) ; sb_1__2__mux_tree_tapbuf_size7_2 mux_right_track_12 ( .in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_41_[0] , chany_bottom_in[4] , chany_bottom_in[15] , chany_bottom_in[26] , @@ -21483,7 +21462,7 @@ sb_1__2__mux_tree_tapbuf_size7_2 mux_right_track_12 ( .sram ( mux_tree_tapbuf_size7_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 , SYNOPSYS_UNCONNECTED_9 } ) , - .out ( chanx_right_out[6] ) , .p0 ( optlc_net_142 ) ) ; + .out ( chanx_right_out[6] ) , .p0 ( optlc_net_148 ) ) ; sb_1__2__mux_tree_tapbuf_size7_3 mux_right_track_20 ( .in ( { right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_42_[0] , chany_bottom_in[3] , chany_bottom_in[14] , chany_bottom_in[25] , @@ -21491,7 +21470,7 @@ sb_1__2__mux_tree_tapbuf_size7_3 mux_right_track_20 ( .sram ( mux_tree_tapbuf_size7_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , - .out ( chanx_right_out[10] ) , .p0 ( optlc_net_143 ) ) ; + .out ( chanx_right_out[10] ) , .p0 ( optlc_net_148 ) ) ; sb_1__2__mux_tree_tapbuf_size7_4 mux_right_track_28 ( .in ( { right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_43_[0] , chany_bottom_in[2] , chany_bottom_in[13] , chany_bottom_in[24] , @@ -21499,7 +21478,7 @@ sb_1__2__mux_tree_tapbuf_size7_4 mux_right_track_28 ( .sram ( mux_tree_tapbuf_size7_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , SYNOPSYS_UNCONNECTED_15 } ) , - .out ( chanx_right_out[14] ) , .p0 ( optlc_net_143 ) ) ; + .out ( chanx_right_out[14] ) , .p0 ( optlc_net_148 ) ) ; sb_1__2__mux_tree_tapbuf_size7_5 mux_left_track_1 ( .in ( { chanx_left_out[4] , chanx_left_out[20] , chany_bottom_in[10] , chany_bottom_in[21] , left_top_grid_pin_1_[0] , @@ -21507,7 +21486,7 @@ sb_1__2__mux_tree_tapbuf_size7_5 mux_left_track_1 ( .sram ( mux_tree_tapbuf_size7_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_16 , SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 } ) , - .out ( chanx_left_out[0] ) , .p0 ( optlc_net_144 ) ) ; + .out ( chanx_left_out[0] ) , .p0 ( optlc_net_149 ) ) ; sb_1__2__mux_tree_tapbuf_size7_6 mux_left_track_13 ( .in ( { chanx_left_out[12] , chanx_left_out[27] , chany_bottom_in[4] , chany_bottom_in[15] , chany_bottom_in[26] , left_top_grid_pin_1_[0] , @@ -21515,7 +21494,7 @@ sb_1__2__mux_tree_tapbuf_size7_6 mux_left_track_13 ( .sram ( mux_tree_tapbuf_size7_6_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 , SYNOPSYS_UNCONNECTED_21 } ) , - .out ( chanx_left_out[6] ) , .p0 ( optlc_net_144 ) ) ; + .out ( chanx_left_out[6] ) , .p0 ( optlc_net_149 ) ) ; sb_1__2__mux_tree_tapbuf_size7_7 mux_left_track_21 ( .in ( { chanx_left_out[13] , chanx_left_out[28] , chany_bottom_in[5] , chany_bottom_in[16] , chany_bottom_in[27] , @@ -21523,7 +21502,7 @@ sb_1__2__mux_tree_tapbuf_size7_7 mux_left_track_21 ( .sram ( mux_tree_tapbuf_size7_7_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_22 , SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) , - .out ( chanx_left_out[10] ) , .p0 ( optlc_net_140 ) ) ; + .out ( chanx_left_out[10] ) , .p0 ( optlc_net_151 ) ) ; sb_1__2__mux_tree_tapbuf_size7 mux_left_track_29 ( .in ( { chanx_left_out[15] , chanx_left_out[29] , chany_bottom_in[6] , chany_bottom_in[17] , chany_bottom_in[28] , @@ -21531,7 +21510,7 @@ sb_1__2__mux_tree_tapbuf_size7 mux_left_track_29 ( .sram ( mux_tree_tapbuf_size7_8_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , SYNOPSYS_UNCONNECTED_27 } ) , - .out ( chanx_left_out[14] ) , .p0 ( optlc_net_140 ) ) ; + .out ( chanx_left_out[14] ) , .p0 ( optlc_net_151 ) ) ; sb_1__2__mux_tree_tapbuf_size7_mem_0 mem_right_track_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , @@ -21584,7 +21563,7 @@ sb_1__2__mux_tree_tapbuf_size8_0 mux_right_track_4 ( .sram ( mux_tree_tapbuf_size8_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_28 , SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 , SYNOPSYS_UNCONNECTED_31 } ) , - .out ( chanx_right_out[2] ) , .p0 ( optlc_net_143 ) ) ; + .out ( chanx_right_out[2] ) , .p0 ( optlc_net_151 ) ) ; sb_1__2__mux_tree_tapbuf_size8_1 mux_left_track_3 ( .in ( { chanx_left_out[7] , chanx_left_out[21] , chany_bottom_in[0] , chany_bottom_in[11] , chany_bottom_in[22] , @@ -21593,7 +21572,7 @@ sb_1__2__mux_tree_tapbuf_size8_1 mux_left_track_3 ( .sram ( mux_tree_tapbuf_size8_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_32 , SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 , SYNOPSYS_UNCONNECTED_35 } ) , - .out ( chanx_left_out[1] ) , .p0 ( optlc_net_144 ) ) ; + .out ( chanx_left_out[1] ) , .p0 ( optlc_net_146 ) ) ; sb_1__2__mux_tree_tapbuf_size8 mux_left_track_5 ( .in ( { chanx_left_out[8] , chanx_left_out[23] , chany_bottom_in[1] , chany_bottom_in[12] , chany_bottom_in[23] , @@ -21602,7 +21581,7 @@ sb_1__2__mux_tree_tapbuf_size8 mux_left_track_5 ( .sram ( mux_tree_tapbuf_size8_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_36 , SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 , SYNOPSYS_UNCONNECTED_39 } ) , - .out ( chanx_left_out[2] ) , .p0 ( optlc_net_140 ) ) ; + .out ( chanx_left_out[2] ) , .p0 ( optlc_net_146 ) ) ; sb_1__2__mux_tree_tapbuf_size8_mem_0 mem_right_track_4 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , @@ -21627,7 +21606,7 @@ sb_1__2__mux_tree_tapbuf_size10_0 mux_right_track_6 ( .sram ( mux_tree_tapbuf_size10_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_40 , SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 , SYNOPSYS_UNCONNECTED_43 } ) , - .out ( chanx_right_out[3] ) , .p0 ( optlc_net_143 ) ) ; + .out ( chanx_right_out[3] ) , .p0 ( optlc_net_148 ) ) ; sb_1__2__mux_tree_tapbuf_size10 mux_left_track_7 ( .in ( { chanx_left_out[9] , chanx_left_out[24] , chany_bottom_in[2] , chany_bottom_in[13] , chany_bottom_in[24] , left_top_grid_pin_1_[0] , @@ -21636,7 +21615,7 @@ sb_1__2__mux_tree_tapbuf_size10 mux_left_track_7 ( .sram ( mux_tree_tapbuf_size10_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_44 , SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 , SYNOPSYS_UNCONNECTED_47 } ) , - .out ( chanx_left_out[3] ) , .p0 ( optlc_net_140 ) ) ; + .out ( chanx_left_out[3] ) , .p0 ( optlc_net_146 ) ) ; sb_1__2__mux_tree_tapbuf_size10_mem_0 mem_right_track_6 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) , @@ -21655,7 +21634,7 @@ sb_1__2__mux_tree_tapbuf_size9_0 mux_right_track_10 ( .sram ( mux_tree_tapbuf_size9_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_48 , SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 , SYNOPSYS_UNCONNECTED_51 } ) , - .out ( chanx_right_out[5] ) , .p0 ( optlc_net_143 ) ) ; + .out ( chanx_right_out[5] ) , .p0 ( optlc_net_148 ) ) ; sb_1__2__mux_tree_tapbuf_size9 mux_left_track_11 ( .in ( { chanx_left_out[11] , chanx_left_out[25] , chany_bottom_in[3] , chany_bottom_in[14] , chany_bottom_in[25] , @@ -21664,7 +21643,7 @@ sb_1__2__mux_tree_tapbuf_size9 mux_left_track_11 ( .sram ( mux_tree_tapbuf_size9_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_52 , SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 , SYNOPSYS_UNCONNECTED_55 } ) , - .out ( chanx_left_out[5] ) , .p0 ( optlc_net_144 ) ) ; + .out ( chanx_left_out[5] ) , .p0 ( optlc_net_149 ) ) ; sb_1__2__mux_tree_tapbuf_size9_mem_0 mem_right_track_10 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , @@ -21681,21 +21660,21 @@ sb_1__2__mux_tree_tapbuf_size5_0 mux_right_track_36 ( .sram ( mux_tree_tapbuf_size5_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_56 , SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 } ) , - .out ( chanx_right_out[18] ) , .p0 ( optlc_net_142 ) ) ; + .out ( chanx_right_out[18] ) , .p0 ( optlc_net_148 ) ) ; sb_1__2__mux_tree_tapbuf_size5_1 mux_right_track_44 ( .in ( { right_bottom_grid_pin_39_[0] , chany_bottom_in[0] , - chany_bottom_in[11] , chany_bottom_in[22] , chanx_right_out[17] } ) , + chany_bottom_in[11] , chany_bottom_in[22] , ropt_net_166 } ) , .sram ( mux_tree_tapbuf_size5_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 , SYNOPSYS_UNCONNECTED_61 } ) , - .out ( chanx_right_out[22] ) , .p0 ( optlc_net_142 ) ) ; + .out ( chanx_right_out[22] ) , .p0 ( optlc_net_147 ) ) ; sb_1__2__mux_tree_tapbuf_size5_2 mux_bottom_track_5 ( .in ( { chanx_left_out[8] , bottom_left_grid_pin_46_[0] , bottom_left_grid_pin_49_[0] , chanx_left_in[4] , chanx_right_out[8] } ) , .sram ( mux_tree_tapbuf_size5_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_62 , SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) , - .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_140 ) ) ; + .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_146 ) ) ; sb_1__2__mux_tree_tapbuf_size5_3 mux_bottom_track_11 ( .in ( { chanx_left_out[12] , bottom_left_grid_pin_46_[0] , bottom_left_grid_pin_49_[0] , chanx_right_out[12] , @@ -21703,14 +21682,14 @@ sb_1__2__mux_tree_tapbuf_size5_3 mux_bottom_track_11 ( .sram ( mux_tree_tapbuf_size5_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 , SYNOPSYS_UNCONNECTED_67 } ) , - .out ( chany_bottom_out[5] ) , .p0 ( optlc_net_141 ) ) ; + .out ( chany_bottom_out[5] ) , .p0 ( optlc_net_146 ) ) ; sb_1__2__mux_tree_tapbuf_size5 mux_left_track_37 ( .in ( { chanx_left_out[16] , chany_bottom_in[7] , chany_bottom_in[18] , chany_bottom_in[29] , left_bottom_grid_pin_38_[0] } ) , .sram ( mux_tree_tapbuf_size5_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_68 , SYNOPSYS_UNCONNECTED_69 , SYNOPSYS_UNCONNECTED_70 } ) , - .out ( chanx_left_out[18] ) , .p0 ( optlc_net_140 ) ) ; + .out ( chanx_left_out[18] ) , .p0 ( optlc_net_151 ) ) ; sb_1__2__mux_tree_tapbuf_size5_mem_0 mem_right_track_36 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) , @@ -21742,56 +21721,56 @@ sb_1__2__mux_tree_tapbuf_size4_0 mux_right_track_52 ( .sram ( mux_tree_tapbuf_size4_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_71 , SYNOPSYS_UNCONNECTED_72 , SYNOPSYS_UNCONNECTED_73 } ) , - .out ( chanx_right_out[26] ) , .p0 ( optlc_net_142 ) ) ; + .out ( chanx_right_out[26] ) , .p0 ( optlc_net_147 ) ) ; sb_1__2__mux_tree_tapbuf_size4_1 mux_bottom_track_13 ( .in ( { chanx_left_out[13] , bottom_left_grid_pin_44_[0] , chanx_right_out[13] , chanx_left_in[17] } ) , .sram ( mux_tree_tapbuf_size4_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_74 , SYNOPSYS_UNCONNECTED_75 , SYNOPSYS_UNCONNECTED_76 } ) , - .out ( chany_bottom_out[6] ) , .p0 ( optlc_net_140 ) ) ; + .out ( chany_bottom_out[6] ) , .p0 ( optlc_net_146 ) ) ; sb_1__2__mux_tree_tapbuf_size4_2 mux_bottom_track_15 ( .in ( { chanx_left_out[15] , bottom_left_grid_pin_45_[0] , chanx_right_out[15] , chanx_left_in[21] } ) , .sram ( mux_tree_tapbuf_size4_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_77 , SYNOPSYS_UNCONNECTED_78 , SYNOPSYS_UNCONNECTED_79 } ) , - .out ( chany_bottom_out[7] ) , .p0 ( optlc_net_141 ) ) ; + .out ( chany_bottom_out[7] ) , .p0 ( optlc_net_146 ) ) ; sb_1__2__mux_tree_tapbuf_size4_3 mux_bottom_track_17 ( .in ( { chanx_left_out[16] , bottom_left_grid_pin_46_[0] , chanx_right_out[16] , chanx_left_in[25] } ) , .sram ( mux_tree_tapbuf_size4_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_80 , SYNOPSYS_UNCONNECTED_81 , SYNOPSYS_UNCONNECTED_82 } ) , - .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_141 ) ) ; + .out ( chany_bottom_out[8] ) , .p0 ( optlc_net_146 ) ) ; sb_1__2__mux_tree_tapbuf_size4_4 mux_bottom_track_19 ( - .in ( { chanx_left_out[17] , bottom_left_grid_pin_47_[0] , - chanx_right_out[17] , chanx_left_in[29] } ) , + .in ( { chanx_left_out[17] , bottom_left_grid_pin_47_[0] , ropt_net_166 , + chanx_left_in[29] } ) , .sram ( mux_tree_tapbuf_size4_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_83 , SYNOPSYS_UNCONNECTED_84 , SYNOPSYS_UNCONNECTED_85 } ) , - .out ( chany_bottom_out[9] ) , .p0 ( optlc_net_141 ) ) ; + .out ( chany_bottom_out[9] ) , .p0 ( optlc_net_149 ) ) ; sb_1__2__mux_tree_tapbuf_size4_5 mux_bottom_track_37 ( .in ( { chanx_left_out[29] , chanx_right_in[29] , bottom_left_grid_pin_44_[0] , chanx_right_out[29] } ) , .sram ( mux_tree_tapbuf_size4_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_86 , SYNOPSYS_UNCONNECTED_87 , SYNOPSYS_UNCONNECTED_88 } ) , - .out ( chany_bottom_out[18] ) , .p0 ( optlc_net_142 ) ) ; + .out ( chany_bottom_out[18] ) , .p0 ( optlc_net_147 ) ) ; sb_1__2__mux_tree_tapbuf_size4_6 mux_left_track_45 ( .in ( { chanx_left_out[17] , chany_bottom_in[8] , chany_bottom_in[19] , left_bottom_grid_pin_39_[0] } ) , .sram ( mux_tree_tapbuf_size4_6_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_89 , SYNOPSYS_UNCONNECTED_90 , SYNOPSYS_UNCONNECTED_91 } ) , - .out ( chanx_left_out[22] ) , .p0 ( optlc_net_140 ) ) ; + .out ( chanx_left_out[22] ) , .p0 ( optlc_net_151 ) ) ; sb_1__2__mux_tree_tapbuf_size4 mux_left_track_53 ( .in ( { chanx_left_out[19] , chany_bottom_in[9] , chany_bottom_in[20] , left_bottom_grid_pin_40_[0] } ) , .sram ( mux_tree_tapbuf_size4_7_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_92 , SYNOPSYS_UNCONNECTED_93 , SYNOPSYS_UNCONNECTED_94 } ) , - .out ( chanx_left_out[26] ) , .p0 ( optlc_net_140 ) ) ; + .out ( chanx_left_out[26] ) , .p0 ( optlc_net_152 ) ) ; sb_1__2__mux_tree_tapbuf_size4_mem_0 mem_right_track_52 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , @@ -21838,7 +21817,7 @@ sb_1__2__mux_tree_tapbuf_size6_0 mux_bottom_track_1 ( .sram ( mux_tree_tapbuf_size6_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_95 , SYNOPSYS_UNCONNECTED_96 , SYNOPSYS_UNCONNECTED_97 } ) , - .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_141 ) ) ; + .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_146 ) ) ; sb_1__2__mux_tree_tapbuf_size6_1 mux_bottom_track_3 ( .in ( { chanx_left_out[7] , bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_48_[0] , bottom_left_grid_pin_51_[0] , @@ -21846,7 +21825,7 @@ sb_1__2__mux_tree_tapbuf_size6_1 mux_bottom_track_3 ( .sram ( mux_tree_tapbuf_size6_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_98 , SYNOPSYS_UNCONNECTED_99 , SYNOPSYS_UNCONNECTED_100 } ) , - .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_141 ) ) ; + .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_146 ) ) ; sb_1__2__mux_tree_tapbuf_size6_2 mux_bottom_track_7 ( .in ( { chanx_left_out[9] , bottom_left_grid_pin_44_[0] , bottom_left_grid_pin_47_[0] , bottom_left_grid_pin_50_[0] , @@ -21854,7 +21833,7 @@ sb_1__2__mux_tree_tapbuf_size6_2 mux_bottom_track_7 ( .sram ( mux_tree_tapbuf_size6_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_101 , SYNOPSYS_UNCONNECTED_102 , SYNOPSYS_UNCONNECTED_103 } ) , - .out ( chany_bottom_out[3] ) , .p0 ( optlc_net_140 ) ) ; + .out ( chany_bottom_out[3] ) , .p0 ( optlc_net_152 ) ) ; sb_1__2__mux_tree_tapbuf_size6 mux_bottom_track_9 ( .in ( { chanx_left_out[11] , bottom_left_grid_pin_45_[0] , bottom_left_grid_pin_48_[0] , bottom_left_grid_pin_51_[0] , @@ -21862,7 +21841,7 @@ sb_1__2__mux_tree_tapbuf_size6 mux_bottom_track_9 ( .sram ( mux_tree_tapbuf_size6_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_104 , SYNOPSYS_UNCONNECTED_105 , SYNOPSYS_UNCONNECTED_106 } ) , - .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_141 ) ) ; + .out ( chany_bottom_out[4] ) , .p0 ( optlc_net_146 ) ) ; sb_1__2__mux_tree_tapbuf_size6_mem_0 mem_bottom_track_1 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , @@ -21888,25 +21867,25 @@ sb_1__2__mux_tree_tapbuf_size3_0 mux_bottom_track_21 ( chanx_right_out[19] } ) , .sram ( mux_tree_tapbuf_size3_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_107 , SYNOPSYS_UNCONNECTED_108 } ) , - .out ( chany_bottom_out[10] ) , .p0 ( optlc_net_144 ) ) ; + .out ( chany_bottom_out[10] ) , .p0 ( optlc_net_149 ) ) ; sb_1__2__mux_tree_tapbuf_size3_1 mux_bottom_track_23 ( .in ( { chanx_left_out[20] , bottom_left_grid_pin_49_[0] , chanx_right_out[20] } ) , .sram ( mux_tree_tapbuf_size3_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_109 , SYNOPSYS_UNCONNECTED_110 } ) , - .out ( chany_bottom_out[11] ) , .p0 ( optlc_net_144 ) ) ; + .out ( chany_bottom_out[11] ) , .p0 ( optlc_net_149 ) ) ; sb_1__2__mux_tree_tapbuf_size3_2 mux_bottom_track_25 ( .in ( { chanx_left_out[21] , bottom_left_grid_pin_50_[0] , chanx_right_out[21] } ) , .sram ( mux_tree_tapbuf_size3_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_111 , SYNOPSYS_UNCONNECTED_112 } ) , - .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_144 ) ) ; + .out ( chany_bottom_out[12] ) , .p0 ( optlc_net_149 ) ) ; sb_1__2__mux_tree_tapbuf_size3 mux_bottom_track_27 ( .in ( { chanx_left_out[23] , bottom_left_grid_pin_51_[0] , chanx_right_out[23] } ) , .sram ( mux_tree_tapbuf_size3_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_113 , SYNOPSYS_UNCONNECTED_114 } ) , - .out ( chany_bottom_out[13] ) , .p0 ( optlc_net_144 ) ) ; + .out ( chany_bottom_out[13] ) , .p0 ( optlc_net_149 ) ) ; sb_1__2__mux_tree_tapbuf_size3_mem_0 mem_bottom_track_21 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_4_ccff_tail ) , @@ -21931,57 +21910,57 @@ sb_1__2__mux_tree_tapbuf_size2_0 mux_bottom_track_29 ( .in ( { chanx_left_out[24] , chanx_right_out[24] } ) , .sram ( mux_tree_tapbuf_size2_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_115 , SYNOPSYS_UNCONNECTED_116 } ) , - .out ( chany_bottom_out[14] ) , .p0 ( optlc_net_144 ) ) ; + .out ( chany_bottom_out[14] ) , .p0 ( optlc_net_149 ) ) ; sb_1__2__mux_tree_tapbuf_size2_1 mux_bottom_track_31 ( .in ( { chanx_left_out[25] , chanx_right_out[25] } ) , .sram ( mux_tree_tapbuf_size2_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_117 , SYNOPSYS_UNCONNECTED_118 } ) , - .out ( chany_bottom_out[15] ) , .p0 ( optlc_net_142 ) ) ; + .out ( chany_bottom_out[15] ) , .p0 ( optlc_net_149 ) ) ; sb_1__2__mux_tree_tapbuf_size2_2 mux_bottom_track_33 ( .in ( { chanx_left_out[27] , chanx_right_out[27] } ) , .sram ( mux_tree_tapbuf_size2_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_119 , SYNOPSYS_UNCONNECTED_120 } ) , - .out ( chany_bottom_out[16] ) , .p0 ( optlc_net_142 ) ) ; + .out ( chany_bottom_out[16] ) , .p0 ( optlc_net_147 ) ) ; sb_1__2__mux_tree_tapbuf_size2_3 mux_bottom_track_35 ( .in ( { chanx_left_out[28] , chanx_right_out[28] } ) , .sram ( mux_tree_tapbuf_size2_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_121 , SYNOPSYS_UNCONNECTED_122 } ) , - .out ( chany_bottom_out[17] ) , .p0 ( optlc_net_142 ) ) ; + .out ( chany_bottom_out[17] ) , .p0 ( optlc_net_147 ) ) ; sb_1__2__mux_tree_tapbuf_size2_4 mux_bottom_track_39 ( .in ( { chanx_right_in[25] , bottom_left_grid_pin_45_[0] } ) , .sram ( mux_tree_tapbuf_size2_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_123 , SYNOPSYS_UNCONNECTED_124 } ) , - .out ( chany_bottom_out[19] ) , .p0 ( optlc_net_142 ) ) ; + .out ( chany_bottom_out[19] ) , .p0 ( optlc_net_147 ) ) ; sb_1__2__mux_tree_tapbuf_size2_5 mux_bottom_track_41 ( .in ( { chanx_right_in[21] , bottom_left_grid_pin_46_[0] } ) , .sram ( mux_tree_tapbuf_size2_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_125 , SYNOPSYS_UNCONNECTED_126 } ) , - .out ( chany_bottom_out[20] ) , .p0 ( optlc_net_142 ) ) ; + .out ( chany_bottom_out[20] ) , .p0 ( optlc_net_147 ) ) ; sb_1__2__mux_tree_tapbuf_size2_6 mux_bottom_track_43 ( .in ( { chanx_right_in[17] , bottom_left_grid_pin_47_[0] } ) , .sram ( mux_tree_tapbuf_size2_6_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_127 , SYNOPSYS_UNCONNECTED_128 } ) , - .out ( chany_bottom_out[21] ) , .p0 ( optlc_net_142 ) ) ; + .out ( chany_bottom_out[21] ) , .p0 ( optlc_net_147 ) ) ; sb_1__2__mux_tree_tapbuf_size2_7 mux_bottom_track_45 ( .in ( { chanx_right_in[13] , bottom_left_grid_pin_48_[0] } ) , .sram ( mux_tree_tapbuf_size2_7_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_129 , SYNOPSYS_UNCONNECTED_130 } ) , - .out ( chany_bottom_out[22] ) , .p0 ( optlc_net_142 ) ) ; + .out ( chany_bottom_out[22] ) , .p0 ( optlc_net_147 ) ) ; sb_1__2__mux_tree_tapbuf_size2_8 mux_bottom_track_47 ( .in ( { chanx_right_in[9] , bottom_left_grid_pin_49_[0] } ) , .sram ( mux_tree_tapbuf_size2_8_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_131 , SYNOPSYS_UNCONNECTED_132 } ) , - .out ( chany_bottom_out[23] ) , .p0 ( optlc_net_144 ) ) ; + .out ( chany_bottom_out[23] ) , .p0 ( optlc_net_149 ) ) ; sb_1__2__mux_tree_tapbuf_size2_9 mux_bottom_track_49 ( .in ( { chanx_right_in[5] , bottom_left_grid_pin_50_[0] } ) , .sram ( mux_tree_tapbuf_size2_9_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_133 , SYNOPSYS_UNCONNECTED_134 } ) , - .out ( chany_bottom_out[24] ) , .p0 ( optlc_net_144 ) ) ; + .out ( chany_bottom_out[24] ) , .p0 ( optlc_net_149 ) ) ; sb_1__2__mux_tree_tapbuf_size2 mux_bottom_track_51 ( .in ( { chanx_right_in[4] , bottom_left_grid_pin_51_[0] } ) , .sram ( mux_tree_tapbuf_size2_10_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_135 , SYNOPSYS_UNCONNECTED_136 } ) , - .out ( chany_bottom_out[25] ) , .p0 ( optlc_net_144 ) ) ; + .out ( chany_bottom_out[25] ) , .p0 ( optlc_net_149 ) ) ; sb_1__2__mux_tree_tapbuf_size2_mem_0 mem_bottom_track_29 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , @@ -22039,10 +22018,10 @@ sb_1__2__mux_tree_tapbuf_size2_mem mem_bottom_track_51 ( .pReset ( pReset ) , .mem_out ( mux_tree_tapbuf_size2_10_sram ) ) ; sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_E_in ) , .X ( pReset[0] ) ) ; sky130_fd_sc_hd__buf_1 pReset_W_FTB01 ( .A ( pReset_E_in ) , - .X ( net_net_139 ) ) ; + .X ( net_net_137 ) ) ; sky130_fd_sc_hd__buf_1 pReset_E_FTB01 ( .A ( pReset_E_in ) , .X ( aps_rename_505_ ) ) ; -sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_S_in ) , +sky130_fd_sc_hd__buf_16 prog_clk_0_FTB00 ( .A ( prog_clk_0_S_in ) , .X ( prog_clk[0] ) ) ; sky130_fd_sc_hd__buf_8 FTB_49__48 ( .A ( chanx_right_in[0] ) , .X ( chany_bottom_out[28] ) ) ; @@ -22088,8 +22067,8 @@ sky130_fd_sc_hd__buf_8 FTB_69__68 ( .A ( chanx_right_in[27] ) , .X ( chanx_left_out[28] ) ) ; sky130_fd_sc_hd__buf_8 FTB_70__69 ( .A ( chanx_right_in[28] ) , .X ( chanx_left_out[29] ) ) ; -sky130_fd_sc_hd__buf_6 FTB_71__70 ( .A ( chanx_left_in[0] ) , - .X ( ropt_net_167 ) ) ; +sky130_fd_sc_hd__buf_8 FTB_71__70 ( .A ( chanx_left_in[0] ) , + .X ( chany_bottom_out[29] ) ) ; sky130_fd_sc_hd__buf_8 FTB_72__71 ( .A ( chanx_left_in[3] ) , .X ( chanx_right_out[4] ) ) ; sky130_fd_sc_hd__buf_8 FTB_73__72 ( .A ( chanx_left_in[6] ) , @@ -22108,8 +22087,8 @@ sky130_fd_sc_hd__buf_8 FTB_79__78 ( .A ( chanx_left_in[14] ) , .X ( chanx_right_out[15] ) ) ; sky130_fd_sc_hd__buf_8 FTB_80__79 ( .A ( chanx_left_in[15] ) , .X ( chanx_right_out[16] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_81__80 ( .A ( chanx_left_in[16] ) , - .X ( chanx_right_out[17] ) ) ; +sky130_fd_sc_hd__buf_1 FTB_81__80 ( .A ( chanx_left_in[16] ) , + .X ( ropt_net_166 ) ) ; sky130_fd_sc_hd__buf_8 FTB_82__81 ( .A ( chanx_left_in[18] ) , .X ( chanx_right_out[19] ) ) ; sky130_fd_sc_hd__buf_8 FTB_83__82 ( .A ( chanx_left_in[19] ) , @@ -22129,24 +22108,26 @@ sky130_fd_sc_hd__buf_8 FTB_89__88 ( .A ( chanx_left_in[27] ) , sky130_fd_sc_hd__buf_8 FTB_90__89 ( .A ( chanx_left_in[28] ) , .X ( chanx_right_out[29] ) ) ; sky130_fd_sc_hd__buf_8 FTB_91__90 ( .A ( SC_IN_BOT ) , .X ( SC_OUT_BOT ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_139 ( .A ( net_net_139 ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_137 ( .A ( net_net_137 ) , .X ( pReset_W_out ) ) ; -sky130_fd_sc_hd__conb_1 optlc_142 ( .LO ( SYNOPSYS_UNCONNECTED_137 ) , - .HI ( optlc_net_140 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_144 ( .LO ( SYNOPSYS_UNCONNECTED_138 ) , - .HI ( optlc_net_141 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_146 ( .LO ( SYNOPSYS_UNCONNECTED_139 ) , - .HI ( optlc_net_142 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_148 ( .LO ( SYNOPSYS_UNCONNECTED_140 ) , - .HI ( optlc_net_143 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_150 ( .LO ( SYNOPSYS_UNCONNECTED_141 ) , - .HI ( optlc_net_144 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_152 ( .LO ( SYNOPSYS_UNCONNECTED_142 ) , - .HI ( optlc_net_145 ) ) ; -sky130_fd_sc_hd__buf_6 ZBUF_6_f_inst_153 ( .A ( aps_rename_505_ ) , +sky130_fd_sc_hd__conb_1 optlc_148 ( .LO ( SYNOPSYS_UNCONNECTED_137 ) , + .HI ( optlc_net_146 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_150 ( .LO ( SYNOPSYS_UNCONNECTED_138 ) , + .HI ( optlc_net_147 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_152 ( .LO ( SYNOPSYS_UNCONNECTED_139 ) , + .HI ( optlc_net_148 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_155 ( .LO ( SYNOPSYS_UNCONNECTED_140 ) , + .HI ( optlc_net_149 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_157 ( .LO ( SYNOPSYS_UNCONNECTED_141 ) , + .HI ( optlc_net_150 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_159 ( .LO ( SYNOPSYS_UNCONNECTED_142 ) , + .HI ( optlc_net_151 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_161 ( .LO ( SYNOPSYS_UNCONNECTED_143 ) , + .HI ( optlc_net_152 ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_6_f_inst_162 ( .A ( aps_rename_505_ ) , .X ( pReset_E_out ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1349 ( .A ( ropt_net_167 ) , - .X ( chany_bottom_out[29] ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1399 ( .A ( ropt_net_166 ) , + .X ( chanx_right_out[17] ) ) ; endmodule @@ -22164,7 +22145,7 @@ sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; -sky130_fd_sc_hd__buf_1 FTB_44__43 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_44__43 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; endmodule @@ -22631,10 +22612,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -22650,8 +22628,7 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( out[0] ) ) ; endmodule @@ -23977,7 +23954,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; @@ -24082,7 +24059,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; @@ -24744,20 +24721,26 @@ sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ; sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1366 ( .A ( copt_net_175 ) , +sky130_fd_sc_hd__buf_1 ropt_h_inst_1366 ( .A ( copt_net_175 ) , .X ( ropt_net_178 ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1360 ( .A ( copt_net_174 ) , .X ( copt_net_172 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1361 ( .A ( copt_net_172 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1361 ( .A ( ropt_net_181 ) , .X ( copt_net_173 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1362 ( .A ( ropt_net_179 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1362 ( .A ( ccff_head[0] ) , .X ( copt_net_174 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1363 ( .A ( copt_net_173 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1363 ( .A ( ropt_net_183 ) , .X ( copt_net_175 ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1364 ( .A ( ropt_net_178 ) , .X ( copt_net_176 ) ) ; -sky130_fd_sc_hd__buf_1 ropt_h_inst_1367 ( .A ( ccff_head[0] ) , +sky130_fd_sc_hd__buf_4 ropt_h_inst_1371 ( .A ( ropt_net_180 ) , + .X ( ropt_net_183 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1367 ( .A ( copt_net_173 ) , .X ( ropt_net_179 ) ) ; +sky130_fd_sc_hd__dlygate4sd2_1 ropt_h_inst_1368 ( .A ( ropt_net_179 ) , + .X ( ropt_net_180 ) ) ; +sky130_fd_sc_hd__buf_1 ropt_h_inst_1369 ( .A ( copt_net_172 ) , + .X ( ropt_net_181 ) ) ; endmodule @@ -24836,7 +24819,7 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ; -sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_4_0_ ( +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; @@ -25666,8 +25649,7 @@ sb_1__1__mux_tree_tapbuf_size10_9 mux_left_track_5 ( .sram ( mux_tree_tapbuf_size10_9_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_69 , SYNOPSYS_UNCONNECTED_70 , SYNOPSYS_UNCONNECTED_71 , SYNOPSYS_UNCONNECTED_72 } ) , - .out ( { ropt_net_180 } ) , - .p0 ( optlc_net_159 ) ) ; + .out ( chanx_left_out[2] ) , .p0 ( optlc_net_159 ) ) ; sb_1__1__mux_tree_tapbuf_size10_10 mux_left_track_13 ( .in ( { chany_bottom_out[12] , chany_top_in[13] , chany_bottom_out[27] , chanx_left_out[12] , chanx_left_out[27] , chany_bottom_in[5] , @@ -25815,7 +25797,8 @@ sb_1__1__mux_tree_tapbuf_size12_6 mux_left_track_7 ( .sram ( mux_tree_tapbuf_size12_6_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_105 , SYNOPSYS_UNCONNECTED_106 , SYNOPSYS_UNCONNECTED_107 , SYNOPSYS_UNCONNECTED_108 } ) , - .out ( chanx_left_out[3] ) , .p0 ( optlc_net_159 ) ) ; + .out ( { ropt_net_182 } ) , + .p0 ( optlc_net_159 ) ) ; sb_1__1__mux_tree_tapbuf_size12 mux_left_track_11 ( .in ( { chany_bottom_out[11] , chany_top_in[17] , chany_bottom_out[25] , chanx_left_out[11] , chanx_left_out[25] , chany_bottom_in[4] , @@ -25960,7 +25943,8 @@ sb_1__1__mux_tree_tapbuf_size6_4 mux_right_track_44 ( .sram ( mux_tree_tapbuf_size6_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_141 , SYNOPSYS_UNCONNECTED_142 , SYNOPSYS_UNCONNECTED_143 } ) , - .out ( chanx_right_out[22] ) , .p0 ( optlc_net_158 ) ) ; + .out ( { ZBUF_6_f_0 } ) , + .p0 ( optlc_net_158 ) ) ; sb_1__1__mux_tree_tapbuf_size6_5 mux_right_track_52 ( .in ( { chany_bottom_out[19] , chany_top_in[25] , right_bottom_grid_pin_41_[0] , chany_top_out[19] , @@ -26073,9 +26057,8 @@ sb_1__1__mux_tree_tapbuf_size6_mem_10 mem_left_track_45 ( .pReset ( pReset ) , .mem_out ( mux_tree_tapbuf_size6_10_sram ) ) ; sb_1__1__mux_tree_tapbuf_size6_mem mem_left_track_53 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , - .ccff_head ( mux_tree_tapbuf_size6_mem_10_ccff_tail ) , - .ccff_tail ( { copt_net_170 } ) , - .mem_out ( mux_tree_tapbuf_size6_11_sram ) ) ; + .ccff_head ( mux_tree_tapbuf_size6_mem_10_ccff_tail ) , + .ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size6_11_sram ) ) ; sky130_fd_sc_hd__buf_4 Test_en_N_FTB01 ( .A ( Test_en_S_in ) , .X ( Test_en_N_out ) ) ; sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_E_in ) , .X ( pReset[0] ) ) ; @@ -26255,10 +26238,10 @@ sky130_fd_sc_hd__conb_1 optlc_166 ( .LO ( SYNOPSYS_UNCONNECTED_169 ) , .HI ( optlc_net_160 ) ) ; sky130_fd_sc_hd__conb_1 optlc_168 ( .LO ( SYNOPSYS_UNCONNECTED_170 ) , .HI ( optlc_net_161 ) ) ; -sky130_fd_sc_hd__buf_8 copt_h_inst_1358 ( .A ( copt_net_170 ) , - .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__buf_6 ropt_mt_inst_1368 ( .A ( ropt_net_180 ) , - .X ( chanx_left_out[2] ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_6_f_inst_1350 ( .A ( ZBUF_6_f_0 ) , + .X ( chanx_right_out[22] ) ) ; +sky130_fd_sc_hd__buf_4 ropt_mt_inst_1370 ( .A ( ropt_net_182 ) , + .X ( chanx_left_out[3] ) ) ; endmodule @@ -26365,9 +26348,9 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_144 ( .A ( BUF_net_145 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_145 ( .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .Y ( BUF_net_145 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_147 ( .A ( BUF_net_148 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_148 ( .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .Y ( BUF_net_148 ) ) ; endmodule @@ -26388,6 +26371,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -26410,13 +26395,10 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( +sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_130 ( .A ( BUF_net_131 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_131 ( .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .Y ( BUF_net_131 ) ) ; endmodule @@ -26463,9 +26445,9 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_128 ( .A ( BUF_net_129 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_129 ( .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , - .Y ( BUF_net_129 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_135 ( .A ( BUF_net_136 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_136 ( .A ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , + .Y ( BUF_net_136 ) ) ; endmodule @@ -26536,9 +26518,9 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_126 ( .A ( BUF_net_127 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_127 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , - .Y ( BUF_net_127 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_133 ( .A ( BUF_net_134 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_134 ( .A ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , + .Y ( BUF_net_134 ) ) ; endmodule @@ -26685,9 +26667,9 @@ sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_124 ( .A ( BUF_net_125 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_125 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , - .Y ( BUF_net_125 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_131 ( .A ( BUF_net_132 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_132 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .Y ( BUF_net_132 ) ) ; endmodule @@ -26707,8 +26689,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , @@ -26728,10 +26708,13 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__mux2_2 mux_l4_in_0_ ( +sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[3] ) , .X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_129 ( .A ( BUF_net_130 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_130 ( .A ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , + .Y ( BUF_net_130 ) ) ; endmodule @@ -26926,9 +26909,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_122 ( .A ( BUF_net_123 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_123 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_123 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_127 ( .A ( BUF_net_128 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_128 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_128 ) ) ; endmodule @@ -26947,7 +26930,7 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_121 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_126 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -26967,9 +26950,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_119 ( .A ( BUF_net_120 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_120 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_120 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_124 ( .A ( BUF_net_125 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_125 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_125 ) ) ; endmodule @@ -27008,9 +26991,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_117 ( .A ( BUF_net_118 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_118 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_118 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_122 ( .A ( BUF_net_123 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_123 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_123 ) ) ; endmodule @@ -27029,9 +27012,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_115 ( .A ( BUF_net_116 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_116 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_116 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_120 ( .A ( BUF_net_121 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_121 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_121 ) ) ; endmodule @@ -27050,9 +27033,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_113 ( .A ( BUF_net_114 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_114 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_114 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_118 ( .A ( BUF_net_119 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_119 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_119 ) ) ; endmodule @@ -27066,13 +27049,14 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_116 ( .A ( BUF_net_117 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_117 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_117 ) ) ; endmodule @@ -27091,9 +27075,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_111 ( .A ( BUF_net_112 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_112 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_112 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_114 ( .A ( BUF_net_115 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_115 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_115 ) ) ; endmodule @@ -27236,9 +27220,9 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_109 ( .A ( BUF_net_110 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_110 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .Y ( BUF_net_110 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_112 ( .A ( BUF_net_113 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_113 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .Y ( BUF_net_113 ) ) ; endmodule @@ -27261,9 +27245,9 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_107 ( .A ( BUF_net_108 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_108 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .Y ( BUF_net_108 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_110 ( .A ( BUF_net_111 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_111 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .Y ( BUF_net_111 ) ) ; endmodule @@ -27286,9 +27270,9 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_105 ( .A ( BUF_net_106 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_106 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .Y ( BUF_net_106 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_108 ( .A ( BUF_net_109 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_109 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .Y ( BUF_net_109 ) ) ; endmodule @@ -27488,6 +27472,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , @@ -27499,8 +27485,6 @@ sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_104 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .X ( out[0] ) ) ; endmodule @@ -27544,8 +27528,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , @@ -27557,6 +27539,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_106 ( .A ( BUF_net_107 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_107 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_107 ) ) ; endmodule @@ -27583,9 +27568,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_102 ( .A ( BUF_net_103 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_103 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .Y ( BUF_net_103 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_104 ( .A ( BUF_net_105 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_105 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_105 ) ) ; endmodule @@ -27784,9 +27769,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_100 ( .A ( BUF_net_101 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_101 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .Y ( BUF_net_101 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_102 ( .A ( BUF_net_103 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_103 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .Y ( BUF_net_103 ) ) ; endmodule @@ -27803,6 +27788,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -27817,8 +27804,6 @@ sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_99 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .X ( out[0] ) ) ; endmodule @@ -27849,7 +27834,7 @@ sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_98 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_101 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -27881,9 +27866,8 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_96 ( .A ( BUF_net_97 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_97 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .Y ( BUF_net_97 ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_100 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .X ( out[0] ) ) ; endmodule @@ -28251,35 +28235,35 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_185 ) , +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_193 ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1330 ( .A ( copt_net_155 ) , - .X ( copt_net_152 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1331 ( .A ( copt_net_157 ) , - .X ( copt_net_153 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1332 ( .A ( copt_net_152 ) , - .X ( copt_net_154 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1333 ( .A ( ccff_head[0] ) , - .X ( copt_net_155 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1334 ( .A ( copt_net_153 ) , - .X ( copt_net_156 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1335 ( .A ( copt_net_154 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1340 ( .A ( copt_net_159 ) , .X ( copt_net_157 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1357 ( .A ( copt_net_156 ) , - .X ( ropt_net_181 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1358 ( .A ( ropt_net_181 ) , - .X ( ropt_net_182 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1359 ( .A ( ropt_net_184 ) , - .X ( ropt_net_183 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1360 ( .A ( ropt_net_182 ) , - .X ( ropt_net_184 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1361 ( .A ( ropt_net_183 ) , - .X ( ropt_net_185 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1341 ( .A ( copt_net_157 ) , + .X ( copt_net_158 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1342 ( .A ( copt_net_160 ) , + .X ( copt_net_159 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1343 ( .A ( ccff_head[0] ) , + .X ( copt_net_160 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1344 ( .A ( copt_net_158 ) , + .X ( copt_net_161 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1345 ( .A ( copt_net_161 ) , + .X ( copt_net_162 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1371 ( .A ( copt_net_162 ) , + .X ( ropt_net_190 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1372 ( .A ( ropt_net_192 ) , + .X ( ropt_net_191 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1373 ( .A ( ropt_net_190 ) , + .X ( ropt_net_192 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1374 ( .A ( ropt_net_194 ) , + .X ( ropt_net_193 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1375 ( .A ( ropt_net_191 ) , + .X ( ropt_net_194 ) ) ; endmodule @@ -28358,7 +28342,7 @@ sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_95 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_99 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -28478,9 +28462,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_93 ( .A ( BUF_net_94 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_94 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .Y ( BUF_net_94 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_97 ( .A ( BUF_net_98 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_98 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .Y ( BUF_net_98 ) ) ; endmodule @@ -28599,9 +28583,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_142 ( .A ( BUF_net_143 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_143 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , - .Y ( BUF_net_143 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_95 ( .A ( BUF_net_96 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_96 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .Y ( BUF_net_96 ) ) ; endmodule @@ -28620,8 +28604,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -28638,10 +28620,13 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_93 ( .A ( BUF_net_94 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_94 ( .A ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , + .Y ( BUF_net_94 ) ) ; endmodule @@ -28756,7 +28741,7 @@ output prog_clk_3_N_out ; input clk_3_S_in ; output clk_3_N_out ; -wire ropt_net_170 ; +wire ropt_net_176 ; wire [0:0] prog_clk ; wire prog_clk_0 ; wire [0:3] mux_tree_tapbuf_size10_0_sram ; @@ -28866,7 +28851,7 @@ sb_1__0__mux_tree_tapbuf_size7_0 mux_top_track_0 ( .sram ( mux_tree_tapbuf_size7_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 } ) , - .out ( chany_top_out[0] ) , .p0 ( optlc_net_146 ) ) ; + .out ( chany_top_out[0] ) , .p0 ( optlc_net_154 ) ) ; sb_1__0__mux_tree_tapbuf_size7_1 mux_right_track_0 ( .in ( { chany_top_in[10] , chany_top_in[21] , right_bottom_grid_pin_1_[0] , right_bottom_grid_pin_7_[0] , @@ -28875,7 +28860,7 @@ sb_1__0__mux_tree_tapbuf_size7_1 mux_right_track_0 ( .sram ( mux_tree_tapbuf_size7_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 } ) , - .out ( chanx_right_out[0] ) , .p0 ( optlc_net_151 ) ) ; + .out ( chanx_right_out[0] ) , .p0 ( optlc_net_154 ) ) ; sb_1__0__mux_tree_tapbuf_size7_2 mux_right_track_12 ( .in ( { chany_top_in[4] , chany_top_in[15] , chany_top_in[26] , right_bottom_grid_pin_1_[0] , right_bottom_grid_pin_13_[0] , @@ -28883,7 +28868,7 @@ sb_1__0__mux_tree_tapbuf_size7_2 mux_right_track_12 ( .sram ( mux_tree_tapbuf_size7_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 , SYNOPSYS_UNCONNECTED_9 } ) , - .out ( chanx_right_out[6] ) , .p0 ( optlc_net_151 ) ) ; + .out ( chanx_right_out[6] ) , .p0 ( optlc_net_154 ) ) ; sb_1__0__mux_tree_tapbuf_size7_3 mux_right_track_20 ( .in ( { chany_top_in[5] , chany_top_in[16] , chany_top_in[27] , right_bottom_grid_pin_3_[0] , right_bottom_grid_pin_15_[0] , @@ -28891,7 +28876,7 @@ sb_1__0__mux_tree_tapbuf_size7_3 mux_right_track_20 ( .sram ( mux_tree_tapbuf_size7_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , - .out ( chanx_right_out[10] ) , .p0 ( optlc_net_147 ) ) ; + .out ( chanx_right_out[10] ) , .p0 ( optlc_net_150 ) ) ; sb_1__0__mux_tree_tapbuf_size7_4 mux_right_track_28 ( .in ( { chany_top_in[6] , chany_top_in[17] , chany_top_in[28] , right_bottom_grid_pin_5_[0] , right_bottom_grid_pin_17_[0] , @@ -28899,7 +28884,7 @@ sb_1__0__mux_tree_tapbuf_size7_4 mux_right_track_28 ( .sram ( mux_tree_tapbuf_size7_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , SYNOPSYS_UNCONNECTED_15 } ) , - .out ( chanx_right_out[14] ) , .p0 ( optlc_net_147 ) ) ; + .out ( chanx_right_out[14] ) , .p0 ( optlc_net_150 ) ) ; sb_1__0__mux_tree_tapbuf_size7_5 mux_left_track_3 ( .in ( { chany_top_in[10] , chany_top_in[21] , chanx_left_out[7] , chanx_left_out[21] , left_bottom_grid_pin_3_[0] , @@ -28907,7 +28892,7 @@ sb_1__0__mux_tree_tapbuf_size7_5 mux_left_track_3 ( .sram ( mux_tree_tapbuf_size7_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_16 , SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 } ) , - .out ( chanx_left_out[1] ) , .p0 ( optlc_net_146 ) ) ; + .out ( chanx_left_out[1] ) , .p0 ( optlc_net_151 ) ) ; sb_1__0__mux_tree_tapbuf_size7_6 mux_left_track_5 ( .in ( { chany_top_in[9] , chany_top_in[20] , chanx_left_out[8] , chanx_left_out[23] , left_bottom_grid_pin_5_[0] , @@ -28915,7 +28900,7 @@ sb_1__0__mux_tree_tapbuf_size7_6 mux_left_track_5 ( .sram ( mux_tree_tapbuf_size7_6_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 , SYNOPSYS_UNCONNECTED_21 } ) , - .out ( chanx_left_out[2] ) , .p0 ( optlc_net_148 ) ) ; + .out ( chanx_left_out[2] ) , .p0 ( optlc_net_149 ) ) ; sb_1__0__mux_tree_tapbuf_size7_7 mux_left_track_13 ( .in ( { chany_top_in[6] , chany_top_in[17] , chany_top_in[28] , chanx_left_out[12] , chanx_left_out[27] , left_bottom_grid_pin_1_[0] , @@ -28923,7 +28908,7 @@ sb_1__0__mux_tree_tapbuf_size7_7 mux_left_track_13 ( .sram ( mux_tree_tapbuf_size7_7_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_22 , SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) , - .out ( chanx_left_out[6] ) , .p0 ( optlc_net_148 ) ) ; + .out ( chanx_left_out[6] ) , .p0 ( optlc_net_149 ) ) ; sb_1__0__mux_tree_tapbuf_size7_8 mux_left_track_21 ( .in ( { chany_top_in[5] , chany_top_in[16] , chany_top_in[27] , chanx_left_out[13] , chanx_left_out[28] , left_bottom_grid_pin_3_[0] , @@ -28931,7 +28916,7 @@ sb_1__0__mux_tree_tapbuf_size7_8 mux_left_track_21 ( .sram ( mux_tree_tapbuf_size7_8_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , SYNOPSYS_UNCONNECTED_27 } ) , - .out ( chanx_left_out[10] ) , .p0 ( optlc_net_146 ) ) ; + .out ( chanx_left_out[10] ) , .p0 ( optlc_net_149 ) ) ; sb_1__0__mux_tree_tapbuf_size7 mux_left_track_29 ( .in ( { chany_top_in[4] , chany_top_in[15] , chany_top_in[26] , chanx_left_out[15] , chanx_left_out[29] , left_bottom_grid_pin_5_[0] , @@ -28939,7 +28924,7 @@ sb_1__0__mux_tree_tapbuf_size7 mux_left_track_29 ( .sram ( mux_tree_tapbuf_size7_9_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_28 , SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 } ) , - .out ( chanx_left_out[14] ) , .p0 ( optlc_net_146 ) ) ; + .out ( chanx_left_out[14] ) , .p0 ( optlc_net_149 ) ) ; sb_1__0__mux_tree_tapbuf_size7_mem_0 mem_top_track_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , @@ -28996,7 +28981,7 @@ sb_1__0__mux_tree_tapbuf_size6_0 mux_top_track_2 ( .sram ( mux_tree_tapbuf_size6_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 , SYNOPSYS_UNCONNECTED_33 } ) , - .out ( chany_top_out[1] ) , .p0 ( optlc_net_151 ) ) ; + .out ( chany_top_out[1] ) , .p0 ( optlc_net_152 ) ) ; sb_1__0__mux_tree_tapbuf_size6_1 mux_top_track_6 ( .in ( { top_left_grid_pin_44_[0] , top_left_grid_pin_47_[0] , top_left_grid_pin_50_[0] , chanx_right_in[5] , chanx_left_out[9] , @@ -29004,7 +28989,7 @@ sb_1__0__mux_tree_tapbuf_size6_1 mux_top_track_6 ( .sram ( mux_tree_tapbuf_size6_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_34 , SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) , - .out ( chany_top_out[3] ) , .p0 ( optlc_net_151 ) ) ; + .out ( chany_top_out[3] ) , .p0 ( optlc_net_152 ) ) ; sb_1__0__mux_tree_tapbuf_size6 mux_top_track_8 ( .in ( { chany_top_out[19] , top_left_grid_pin_48_[0] , top_left_grid_pin_51_[0] , chanx_right_in[9] , chanx_left_out[11] , @@ -29012,7 +28997,7 @@ sb_1__0__mux_tree_tapbuf_size6 mux_top_track_8 ( .sram ( mux_tree_tapbuf_size6_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 , SYNOPSYS_UNCONNECTED_39 } ) , - .out ( chany_top_out[4] ) , .p0 ( optlc_net_150 ) ) ; + .out ( chany_top_out[4] ) , .p0 ( optlc_net_152 ) ) ; sb_1__0__mux_tree_tapbuf_size6_mem_0 mem_top_track_2 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) , @@ -29034,42 +29019,42 @@ sb_1__0__mux_tree_tapbuf_size5_0 mux_top_track_4 ( .sram ( mux_tree_tapbuf_size5_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_40 , SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 } ) , - .out ( chany_top_out[2] ) , .p0 ( optlc_net_150 ) ) ; + .out ( chany_top_out[2] ) , .p0 ( optlc_net_152 ) ) ; sb_1__0__mux_tree_tapbuf_size5_1 mux_top_track_10 ( .in ( { top_left_grid_pin_46_[0] , top_left_grid_pin_49_[0] , chanx_left_out[12] , chanx_right_in[13] , chanx_right_out[12] } ) , .sram ( mux_tree_tapbuf_size5_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 , SYNOPSYS_UNCONNECTED_45 } ) , - .out ( chany_top_out[5] ) , .p0 ( optlc_net_149 ) ) ; + .out ( chany_top_out[5] ) , .p0 ( optlc_net_155 ) ) ; sb_1__0__mux_tree_tapbuf_size5_2 mux_right_track_36 ( .in ( { chany_top_in[7] , chany_top_in[18] , chany_top_in[29] , right_bottom_grid_pin_7_[0] , chanx_right_out[16] } ) , .sram ( mux_tree_tapbuf_size5_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_46 , SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) , - .out ( chanx_right_out[18] ) , .p0 ( optlc_net_147 ) ) ; + .out ( chanx_right_out[18] ) , .p0 ( optlc_net_150 ) ) ; sb_1__0__mux_tree_tapbuf_size5_3 mux_left_track_37 ( .in ( { chany_top_in[3] , chany_top_in[14] , chany_top_in[25] , chanx_left_out[16] , left_bottom_grid_pin_7_[0] } ) , .sram ( mux_tree_tapbuf_size5_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 , SYNOPSYS_UNCONNECTED_51 } ) , - .out ( chanx_left_out[18] ) , .p0 ( optlc_net_146 ) ) ; + .out ( chanx_left_out[18] ) , .p0 ( optlc_net_151 ) ) ; sb_1__0__mux_tree_tapbuf_size5_4 mux_left_track_45 ( .in ( { chany_top_in[2] , chany_top_in[13] , chany_top_in[24] , chanx_left_out[17] , left_bottom_grid_pin_9_[0] } ) , .sram ( mux_tree_tapbuf_size5_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_52 , SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 } ) , - .out ( chanx_left_out[22] ) , .p0 ( optlc_net_146 ) ) ; + .out ( chanx_left_out[22] ) , .p0 ( optlc_net_151 ) ) ; sb_1__0__mux_tree_tapbuf_size5 mux_left_track_53 ( .in ( { chany_top_in[1] , chany_top_in[12] , chany_top_in[23] , chanx_left_out[19] , left_bottom_grid_pin_11_[0] } ) , .sram ( mux_tree_tapbuf_size5_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 , SYNOPSYS_UNCONNECTED_57 } ) , - .out ( chanx_left_out[26] ) , .p0 ( optlc_net_148 ) ) ; + .out ( chanx_left_out[26] ) , .p0 ( optlc_net_149 ) ) ; sb_1__0__mux_tree_tapbuf_size5_mem_0 mem_top_track_4 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , @@ -29105,14 +29090,14 @@ sb_1__0__mux_tree_tapbuf_size4_0 mux_top_track_12 ( .sram ( mux_tree_tapbuf_size4_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_58 , SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) , - .out ( chany_top_out[6] ) , .p0 ( optlc_net_151 ) ) ; + .out ( chany_top_out[6] ) , .p0 ( optlc_net_152 ) ) ; sb_1__0__mux_tree_tapbuf_size4_1 mux_top_track_14 ( .in ( { chany_top_out[19] , chanx_left_out[15] , chanx_right_in[21] , chanx_right_out[15] } ) , .sram ( mux_tree_tapbuf_size4_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 , SYNOPSYS_UNCONNECTED_63 } ) , - .out ( chany_top_out[7] ) , .p0 ( optlc_net_147 ) ) ; + .out ( chany_top_out[7] ) , .p0 ( optlc_net_150 ) ) ; sb_1__0__mux_tree_tapbuf_size4_2 mux_top_track_16 ( .in ( { top_left_grid_pin_46_[0] , chanx_left_out[16] , chanx_right_in[25] , chanx_right_out[16] } ) , @@ -29126,21 +29111,21 @@ sb_1__0__mux_tree_tapbuf_size4_3 mux_top_track_18 ( .sram ( mux_tree_tapbuf_size4_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 , SYNOPSYS_UNCONNECTED_69 } ) , - .out ( chany_top_out[9] ) , .p0 ( optlc_net_150 ) ) ; + .out ( chany_top_out[9] ) , .p0 ( optlc_net_155 ) ) ; sb_1__0__mux_tree_tapbuf_size4_4 mux_right_track_44 ( .in ( { chany_top_in[8] , chany_top_in[19] , right_bottom_grid_pin_9_[0] , chanx_right_out[17] } ) , .sram ( mux_tree_tapbuf_size4_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_70 , SYNOPSYS_UNCONNECTED_71 , SYNOPSYS_UNCONNECTED_72 } ) , - .out ( chanx_right_out[22] ) , .p0 ( optlc_net_147 ) ) ; + .out ( chanx_right_out[22] ) , .p0 ( optlc_net_150 ) ) ; sb_1__0__mux_tree_tapbuf_size4 mux_right_track_52 ( .in ( { chany_top_in[9] , chany_top_in[20] , right_bottom_grid_pin_11_[0] , chanx_right_out[19] } ) , .sram ( mux_tree_tapbuf_size4_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_73 , SYNOPSYS_UNCONNECTED_74 , SYNOPSYS_UNCONNECTED_75 } ) , - .out ( chanx_right_out[26] ) , .p0 ( optlc_net_147 ) ) ; + .out ( chanx_right_out[26] ) , .p0 ( optlc_net_150 ) ) ; sb_1__0__mux_tree_tapbuf_size4_mem_0 mem_top_track_12 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) , @@ -29176,31 +29161,31 @@ sb_1__0__mux_tree_tapbuf_size3_0 mux_top_track_20 ( chanx_right_out[19] } ) , .sram ( mux_tree_tapbuf_size3_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_76 , SYNOPSYS_UNCONNECTED_77 } ) , - .out ( chany_top_out[10] ) , .p0 ( optlc_net_149 ) ) ; + .out ( chany_top_out[10] ) , .p0 ( optlc_net_155 ) ) ; sb_1__0__mux_tree_tapbuf_size3_1 mux_top_track_22 ( .in ( { top_left_grid_pin_49_[0] , chanx_left_out[20] , chanx_right_out[20] } ) , .sram ( mux_tree_tapbuf_size3_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_78 , SYNOPSYS_UNCONNECTED_79 } ) , - .out ( chany_top_out[11] ) , .p0 ( optlc_net_149 ) ) ; + .out ( chany_top_out[11] ) , .p0 ( optlc_net_156 ) ) ; sb_1__0__mux_tree_tapbuf_size3_2 mux_top_track_24 ( .in ( { top_left_grid_pin_50_[0] , chanx_left_out[21] , chanx_right_out[21] } ) , .sram ( mux_tree_tapbuf_size3_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_80 , SYNOPSYS_UNCONNECTED_81 } ) , - .out ( chany_top_out[12] ) , .p0 ( optlc_net_149 ) ) ; + .out ( chany_top_out[12] ) , .p0 ( optlc_net_155 ) ) ; sb_1__0__mux_tree_tapbuf_size3_3 mux_top_track_26 ( .in ( { top_left_grid_pin_51_[0] , chanx_left_out[23] , chanx_right_out[23] } ) , .sram ( mux_tree_tapbuf_size3_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_82 , SYNOPSYS_UNCONNECTED_83 } ) , - .out ( chany_top_out[13] ) , .p0 ( optlc_net_150 ) ) ; + .out ( chany_top_out[13] ) , .p0 ( optlc_net_155 ) ) ; sb_1__0__mux_tree_tapbuf_size3 mux_top_track_36 ( .in ( { top_left_grid_pin_44_[0] , chanx_left_out[29] , chanx_right_out[29] } ) , .sram ( mux_tree_tapbuf_size3_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_84 , SYNOPSYS_UNCONNECTED_85 } ) , - .out ( chany_top_out[18] ) , .p0 ( optlc_net_149 ) ) ; + .out ( chany_top_out[18] ) , .p0 ( optlc_net_156 ) ) ; sb_1__0__mux_tree_tapbuf_size3_mem_0 mem_top_track_20 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) , @@ -29230,57 +29215,57 @@ sb_1__0__mux_tree_tapbuf_size2_0 mux_top_track_28 ( .in ( { chanx_left_out[24] , chanx_right_out[24] } ) , .sram ( mux_tree_tapbuf_size2_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_86 , SYNOPSYS_UNCONNECTED_87 } ) , - .out ( chany_top_out[14] ) , .p0 ( optlc_net_150 ) ) ; + .out ( chany_top_out[14] ) , .p0 ( optlc_net_155 ) ) ; sb_1__0__mux_tree_tapbuf_size2_1 mux_top_track_30 ( .in ( { chanx_left_out[25] , chanx_right_out[25] } ) , .sram ( mux_tree_tapbuf_size2_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_88 , SYNOPSYS_UNCONNECTED_89 } ) , - .out ( chany_top_out[15] ) , .p0 ( optlc_net_150 ) ) ; + .out ( chany_top_out[15] ) , .p0 ( optlc_net_152 ) ) ; sb_1__0__mux_tree_tapbuf_size2_2 mux_top_track_32 ( .in ( { chanx_left_out[27] , chanx_right_out[27] } ) , .sram ( mux_tree_tapbuf_size2_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_90 , SYNOPSYS_UNCONNECTED_91 } ) , - .out ( chany_top_out[16] ) , .p0 ( optlc_net_150 ) ) ; + .out ( chany_top_out[16] ) , .p0 ( optlc_net_155 ) ) ; sb_1__0__mux_tree_tapbuf_size2_3 mux_top_track_34 ( .in ( { chanx_left_out[28] , chanx_right_out[28] } ) , .sram ( mux_tree_tapbuf_size2_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_92 , SYNOPSYS_UNCONNECTED_93 } ) , - .out ( chany_top_out[17] ) , .p0 ( optlc_net_149 ) ) ; + .out ( chany_top_out[17] ) , .p0 ( optlc_net_156 ) ) ; sb_1__0__mux_tree_tapbuf_size2_4 mux_top_track_40 ( .in ( { top_left_grid_pin_46_[0] , chanx_left_in[29] } ) , .sram ( mux_tree_tapbuf_size2_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_94 , SYNOPSYS_UNCONNECTED_95 } ) , - .out ( chany_top_out[20] ) , .p0 ( optlc_net_149 ) ) ; + .out ( chany_top_out[20] ) , .p0 ( optlc_net_156 ) ) ; sb_1__0__mux_tree_tapbuf_size2_5 mux_top_track_42 ( .in ( { top_left_grid_pin_47_[0] , chanx_left_in[25] } ) , .sram ( mux_tree_tapbuf_size2_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_96 , SYNOPSYS_UNCONNECTED_97 } ) , - .out ( chany_top_out[21] ) , .p0 ( optlc_net_149 ) ) ; + .out ( chany_top_out[21] ) , .p0 ( optlc_net_156 ) ) ; sb_1__0__mux_tree_tapbuf_size2_6 mux_top_track_44 ( .in ( { top_left_grid_pin_48_[0] , chanx_left_in[21] } ) , .sram ( mux_tree_tapbuf_size2_6_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_98 , SYNOPSYS_UNCONNECTED_99 } ) , - .out ( chany_top_out[22] ) , .p0 ( optlc_net_149 ) ) ; + .out ( chany_top_out[22] ) , .p0 ( optlc_net_156 ) ) ; sb_1__0__mux_tree_tapbuf_size2_7 mux_top_track_46 ( .in ( { top_left_grid_pin_49_[0] , chanx_left_in[17] } ) , .sram ( mux_tree_tapbuf_size2_7_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_100 , SYNOPSYS_UNCONNECTED_101 } ) , - .out ( chany_top_out[23] ) , .p0 ( optlc_net_149 ) ) ; + .out ( chany_top_out[23] ) , .p0 ( optlc_net_156 ) ) ; sb_1__0__mux_tree_tapbuf_size2_8 mux_top_track_48 ( .in ( { top_left_grid_pin_50_[0] , chanx_left_in[13] } ) , .sram ( mux_tree_tapbuf_size2_8_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_102 , SYNOPSYS_UNCONNECTED_103 } ) , - .out ( chany_top_out[24] ) , .p0 ( optlc_net_149 ) ) ; + .out ( chany_top_out[24] ) , .p0 ( optlc_net_156 ) ) ; sb_1__0__mux_tree_tapbuf_size2_9 mux_top_track_50 ( .in ( { top_left_grid_pin_51_[0] , chanx_left_in[9] } ) , .sram ( mux_tree_tapbuf_size2_9_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_104 , SYNOPSYS_UNCONNECTED_105 } ) , - .out ( chany_top_out[25] ) , .p0 ( optlc_net_149 ) ) ; + .out ( chany_top_out[25] ) , .p0 ( optlc_net_155 ) ) ; sb_1__0__mux_tree_tapbuf_size2 mux_top_track_58 ( .in ( { chanx_right_in[0] , chanx_left_in[1] } ) , .sram ( mux_tree_tapbuf_size2_10_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_106 , SYNOPSYS_UNCONNECTED_107 } ) , - .out ( chany_top_out[29] ) , .p0 ( optlc_net_150 ) ) ; + .out ( chany_top_out[29] ) , .p0 ( optlc_net_154 ) ) ; sb_1__0__mux_tree_tapbuf_size2_mem_0 mem_top_track_28 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) , @@ -29344,7 +29329,7 @@ sb_1__0__mux_tree_tapbuf_size8_0 mux_right_track_2 ( .sram ( mux_tree_tapbuf_size8_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_108 , SYNOPSYS_UNCONNECTED_109 , SYNOPSYS_UNCONNECTED_110 , SYNOPSYS_UNCONNECTED_111 } ) , - .out ( chanx_right_out[1] ) , .p0 ( optlc_net_147 ) ) ; + .out ( chanx_right_out[1] ) , .p0 ( optlc_net_150 ) ) ; sb_1__0__mux_tree_tapbuf_size8_1 mux_right_track_4 ( .in ( { chany_top_in[1] , chany_top_in[12] , chany_top_in[23] , right_bottom_grid_pin_5_[0] , right_bottom_grid_pin_11_[0] , @@ -29353,7 +29338,7 @@ sb_1__0__mux_tree_tapbuf_size8_1 mux_right_track_4 ( .sram ( mux_tree_tapbuf_size8_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_112 , SYNOPSYS_UNCONNECTED_113 , SYNOPSYS_UNCONNECTED_114 , SYNOPSYS_UNCONNECTED_115 } ) , - .out ( chanx_right_out[2] ) , .p0 ( optlc_net_147 ) ) ; + .out ( chanx_right_out[2] ) , .p0 ( optlc_net_150 ) ) ; sb_1__0__mux_tree_tapbuf_size8 mux_left_track_1 ( .in ( { chany_top_in[0] , chany_top_in[11] , chany_top_in[22] , chanx_left_out[4] , chanx_left_out[20] , left_bottom_grid_pin_1_[0] , @@ -29361,7 +29346,7 @@ sb_1__0__mux_tree_tapbuf_size8 mux_left_track_1 ( .sram ( mux_tree_tapbuf_size8_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_116 , SYNOPSYS_UNCONNECTED_117 , SYNOPSYS_UNCONNECTED_118 , SYNOPSYS_UNCONNECTED_119 } ) , - .out ( chanx_left_out[0] ) , .p0 ( optlc_net_148 ) ) ; + .out ( chanx_left_out[0] ) , .p0 ( optlc_net_151 ) ) ; sb_1__0__mux_tree_tapbuf_size8_mem_0 mem_right_track_2 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) , @@ -29386,7 +29371,7 @@ sb_1__0__mux_tree_tapbuf_size10 mux_right_track_6 ( .sram ( mux_tree_tapbuf_size10_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_120 , SYNOPSYS_UNCONNECTED_121 , SYNOPSYS_UNCONNECTED_122 , SYNOPSYS_UNCONNECTED_123 } ) , - .out ( chanx_right_out[3] ) , .p0 ( optlc_net_151 ) ) ; + .out ( chanx_right_out[3] ) , .p0 ( optlc_net_153 ) ) ; sb_1__0__mux_tree_tapbuf_size10_mem mem_right_track_6 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) , @@ -29400,7 +29385,7 @@ sb_1__0__mux_tree_tapbuf_size9_0 mux_right_track_10 ( .sram ( mux_tree_tapbuf_size9_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_124 , SYNOPSYS_UNCONNECTED_125 , SYNOPSYS_UNCONNECTED_126 , SYNOPSYS_UNCONNECTED_127 } ) , - .out ( chanx_right_out[5] ) , .p0 ( optlc_net_151 ) ) ; + .out ( chanx_right_out[5] ) , .p0 ( optlc_net_153 ) ) ; sb_1__0__mux_tree_tapbuf_size9_1 mux_left_track_7 ( .in ( { chany_top_in[8] , chany_top_in[19] , chanx_left_out[9] , chanx_left_out[24] , left_bottom_grid_pin_1_[0] , @@ -29409,7 +29394,7 @@ sb_1__0__mux_tree_tapbuf_size9_1 mux_left_track_7 ( .sram ( mux_tree_tapbuf_size9_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_128 , SYNOPSYS_UNCONNECTED_129 , SYNOPSYS_UNCONNECTED_130 , SYNOPSYS_UNCONNECTED_131 } ) , - .out ( chanx_left_out[3] ) , .p0 ( optlc_net_148 ) ) ; + .out ( chanx_left_out[3] ) , .p0 ( optlc_net_151 ) ) ; sb_1__0__mux_tree_tapbuf_size9 mux_left_track_11 ( .in ( { chany_top_in[7] , chany_top_in[18] , chany_top_in[29] , chanx_left_out[11] , chanx_left_out[25] , left_bottom_grid_pin_3_[0] , @@ -29418,7 +29403,7 @@ sb_1__0__mux_tree_tapbuf_size9 mux_left_track_11 ( .sram ( mux_tree_tapbuf_size9_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_132 , SYNOPSYS_UNCONNECTED_133 , SYNOPSYS_UNCONNECTED_134 , SYNOPSYS_UNCONNECTED_135 } ) , - .out ( chanx_left_out[5] ) , .p0 ( optlc_net_148 ) ) ; + .out ( chanx_left_out[5] ) , .p0 ( optlc_net_149 ) ) ; sb_1__0__mux_tree_tapbuf_size9_mem_0 mem_right_track_10 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) , @@ -29434,8 +29419,8 @@ sb_1__0__mux_tree_tapbuf_size9_mem mem_left_track_11 ( .pReset ( pReset ) , .ccff_head ( mux_tree_tapbuf_size9_mem_1_ccff_tail ) , .ccff_tail ( mux_tree_tapbuf_size9_mem_2_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size9_2_sram ) ) ; -sky130_fd_sc_hd__conb_1 optlc_148 ( .LO ( SYNOPSYS_UNCONNECTED_136 ) , - .HI ( optlc_net_146 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_151 ( .LO ( SYNOPSYS_UNCONNECTED_136 ) , + .HI ( optlc_net_149 ) ) ; sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_E_in ) , .X ( pReset[0] ) ) ; sky130_fd_sc_hd__buf_1 pReset_N_FTB01 ( .A ( pReset_E_in ) , .X ( aps_rename_505_ ) ) ; @@ -29443,8 +29428,8 @@ sky130_fd_sc_hd__bufbuf_16 pReset_W_FTB01 ( .A ( pReset_E_in ) , .X ( pReset_W_out ) ) ; sky130_fd_sc_hd__bufbuf_16 pReset_E_FTB01 ( .A ( pReset_E_in ) , .X ( pReset_E_out ) ) ; -sky130_fd_sc_hd__conb_1 optlc_150 ( .LO ( SYNOPSYS_UNCONNECTED_137 ) , - .HI ( optlc_net_147 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_153 ( .LO ( SYNOPSYS_UNCONNECTED_137 ) , + .HI ( optlc_net_150 ) ) ; sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_N_in ) , .X ( prog_clk[0] ) ) ; sky130_fd_sc_hd__buf_1 prog_clk_3_N_FTB01 ( .A ( prog_clk_3_S_in ) , @@ -29453,7 +29438,7 @@ sky130_fd_sc_hd__buf_1 clk_3_N_FTB01 ( .A ( clk_3_S_in ) , .X ( aps_rename_507_ ) ) ; sky130_fd_sc_hd__buf_8 FTB_49__48 ( .A ( top_left_grid_pin_45_[0] ) , .X ( chany_top_out[19] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_50__49 ( .A ( chanx_right_in[3] ) , +sky130_fd_sc_hd__buf_12 FTB_50__49 ( .A ( chanx_right_in[3] ) , .X ( chanx_left_out[4] ) ) ; sky130_fd_sc_hd__buf_8 FTB_51__50 ( .A ( chanx_right_in[6] ) , .X ( chanx_left_out[7] ) ) ; @@ -29535,31 +29520,35 @@ sky130_fd_sc_hd__buf_8 FTB_89__88 ( .A ( chanx_left_in[27] ) , .X ( chanx_right_out[28] ) ) ; sky130_fd_sc_hd__buf_8 FTB_90__89 ( .A ( chanx_left_in[28] ) , .X ( chanx_right_out[29] ) ) ; -sky130_fd_sc_hd__buf_6 FTB_91__90 ( .A ( SC_IN_TOP ) , .X ( ropt_net_170 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_132 ( .A ( BUF_net_133 ) , +sky130_fd_sc_hd__buf_6 FTB_91__90 ( .A ( SC_IN_TOP ) , .X ( ropt_net_176 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_137 ( .A ( BUF_net_138 ) , .Y ( Test_en_N_out ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_133 ( .A ( Test_en_S_in ) , .Y ( BUF_net_133 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_134 ( .A ( BUF_net_135 ) , .Y ( pReset_N_out ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_135 ( .A ( aps_rename_505_ ) , - .Y ( BUF_net_135 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_136 ( .A ( BUF_net_137 ) , .Y ( Reset_N_out ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_137 ( .A ( Reset_S_in ) , .Y ( BUF_net_137 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_138 ( .A ( BUF_net_139 ) , +sky130_fd_sc_hd__inv_1 BINV_R_138 ( .A ( Test_en_S_in ) , .Y ( BUF_net_138 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_139 ( .A ( BUF_net_140 ) , .Y ( pReset_N_out ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_140 ( .A ( aps_rename_505_ ) , + .Y ( BUF_net_140 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_141 ( .A ( BUF_net_142 ) , .Y ( Reset_N_out ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_142 ( .A ( Reset_S_in ) , .Y ( BUF_net_142 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_143 ( .A ( BUF_net_144 ) , .Y ( prog_clk_3_N_out ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_139 ( .A ( aps_rename_506_ ) , - .Y ( BUF_net_139 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_140 ( .A ( BUF_net_141 ) , .Y ( clk_3_N_out ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_141 ( .A ( aps_rename_507_ ) , - .Y ( BUF_net_141 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_152 ( .LO ( SYNOPSYS_UNCONNECTED_138 ) , - .HI ( optlc_net_148 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_154 ( .LO ( SYNOPSYS_UNCONNECTED_139 ) , - .HI ( optlc_net_149 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_156 ( .LO ( SYNOPSYS_UNCONNECTED_140 ) , - .HI ( optlc_net_150 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_158 ( .LO ( SYNOPSYS_UNCONNECTED_141 ) , +sky130_fd_sc_hd__inv_1 BINV_R_144 ( .A ( aps_rename_506_ ) , + .Y ( BUF_net_144 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_145 ( .A ( BUF_net_146 ) , .Y ( clk_3_N_out ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_146 ( .A ( aps_rename_507_ ) , + .Y ( BUF_net_146 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_155 ( .LO ( SYNOPSYS_UNCONNECTED_138 ) , .HI ( optlc_net_151 ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1347 ( .A ( ropt_net_170 ) , +sky130_fd_sc_hd__conb_1 optlc_157 ( .LO ( SYNOPSYS_UNCONNECTED_139 ) , + .HI ( optlc_net_152 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_162 ( .LO ( SYNOPSYS_UNCONNECTED_140 ) , + .HI ( optlc_net_153 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_164 ( .LO ( SYNOPSYS_UNCONNECTED_141 ) , + .HI ( optlc_net_154 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_166 ( .LO ( SYNOPSYS_UNCONNECTED_142 ) , + .HI ( optlc_net_155 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_168 ( .LO ( SYNOPSYS_UNCONNECTED_143 ) , + .HI ( optlc_net_156 ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1359 ( .A ( ropt_net_176 ) , .X ( SC_OUT_TOP ) ) ; endmodule @@ -29652,18 +29641,18 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -wire copt_net_102 ; +wire copt_net_103 ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( copt_net_102 ) ) ; + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( copt_net_103 ) ) ; sky130_fd_sc_hd__buf_6 FTB_33__32 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1267 ( .A ( copt_net_102 ) , - .X ( copt_net_101 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1269 ( .A ( copt_net_101 ) , - .X ( copt_net_103 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1270 ( .A ( copt_net_103 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1265 ( .A ( copt_net_103 ) , + .X ( copt_net_99 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1266 ( .A ( copt_net_99 ) , + .X ( copt_net_100 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1267 ( .A ( copt_net_100 ) , .X ( mem_out[1] ) ) ; endmodule @@ -30094,13 +30083,13 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_84 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) ) ; endmodule @@ -30175,13 +30164,14 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_79 ( .A ( BUF_net_80 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_80 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_80 ) ) ; endmodule @@ -30215,14 +30205,13 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_79 ( .A ( BUF_net_80 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_80 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_80 ) ) ; endmodule @@ -30301,9 +30290,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_77 ( .A ( BUF_net_78 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_78 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_78 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_86 ( .A ( BUF_net_87 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_87 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_87 ) ) ; endmodule @@ -30322,7 +30311,7 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_76 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_78 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -30359,12 +30348,11 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_88 ( .A ( BUF_net_89 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_89 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_89 ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_77 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) ) ; endmodule @@ -30383,9 +30371,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_74 ( .A ( BUF_net_75 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_75 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_75 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_75 ( .A ( BUF_net_76 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_76 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_76 ) ) ; endmodule @@ -30404,9 +30392,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_72 ( .A ( BUF_net_73 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_73 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_73 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_73 ( .A ( BUF_net_74 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_74 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_74 ) ) ; endmodule @@ -30420,14 +30408,13 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_86 ( .A ( BUF_net_87 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_87 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_87 ) ) ; endmodule @@ -30441,13 +30428,13 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_71 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .X ( out[0] ) ) ; endmodule @@ -30501,14 +30488,13 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_84 ( .A ( BUF_net_85 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_85 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_85 ) ) ; endmodule @@ -30527,9 +30513,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_69 ( .A ( BUF_net_70 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_70 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_70 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_71 ( .A ( BUF_net_72 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_72 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_72 ) ) ; endmodule @@ -30548,8 +30534,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_68 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .X ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_69 ( .A ( BUF_net_70 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_70 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_70 ) ) ; endmodule @@ -30603,13 +30590,13 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_67 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .X ( out[0] ) ) ; endmodule @@ -30628,9 +30615,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_65 ( .A ( BUF_net_66 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_66 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_66 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_67 ( .A ( BUF_net_68 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_68 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_68 ) ) ; endmodule @@ -30732,33 +30719,31 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_181 ) , +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_190 ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1258 ( .A ( copt_net_94 ) , + .X ( copt_net_92 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1259 ( .A ( copt_net_92 ) , + .X ( copt_net_93 ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1260 ( .A ( copt_net_96 ) , .X ( copt_net_94 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1261 ( .A ( copt_net_94 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1261 ( .A ( ccff_head[0] ) , .X ( copt_net_95 ) ) ; -sky130_fd_sc_hd__dlygate4sd2_1 copt_h_inst_1262 ( .A ( copt_net_97 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1262 ( .A ( copt_net_95 ) , .X ( copt_net_96 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1263 ( .A ( copt_net_98 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1263 ( .A ( copt_net_93 ) , .X ( copt_net_97 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1264 ( .A ( copt_net_99 ) , - .X ( copt_net_98 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1265 ( .A ( ccff_head[0] ) , - .X ( copt_net_99 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1343 ( .A ( copt_net_95 ) , - .X ( ropt_net_178 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1344 ( .A ( ropt_net_178 ) , - .X ( ropt_net_179 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1345 ( .A ( ropt_net_179 ) , - .X ( ropt_net_180 ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 ropt_h_inst_1346 ( .A ( ropt_net_180 ) , - .X ( ropt_net_181 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1351 ( .A ( copt_net_97 ) , + .X ( ropt_net_188 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1352 ( .A ( ropt_net_188 ) , + .X ( ropt_net_189 ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 ropt_h_inst_1353 ( .A ( ropt_net_189 ) , + .X ( ropt_net_190 ) ) ; endmodule @@ -30774,6 +30759,35 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , + .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_65 ( .A ( BUF_net_66 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_66 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_66 ) ) ; +endmodule + + +module sb_0__2__mux_tree_tapbuf_size4_4 ( in , sram , sram_inv , out , p0 ) ; +input [0:3] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; + sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , @@ -30791,35 +30805,6 @@ sky130_fd_sc_hd__inv_1 BINV_R_64 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , endmodule -module sb_0__2__mux_tree_tapbuf_size4_4 ( in , sram , sram_inv , out , p0 ) ; -input [0:3] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , - .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_61 ( .A ( BUF_net_62 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_62 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .Y ( BUF_net_62 ) ) ; -endmodule - - module sb_0__2__mux_tree_tapbuf_size4_3 ( in , sram , sram_inv , out , p0 ) ; input [0:3] in ; input [0:2] sram ; @@ -30832,8 +30817,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , @@ -30845,6 +30828,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_61 ( .A ( BUF_net_62 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_62 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_62 ) ) ; endmodule @@ -30964,10 +30950,9 @@ output pReset_S_out ; input prog_clk_0_E_in ; wire ropt_net_129 ; -wire ropt_net_127 ; -wire ropt_net_137 ; +wire ropt_net_130 ; +wire ropt_net_131 ; wire ropt_net_128 ; -wire ropt_net_134 ; wire [0:0] prog_clk ; wire prog_clk_0 ; wire [0:1] mux_tree_tapbuf_size2_0_sram ; @@ -31055,7 +31040,7 @@ sb_0__2__mux_tree_tapbuf_size4_1 mux_right_track_2 ( .sram ( mux_tree_tapbuf_size4_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 } ) , - .out ( chanx_right_out[1] ) , .p0 ( optlc_net_92 ) ) ; + .out ( chanx_right_out[1] ) , .p0 ( optlc_net_90 ) ) ; sb_0__2__mux_tree_tapbuf_size4_2 mux_right_track_4 ( .in ( { right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_40_[0] , right_bottom_grid_pin_43_[0] , chany_bottom_in[26] } ) , @@ -31069,7 +31054,7 @@ sb_0__2__mux_tree_tapbuf_size4_3 mux_right_track_6 ( .sram ( mux_tree_tapbuf_size4_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , - .out ( chanx_right_out[3] ) , .p0 ( optlc_net_92 ) ) ; + .out ( chanx_right_out[3] ) , .p0 ( optlc_net_90 ) ) ; sb_0__2__mux_tree_tapbuf_size4_4 mux_right_track_8 ( .in ( { right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_39_[0] , right_bottom_grid_pin_42_[0] , chany_bottom_in[24] } ) , @@ -31117,77 +31102,77 @@ sb_0__2__mux_tree_tapbuf_size2_0 mux_right_track_12 ( .in ( { right_top_grid_pin_1_[0] , chany_bottom_in[22] } ) , .sram ( mux_tree_tapbuf_size2_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) , - .out ( chanx_right_out[6] ) , .p0 ( optlc_net_90 ) ) ; + .out ( chanx_right_out[6] ) , .p0 ( optlc_net_91 ) ) ; sb_0__2__mux_tree_tapbuf_size2_1 mux_right_track_14 ( .in ( { right_bottom_grid_pin_36_[0] , chany_bottom_in[21] } ) , .sram ( mux_tree_tapbuf_size2_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 } ) , - .out ( chanx_right_out[7] ) , .p0 ( optlc_net_93 ) ) ; + .out ( chanx_right_out[7] ) , .p0 ( optlc_net_88 ) ) ; sb_0__2__mux_tree_tapbuf_size2_2 mux_right_track_16 ( .in ( { right_bottom_grid_pin_37_[0] , chany_bottom_in[20] } ) , .sram ( mux_tree_tapbuf_size2_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) , - .out ( chanx_right_out[8] ) , .p0 ( optlc_net_93 ) ) ; + .out ( chanx_right_out[8] ) , .p0 ( optlc_net_88 ) ) ; sb_0__2__mux_tree_tapbuf_size2_3 mux_right_track_18 ( .in ( { right_bottom_grid_pin_38_[0] , chany_bottom_in[19] } ) , .sram ( mux_tree_tapbuf_size2_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 } ) , - .out ( chanx_right_out[9] ) , .p0 ( optlc_net_91 ) ) ; + .out ( chanx_right_out[9] ) , .p0 ( optlc_net_89 ) ) ; sb_0__2__mux_tree_tapbuf_size2_4 mux_right_track_20 ( .in ( { right_bottom_grid_pin_39_[0] , chany_bottom_in[18] } ) , .sram ( mux_tree_tapbuf_size2_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) , - .out ( chanx_right_out[10] ) , .p0 ( optlc_net_93 ) ) ; + .out ( chanx_right_out[10] ) , .p0 ( optlc_net_88 ) ) ; sb_0__2__mux_tree_tapbuf_size2_5 mux_right_track_22 ( .in ( { right_bottom_grid_pin_40_[0] , chany_bottom_in[17] } ) , .sram ( mux_tree_tapbuf_size2_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 } ) , - .out ( chanx_right_out[11] ) , .p0 ( optlc_net_93 ) ) ; + .out ( chanx_right_out[11] ) , .p0 ( optlc_net_88 ) ) ; sb_0__2__mux_tree_tapbuf_size2_6 mux_right_track_24 ( .in ( { right_bottom_grid_pin_41_[0] , chany_bottom_in[16] } ) , .sram ( mux_tree_tapbuf_size2_6_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) , - .out ( chanx_right_out[12] ) , .p0 ( optlc_net_93 ) ) ; + .out ( chanx_right_out[12] ) , .p0 ( optlc_net_88 ) ) ; sb_0__2__mux_tree_tapbuf_size2_7 mux_right_track_26 ( .in ( { right_bottom_grid_pin_42_[0] , chany_bottom_in[15] } ) , .sram ( mux_tree_tapbuf_size2_7_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 } ) , - .out ( chanx_right_out[13] ) , .p0 ( optlc_net_93 ) ) ; + .out ( chanx_right_out[13] ) , .p0 ( optlc_net_88 ) ) ; sb_0__2__mux_tree_tapbuf_size2_8 mux_right_track_30 ( .in ( { right_bottom_grid_pin_36_[0] , chany_bottom_in[13] } ) , .sram ( mux_tree_tapbuf_size2_8_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) , - .out ( chanx_right_out[15] ) , .p0 ( optlc_net_90 ) ) ; + .out ( chanx_right_out[15] ) , .p0 ( optlc_net_88 ) ) ; sb_0__2__mux_tree_tapbuf_size2_9 mux_right_track_32 ( .in ( { right_bottom_grid_pin_37_[0] , chany_bottom_in[12] } ) , .sram ( mux_tree_tapbuf_size2_9_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 } ) , - .out ( chanx_right_out[16] ) , .p0 ( optlc_net_93 ) ) ; + .out ( chanx_right_out[16] ) , .p0 ( optlc_net_89 ) ) ; sb_0__2__mux_tree_tapbuf_size2_10 mux_right_track_34 ( .in ( { right_bottom_grid_pin_38_[0] , chany_bottom_in[11] } ) , .sram ( mux_tree_tapbuf_size2_10_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) , - .out ( chanx_right_out[17] ) , .p0 ( optlc_net_91 ) ) ; + .out ( chanx_right_out[17] ) , .p0 ( optlc_net_89 ) ) ; sb_0__2__mux_tree_tapbuf_size2_11 mux_right_track_36 ( .in ( { right_bottom_grid_pin_39_[0] , chany_bottom_in[10] } ) , .sram ( mux_tree_tapbuf_size2_11_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 } ) , - .out ( chanx_right_out[18] ) , .p0 ( optlc_net_93 ) ) ; + .out ( chanx_right_out[18] ) , .p0 ( optlc_net_88 ) ) ; sb_0__2__mux_tree_tapbuf_size2_12 mux_right_track_38 ( .in ( { right_bottom_grid_pin_40_[0] , chany_bottom_in[9] } ) , .sram ( mux_tree_tapbuf_size2_12_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) , - .out ( chanx_right_out[19] ) , .p0 ( optlc_net_93 ) ) ; + .out ( chanx_right_out[19] ) , .p0 ( optlc_net_88 ) ) ; sb_0__2__mux_tree_tapbuf_size2_13 mux_right_track_40 ( .in ( { right_bottom_grid_pin_41_[0] , chany_bottom_in[8] } ) , .sram ( mux_tree_tapbuf_size2_13_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 } ) , - .out ( chanx_right_out[20] ) , .p0 ( optlc_net_93 ) ) ; + .out ( chanx_right_out[20] ) , .p0 ( optlc_net_88 ) ) ; sb_0__2__mux_tree_tapbuf_size2_14 mux_right_track_42 ( .in ( { right_bottom_grid_pin_42_[0] , chany_bottom_in[7] } ) , .sram ( mux_tree_tapbuf_size2_14_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) , - .out ( chanx_right_out[21] ) , .p0 ( optlc_net_90 ) ) ; + .out ( chanx_right_out[21] ) , .p0 ( optlc_net_88 ) ) ; sb_0__2__mux_tree_tapbuf_size2_15 mux_right_track_44 ( .in ( { right_top_grid_pin_1_[0] , chany_bottom_in[6] } ) , .sram ( mux_tree_tapbuf_size2_15_sram ) , @@ -31202,27 +31187,27 @@ sb_0__2__mux_tree_tapbuf_size2_17 mux_right_track_48 ( .in ( { right_bottom_grid_pin_37_[0] , chany_bottom_in[4] } ) , .sram ( mux_tree_tapbuf_size2_17_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 } ) , - .out ( chanx_right_out[24] ) , .p0 ( optlc_net_92 ) ) ; + .out ( chanx_right_out[24] ) , .p0 ( optlc_net_90 ) ) ; sb_0__2__mux_tree_tapbuf_size2_18 mux_right_track_50 ( .in ( { right_bottom_grid_pin_38_[0] , chany_bottom_in[3] } ) , .sram ( mux_tree_tapbuf_size2_18_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) , - .out ( chanx_right_out[25] ) , .p0 ( optlc_net_92 ) ) ; + .out ( chanx_right_out[25] ) , .p0 ( optlc_net_90 ) ) ; sb_0__2__mux_tree_tapbuf_size2_19 mux_right_track_54 ( .in ( { right_bottom_grid_pin_40_[0] , chany_bottom_in[1] } ) , .sram ( mux_tree_tapbuf_size2_19_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 } ) , - .out ( chanx_right_out[27] ) , .p0 ( optlc_net_92 ) ) ; + .out ( chanx_right_out[27] ) , .p0 ( optlc_net_90 ) ) ; sb_0__2__mux_tree_tapbuf_size2_20 mux_right_track_56 ( .in ( { right_bottom_grid_pin_41_[0] , chany_bottom_in[0] } ) , .sram ( mux_tree_tapbuf_size2_20_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) , - .out ( chanx_right_out[28] ) , .p0 ( optlc_net_93 ) ) ; + .out ( chanx_right_out[28] ) , .p0 ( optlc_net_88 ) ) ; sb_0__2__mux_tree_tapbuf_size2_21 mux_right_track_58 ( .in ( { right_bottom_grid_pin_42_[0] , chany_bottom_in[29] } ) , .sram ( mux_tree_tapbuf_size2_21_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 } ) , - .out ( chanx_right_out[29] ) , .p0 ( optlc_net_93 ) ) ; + .out ( chanx_right_out[29] ) , .p0 ( optlc_net_88 ) ) ; sb_0__2__mux_tree_tapbuf_size2_22 mux_bottom_track_1 ( .in ( { chanx_right_in[28] , bottom_left_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size2_22_sram ) , @@ -31237,17 +31222,17 @@ sb_0__2__mux_tree_tapbuf_size2_24 mux_bottom_track_13 ( .in ( { chanx_right_in[22] , bottom_left_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size2_24_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 } ) , - .out ( chany_bottom_out[6] ) , .p0 ( optlc_net_91 ) ) ; + .out ( chany_bottom_out[6] ) , .p0 ( optlc_net_89 ) ) ; sb_0__2__mux_tree_tapbuf_size2_25 mux_bottom_track_29 ( .in ( { chanx_right_in[14] , bottom_left_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size2_25_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_69 , SYNOPSYS_UNCONNECTED_70 } ) , - .out ( chany_bottom_out[14] ) , .p0 ( optlc_net_91 ) ) ; + .out ( chany_bottom_out[14] ) , .p0 ( optlc_net_89 ) ) ; sb_0__2__mux_tree_tapbuf_size2 mux_bottom_track_45 ( .in ( { chanx_right_in[6] , bottom_left_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size2_26_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_71 , SYNOPSYS_UNCONNECTED_72 } ) , - .out ( chany_bottom_out[22] ) , .p0 ( optlc_net_91 ) ) ; + .out ( chany_bottom_out[22] ) , .p0 ( optlc_net_89 ) ) ; sb_0__2__mux_tree_tapbuf_size2_mem_0 mem_right_track_12 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) , @@ -31393,7 +31378,7 @@ sb_0__2__mux_tree_tapbuf_size3 mux_right_track_52 ( chany_bottom_in[2] } ) , .sram ( mux_tree_tapbuf_size3_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_75 , SYNOPSYS_UNCONNECTED_76 } ) , - .out ( chanx_right_out[26] ) , .p0 ( optlc_net_92 ) ) ; + .out ( chanx_right_out[26] ) , .p0 ( optlc_net_90 ) ) ; sb_0__2__mux_tree_tapbuf_size3_mem_0 mem_right_track_28 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) , @@ -31405,8 +31390,8 @@ sb_0__2__mux_tree_tapbuf_size3_mem mem_right_track_52 ( .pReset ( pReset ) , .ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_1_sram ) ) ; sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_E_in ) , .X ( pReset[0] ) ) ; -sky130_fd_sc_hd__buf_6 pReset_S_FTB01 ( .A ( pReset_E_in ) , - .X ( pReset_S_out ) ) ; +sky130_fd_sc_hd__conb_1 optlc_90 ( .LO ( SYNOPSYS_UNCONNECTED_77 ) , + .HI ( optlc_net_88 ) ) ; sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_E_in ) , .X ( prog_clk[0] ) ) ; sky130_fd_sc_hd__buf_8 FTB_36__35 ( .A ( chanx_right_in[0] ) , @@ -31415,33 +31400,33 @@ sky130_fd_sc_hd__buf_8 FTB_37__36 ( .A ( chanx_right_in[1] ) , .X ( chany_bottom_out[27] ) ) ; sky130_fd_sc_hd__buf_8 FTB_38__37 ( .A ( chanx_right_in[2] ) , .X ( chany_bottom_out[26] ) ) ; -sky130_fd_sc_hd__buf_6 FTB_39__38 ( .A ( chanx_right_in[3] ) , - .X ( ropt_net_129 ) ) ; +sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chanx_right_in[3] ) , + .X ( chany_bottom_out[25] ) ) ; sky130_fd_sc_hd__buf_6 FTB_40__39 ( .A ( chanx_right_in[4] ) , - .X ( ropt_net_127 ) ) ; + .X ( ropt_net_129 ) ) ; sky130_fd_sc_hd__buf_8 FTB_41__40 ( .A ( chanx_right_in[5] ) , .X ( chany_bottom_out[23] ) ) ; sky130_fd_sc_hd__buf_8 FTB_42__41 ( .A ( chanx_right_in[7] ) , .X ( chany_bottom_out[21] ) ) ; -sky130_fd_sc_hd__buf_6 FTB_43__42 ( .A ( chanx_right_in[8] ) , - .X ( ropt_net_137 ) ) ; +sky130_fd_sc_hd__buf_8 FTB_43__42 ( .A ( chanx_right_in[8] ) , + .X ( chany_bottom_out[20] ) ) ; sky130_fd_sc_hd__buf_8 FTB_44__43 ( .A ( chanx_right_in[9] ) , .X ( chany_bottom_out[19] ) ) ; sky130_fd_sc_hd__buf_8 FTB_45__44 ( .A ( chanx_right_in[10] ) , .X ( chany_bottom_out[18] ) ) ; -sky130_fd_sc_hd__buf_6 FTB_46__45 ( .A ( chanx_right_in[11] ) , - .X ( ropt_net_128 ) ) ; -sky130_fd_sc_hd__buf_8 FTB_47__46 ( .A ( chanx_right_in[12] ) , - .X ( chany_bottom_out[16] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_46__45 ( .A ( chanx_right_in[11] ) , + .X ( chany_bottom_out[17] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_47__46 ( .A ( chanx_right_in[12] ) , + .X ( ropt_net_130 ) ) ; sky130_fd_sc_hd__buf_8 FTB_48__47 ( .A ( chanx_right_in[13] ) , .X ( chany_bottom_out[15] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_49__48 ( .A ( chanx_right_in[15] ) , - .X ( chany_bottom_out[13] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_49__48 ( .A ( chanx_right_in[15] ) , + .X ( ropt_net_131 ) ) ; sky130_fd_sc_hd__buf_8 FTB_50__49 ( .A ( chanx_right_in[16] ) , .X ( chany_bottom_out[12] ) ) ; sky130_fd_sc_hd__buf_8 FTB_51__50 ( .A ( chanx_right_in[17] ) , .X ( chany_bottom_out[11] ) ) ; -sky130_fd_sc_hd__buf_6 FTB_52__51 ( .A ( chanx_right_in[18] ) , +sky130_fd_sc_hd__buf_8 FTB_52__51 ( .A ( chanx_right_in[18] ) , .X ( chany_bottom_out[10] ) ) ; sky130_fd_sc_hd__buf_8 FTB_53__52 ( .A ( chanx_right_in[19] ) , .X ( chany_bottom_out[9] ) ) ; @@ -31452,7 +31437,7 @@ sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chanx_right_in[21] ) , sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chanx_right_in[23] ) , .X ( chany_bottom_out[5] ) ) ; sky130_fd_sc_hd__buf_6 FTB_57__56 ( .A ( chanx_right_in[24] ) , - .X ( ropt_net_134 ) ) ; + .X ( ropt_net_128 ) ) ; sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chanx_right_in[26] ) , .X ( chany_bottom_out[2] ) ) ; sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( chanx_right_in[27] ) , @@ -31460,24 +31445,21 @@ sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( chanx_right_in[27] ) , sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( chanx_right_in[29] ) , .X ( chany_bottom_out[29] ) ) ; sky130_fd_sc_hd__buf_6 FTB_61__60 ( .A ( SC_IN_TOP ) , .X ( SC_OUT_BOT ) ) ; -sky130_fd_sc_hd__conb_1 optlc_92 ( .LO ( SYNOPSYS_UNCONNECTED_77 ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_85 ( .A ( pReset_E_in ) , .X ( pReset_S_out ) ) ; +sky130_fd_sc_hd__conb_1 optlc_92 ( .LO ( SYNOPSYS_UNCONNECTED_78 ) , + .HI ( optlc_net_89 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_94 ( .LO ( SYNOPSYS_UNCONNECTED_79 ) , .HI ( optlc_net_90 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_94 ( .LO ( SYNOPSYS_UNCONNECTED_78 ) , +sky130_fd_sc_hd__conb_1 optlc_96 ( .LO ( SYNOPSYS_UNCONNECTED_80 ) , .HI ( optlc_net_91 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_96 ( .LO ( SYNOPSYS_UNCONNECTED_79 ) , - .HI ( optlc_net_92 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_98 ( .LO ( SYNOPSYS_UNCONNECTED_80 ) , - .HI ( optlc_net_93 ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1293 ( .A ( ropt_net_127 ) , - .X ( chany_bottom_out[24] ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1294 ( .A ( ropt_net_128 ) , - .X ( chany_bottom_out[17] ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1295 ( .A ( ropt_net_129 ) , - .X ( chany_bottom_out[25] ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1300 ( .A ( ropt_net_134 ) , +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1293 ( .A ( ropt_net_128 ) , .X ( chany_bottom_out[4] ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1303 ( .A ( ropt_net_137 ) , - .X ( chany_bottom_out[20] ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1294 ( .A ( ropt_net_129 ) , + .X ( chany_bottom_out[24] ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1295 ( .A ( ropt_net_130 ) , + .X ( chany_bottom_out[16] ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1296 ( .A ( ropt_net_131 ) , + .X ( chany_bottom_out[13] ) ) ; endmodule @@ -31624,9 +31606,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_147 ( .A ( BUF_net_148 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_148 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_148 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_141 ( .A ( BUF_net_142 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_142 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_142 ) ) ; endmodule @@ -31640,13 +31622,14 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_139 ( .A ( BUF_net_140 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_140 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_140 ) ) ; endmodule @@ -31660,13 +31643,14 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_137 ( .A ( BUF_net_138 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_138 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_138 ) ) ; endmodule @@ -31700,14 +31684,13 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_145 ( .A ( BUF_net_146 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_146 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_146 ) ) ; endmodule @@ -31721,13 +31704,13 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_144 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .X ( out[0] ) ) ; endmodule @@ -31741,13 +31724,13 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_143 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .X ( out[0] ) ) ; endmodule @@ -31766,9 +31749,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_141 ( .A ( BUF_net_142 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_142 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_142 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_135 ( .A ( BUF_net_136 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_136 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_136 ) ) ; endmodule @@ -31780,14 +31763,14 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -wire copt_net_164 ; +wire copt_net_160 ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , - .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( copt_net_164 ) ) ; -sky130_fd_sc_hd__buf_8 FTB_42__41 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1334 ( .A ( copt_net_164 ) , + .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( copt_net_160 ) ) ; +sky130_fd_sc_hd__buf_6 FTB_42__41 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1336 ( .A ( copt_net_160 ) , .X ( mem_out[1] ) ) ; endmodule @@ -31955,7 +31938,7 @@ sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_140 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_134 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -31975,12 +31958,13 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_139 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .X ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_132 ( .A ( BUF_net_133 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_133 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .Y ( BUF_net_133 ) ) ; endmodule @@ -32003,7 +31987,7 @@ sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_138 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_131 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -32019,129 +32003,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size3_5 ( in , sram , sram_inv , out , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_136 ( .A ( BUF_net_137 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_137 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .Y ( BUF_net_137 ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size3_4 ( in , sram , sram_inv , out , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_134 ( .A ( BUF_net_135 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_135 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .Y ( BUF_net_135 ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size3_3 ( in , sram , sram_inv , out , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_133 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .X ( out[0] ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size3_2 ( in , sram , sram_inv , out , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_131 ( .A ( BUF_net_132 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_132 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , - .Y ( BUF_net_132 ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size3_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:2] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; - sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , @@ -32156,7 +32017,31 @@ sky130_fd_sc_hd__inv_1 BINV_R_130 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , endmodule -module sb_0__1__mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , p0 ) ; +module sb_0__1__mux_tree_tapbuf_size3_5 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size3_4 ( in , sram , sram_inv , out , p0 ) ; input [0:2] in ; input [0:1] sram ; input [0:1] sram_inv ; @@ -32181,6 +32066,104 @@ sky130_fd_sc_hd__inv_1 BINV_R_128 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , endmodule +module sb_0__1__mux_tree_tapbuf_size3_3 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size3_2 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_125 ( .A ( BUF_net_126 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_126 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .Y ( BUF_net_126 ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size3_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +endmodule + + +module sb_0__1__mux_tree_tapbuf_size3_0 ( in , sram , sram_inv , out , p0 ) ; +input [0:2] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; + +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( p0 ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_123 ( .A ( BUF_net_124 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_124 ( .A ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , + .Y ( BUF_net_124 ) ) ; +endmodule + + module sb_0__1__mux_tree_tapbuf_size4_mem ( pReset , prog_clk , ccff_head , ccff_tail , mem_out ) ; input [0:0] pReset ; @@ -32409,6 +32392,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , @@ -32420,8 +32405,6 @@ sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_126 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .X ( out[0] ) ) ; endmodule @@ -32444,13 +32427,12 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( +sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_124 ( .A ( BUF_net_125 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_125 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .Y ( BUF_net_125 ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_122 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .X ( out[0] ) ) ; endmodule @@ -32473,12 +32455,13 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_123 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .X ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_120 ( .A ( BUF_net_121 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_121 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_121 ) ) ; endmodule @@ -32494,8 +32477,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , @@ -32503,10 +32484,13 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( in[3] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_118 ( .A ( BUF_net_119 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_119 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_119 ) ) ; endmodule @@ -32522,8 +32506,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , @@ -32535,6 +32517,8 @@ sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_117 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .X ( out[0] ) ) ; endmodule @@ -32561,9 +32545,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_121 ( .A ( BUF_net_122 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_122 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .Y ( BUF_net_122 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_115 ( .A ( BUF_net_116 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_116 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_116 ) ) ; endmodule @@ -32618,7 +32602,7 @@ sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_120 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_114 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -32646,9 +32630,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_118 ( .A ( BUF_net_119 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_119 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .Y ( BUF_net_119 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_112 ( .A ( BUF_net_113 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_113 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_113 ) ) ; endmodule @@ -32675,9 +32659,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_116 ( .A ( BUF_net_117 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_117 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .Y ( BUF_net_117 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_110 ( .A ( BUF_net_111 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_111 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_111 ) ) ; endmodule @@ -32704,9 +32688,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_114 ( .A ( BUF_net_115 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_115 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .Y ( BUF_net_115 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_108 ( .A ( BUF_net_109 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_109 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_109 ) ) ; endmodule @@ -32722,6 +32706,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( in[2] ) , @@ -32733,9 +32719,6 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_112 ( .A ( BUF_net_113 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_113 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .Y ( BUF_net_113 ) ) ; endmodule @@ -32982,9 +32965,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_110 ( .A ( BUF_net_111 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_111 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .Y ( BUF_net_111 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_106 ( .A ( BUF_net_107 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_107 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .Y ( BUF_net_107 ) ) ; endmodule @@ -33001,6 +32984,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -33015,8 +33000,6 @@ sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_109 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .X ( out[0] ) ) ; endmodule @@ -33047,9 +33030,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_107 ( .A ( BUF_net_108 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_108 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .Y ( BUF_net_108 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_104 ( .A ( BUF_net_105 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_105 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .Y ( BUF_net_105 ) ) ; endmodule @@ -33080,7 +33063,7 @@ sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_106 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_103 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -33144,9 +33127,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_104 ( .A ( BUF_net_105 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_105 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .Y ( BUF_net_105 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_101 ( .A ( BUF_net_102 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_102 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .Y ( BUF_net_102 ) ) ; endmodule @@ -33177,9 +33160,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_102 ( .A ( BUF_net_103 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_103 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .Y ( BUF_net_103 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_99 ( .A ( BUF_net_100 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_100 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .Y ( BUF_net_100 ) ) ; endmodule @@ -33242,9 +33225,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_100 ( .A ( BUF_net_101 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_101 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .Y ( BUF_net_101 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_97 ( .A ( BUF_net_98 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_98 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .Y ( BUF_net_98 ) ) ; endmodule @@ -33261,6 +33244,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -33275,9 +33260,6 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_98 ( .A ( BUF_net_99 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_99 ( .A ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .Y ( BUF_net_99 ) ) ; endmodule @@ -33479,35 +33461,39 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:2] mem_out ; -sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_181 ) , +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_168 ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ; sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[2] ) , .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1325 ( .A ( ccff_head[0] ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1326 ( .A ( ropt_net_172 ) , + .X ( copt_net_149 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1327 ( .A ( copt_net_149 ) , + .X ( copt_net_150 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1328 ( .A ( ropt_net_170 ) , + .X ( copt_net_151 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1329 ( .A ( copt_net_153 ) , + .X ( copt_net_152 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1330 ( .A ( copt_net_150 ) , .X ( copt_net_153 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1326 ( .A ( copt_net_153 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1331 ( .A ( ccff_head[0] ) , .X ( copt_net_154 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1327 ( .A ( copt_net_154 ) , - .X ( copt_net_155 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1328 ( .A ( copt_net_155 ) , - .X ( copt_net_156 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1329 ( .A ( copt_net_156 ) , - .X ( copt_net_157 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1330 ( .A ( copt_net_157 ) , - .X ( copt_net_158 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1347 ( .A ( copt_net_158 ) , - .X ( ropt_net_177 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1348 ( .A ( ropt_net_177 ) , - .X ( ropt_net_178 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1349 ( .A ( ropt_net_178 ) , - .X ( ropt_net_179 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1350 ( .A ( ropt_net_179 ) , - .X ( ropt_net_180 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1351 ( .A ( ropt_net_180 ) , - .X ( ropt_net_181 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1340 ( .A ( copt_net_151 ) , + .X ( ropt_net_166 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1341 ( .A ( ropt_net_166 ) , + .X ( ropt_net_167 ) ) ; +sky130_fd_sc_hd__buf_2 ropt_h_inst_1342 ( .A ( ropt_net_167 ) , + .X ( ropt_net_168 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1343 ( .A ( copt_net_152 ) , + .X ( ropt_net_169 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1344 ( .A ( ropt_net_171 ) , + .X ( ropt_net_170 ) ) ; +sky130_fd_sc_hd__buf_4 ropt_h_inst_1345 ( .A ( ropt_net_169 ) , + .X ( ropt_net_171 ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 ropt_h_inst_1346 ( .A ( copt_net_154 ) , + .X ( ropt_net_172 ) ) ; endmodule @@ -33597,6 +33583,8 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -33610,12 +33598,10 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_2 mux_l3_in_0_ ( +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_97 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , - .X ( out[0] ) ) ; endmodule @@ -33707,42 +33693,6 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; -sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( - .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( - .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , - .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , - .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; -endmodule - - -module sb_0__1__mux_tree_tapbuf_size6_1 ( in , sram , sram_inv , out , p0 ) ; -input [0:5] in ; -input [0:2] sram ; -input [0:2] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; - sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , @@ -33766,6 +33716,42 @@ sky130_fd_sc_hd__inv_1 BINV_R_92 ( .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , endmodule +module sb_0__1__mux_tree_tapbuf_size6_1 ( in , sram , sram_inv , out , p0 ) ; +input [0:5] in ; +input [0:2] sram ; +input [0:2] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ; + +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( + .A0 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , + .A1 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .S ( sram[2] ) , + .X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ; +endmodule + + module sb_0__1__mux_tree_tapbuf_size6_0 ( in , sram , sram_inv , out , p0 ) ; input [0:5] in ; input [0:2] sram ; @@ -33834,7 +33820,6 @@ input pReset_E_in ; output pReset_S_out ; input prog_clk_0_E_in ; -wire ropt_net_168 ; wire [0:0] prog_clk ; wire prog_clk_0 ; wire [0:1] mux_tree_tapbuf_size2_0_sram ; @@ -33945,21 +33930,21 @@ sb_0__1__mux_tree_tapbuf_size6_0 mux_top_track_0 ( .sram ( mux_tree_tapbuf_size6_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 } ) , - .out ( chany_top_out[0] ) , .p0 ( optlc_net_151 ) ) ; + .out ( chany_top_out[0] ) , .p0 ( optlc_net_148 ) ) ; sb_0__1__mux_tree_tapbuf_size6_1 mux_top_track_6 ( .in ( { top_left_grid_pin_1_[0] , chanx_right_in[4] , chanx_right_in[15] , chanx_right_in[26] , chany_top_out[9] , chany_top_out[24] } ) , .sram ( mux_tree_tapbuf_size6_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 } ) , - .out ( chany_top_out[3] ) , .p0 ( optlc_net_152 ) ) ; + .out ( chany_top_out[3] ) , .p0 ( optlc_net_146 ) ) ; sb_0__1__mux_tree_tapbuf_size6_2 mux_top_track_12 ( .in ( { top_left_grid_pin_1_[0] , chanx_right_in[6] , chanx_right_in[17] , chanx_right_in[28] , chany_top_out[12] , chany_top_out[27] } ) , .sram ( mux_tree_tapbuf_size6_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 , SYNOPSYS_UNCONNECTED_9 } ) , - .out ( chany_top_out[6] ) , .p0 ( optlc_net_152 ) ) ; + .out ( chany_top_out[6] ) , .p0 ( optlc_net_146 ) ) ; sb_0__1__mux_tree_tapbuf_size6_3 mux_right_track_2 ( .in ( { chany_top_in[0] , chany_bottom_out[7] , right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_40_[0] , @@ -33967,7 +33952,7 @@ sb_0__1__mux_tree_tapbuf_size6_3 mux_right_track_2 ( .sram ( mux_tree_tapbuf_size6_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , - .out ( chanx_right_out[1] ) , .p0 ( optlc_net_149 ) ) ; + .out ( chanx_right_out[1] ) , .p0 ( optlc_net_147 ) ) ; sb_0__1__mux_tree_tapbuf_size6_4 mux_right_track_6 ( .in ( { chany_top_in[2] , chany_bottom_out[9] , right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_39_[0] , @@ -33975,7 +33960,7 @@ sb_0__1__mux_tree_tapbuf_size6_4 mux_right_track_6 ( .sram ( mux_tree_tapbuf_size6_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 , SYNOPSYS_UNCONNECTED_15 } ) , - .out ( chanx_right_out[3] ) , .p0 ( optlc_net_151 ) ) ; + .out ( chanx_right_out[3] ) , .p0 ( optlc_net_144 ) ) ; sb_0__1__mux_tree_tapbuf_size6_5 mux_right_track_8 ( .in ( { chany_top_in[4] , chany_bottom_out[11] , right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_40_[0] , @@ -33983,21 +33968,21 @@ sb_0__1__mux_tree_tapbuf_size6_5 mux_right_track_8 ( .sram ( mux_tree_tapbuf_size6_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_16 , SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 } ) , - .out ( chanx_right_out[4] ) , .p0 ( optlc_net_149 ) ) ; + .out ( chanx_right_out[4] ) , .p0 ( optlc_net_147 ) ) ; sb_0__1__mux_tree_tapbuf_size6_6 mux_bottom_track_7 ( .in ( { chany_bottom_out[9] , chany_bottom_out[24] , chanx_right_in[6] , chanx_right_in[17] , chanx_right_in[28] , bottom_left_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size6_6_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 , SYNOPSYS_UNCONNECTED_21 } ) , - .out ( chany_bottom_out[3] ) , .p0 ( optlc_net_152 ) ) ; + .out ( chany_bottom_out[3] ) , .p0 ( optlc_net_145 ) ) ; sb_0__1__mux_tree_tapbuf_size6 mux_bottom_track_13 ( .in ( { chany_bottom_out[12] , chany_bottom_out[27] , chanx_right_in[4] , chanx_right_in[15] , chanx_right_in[26] , bottom_left_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size6_7_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_22 , SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) , - .out ( chany_bottom_out[6] ) , .p0 ( optlc_net_152 ) ) ; + .out ( chany_bottom_out[6] ) , .p0 ( optlc_net_145 ) ) ; sb_0__1__mux_tree_tapbuf_size6_mem_0 mem_top_track_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , @@ -34043,28 +34028,28 @@ sb_0__1__mux_tree_tapbuf_size5_0 mux_top_track_2 ( .sram ( mux_tree_tapbuf_size5_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 , SYNOPSYS_UNCONNECTED_27 } ) , - .out ( chany_top_out[1] ) , .p0 ( optlc_net_151 ) ) ; + .out ( chany_top_out[1] ) , .p0 ( optlc_net_148 ) ) ; sb_0__1__mux_tree_tapbuf_size5_1 mux_top_track_4 ( .in ( { chanx_right_in[3] , chanx_right_in[14] , chanx_right_in[25] , - chany_top_out[8] , ropt_net_168 } ) , + chany_top_out[8] , chany_top_out[23] } ) , .sram ( mux_tree_tapbuf_size5_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_28 , SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 } ) , - .out ( chany_top_out[2] ) , .p0 ( optlc_net_152 ) ) ; + .out ( chany_top_out[2] ) , .p0 ( optlc_net_146 ) ) ; sb_0__1__mux_tree_tapbuf_size5_2 mux_top_track_10 ( .in ( { chanx_right_in[5] , chanx_right_in[16] , chanx_right_in[27] , chany_top_out[11] , chany_top_out[25] } ) , .sram ( mux_tree_tapbuf_size5_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 , SYNOPSYS_UNCONNECTED_33 } ) , - .out ( chany_top_out[5] ) , .p0 ( optlc_net_152 ) ) ; + .out ( chany_top_out[5] ) , .p0 ( optlc_net_146 ) ) ; sb_0__1__mux_tree_tapbuf_size5_3 mux_top_track_20 ( .in ( { chanx_right_in[7] , chanx_right_in[18] , chanx_right_in[29] , chany_top_out[13] , chany_top_out[28] } ) , .sram ( mux_tree_tapbuf_size5_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_34 , SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) , - .out ( chany_top_out[10] ) , .p0 ( optlc_net_152 ) ) ; + .out ( chany_top_out[10] ) , .p0 ( optlc_net_148 ) ) ; sb_0__1__mux_tree_tapbuf_size5_4 mux_right_track_0 ( .in ( { chany_bottom_out[4] , right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_39_[0] , right_bottom_grid_pin_42_[0] , @@ -34072,7 +34057,7 @@ sb_0__1__mux_tree_tapbuf_size5_4 mux_right_track_0 ( .sram ( mux_tree_tapbuf_size5_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 , SYNOPSYS_UNCONNECTED_39 } ) , - .out ( chanx_right_out[0] ) , .p0 ( optlc_net_151 ) ) ; + .out ( chanx_right_out[0] ) , .p0 ( optlc_net_148 ) ) ; sb_0__1__mux_tree_tapbuf_size5_5 mux_right_track_4 ( .in ( { chany_top_in[1] , chany_bottom_out[8] , right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_41_[0] , @@ -34080,7 +34065,7 @@ sb_0__1__mux_tree_tapbuf_size5_5 mux_right_track_4 ( .sram ( mux_tree_tapbuf_size5_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_40 , SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 } ) , - .out ( chanx_right_out[2] ) , .p0 ( optlc_net_151 ) ) ; + .out ( chanx_right_out[2] ) , .p0 ( optlc_net_144 ) ) ; sb_0__1__mux_tree_tapbuf_size5_6 mux_right_track_10 ( .in ( { chany_top_in[5] , chany_bottom_out[12] , right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_41_[0] , @@ -34088,42 +34073,42 @@ sb_0__1__mux_tree_tapbuf_size5_6 mux_right_track_10 ( .sram ( mux_tree_tapbuf_size5_6_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 , SYNOPSYS_UNCONNECTED_45 } ) , - .out ( chanx_right_out[5] ) , .p0 ( optlc_net_149 ) ) ; + .out ( chanx_right_out[5] ) , .p0 ( optlc_net_147 ) ) ; sb_0__1__mux_tree_tapbuf_size5_7 mux_bottom_track_1 ( .in ( { chany_bottom_out[4] , chany_bottom_out[20] , chanx_right_in[9] , chanx_right_in[20] , bottom_left_grid_pin_1_[0] } ) , .sram ( mux_tree_tapbuf_size5_7_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_46 , SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) , - .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_152 ) ) ; + .out ( chany_bottom_out[0] ) , .p0 ( optlc_net_145 ) ) ; sb_0__1__mux_tree_tapbuf_size5_8 mux_bottom_track_5 ( .in ( { chany_bottom_out[8] , chany_bottom_out[23] , chanx_right_in[7] , chanx_right_in[18] , chanx_right_in[29] } ) , .sram ( mux_tree_tapbuf_size5_8_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 , SYNOPSYS_UNCONNECTED_51 } ) , - .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_152 ) ) ; + .out ( chany_bottom_out[2] ) , .p0 ( optlc_net_145 ) ) ; sb_0__1__mux_tree_tapbuf_size5_9 mux_bottom_track_11 ( .in ( { chany_bottom_out[11] , chany_bottom_out[25] , chanx_right_in[5] , chanx_right_in[16] , chanx_right_in[27] } ) , .sram ( mux_tree_tapbuf_size5_9_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_52 , SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 } ) , - .out ( chany_bottom_out[5] ) , .p0 ( optlc_net_152 ) ) ; + .out ( chany_bottom_out[5] ) , .p0 ( optlc_net_145 ) ) ; sb_0__1__mux_tree_tapbuf_size5_10 mux_bottom_track_21 ( .in ( { chany_bottom_out[13] , chany_bottom_out[28] , chanx_right_in[3] , chanx_right_in[14] , chanx_right_in[25] } ) , .sram ( mux_tree_tapbuf_size5_10_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 , SYNOPSYS_UNCONNECTED_57 } ) , - .out ( chany_bottom_out[10] ) , .p0 ( optlc_net_150 ) ) ; + .out ( chany_bottom_out[10] ) , .p0 ( optlc_net_148 ) ) ; sb_0__1__mux_tree_tapbuf_size5 mux_bottom_track_29 ( .in ( { chany_bottom_out[15] , chany_bottom_out[29] , chanx_right_in[2] , chanx_right_in[13] , chanx_right_in[24] } ) , .sram ( mux_tree_tapbuf_size5_11_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_58 , SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) , - .out ( chany_bottom_out[14] ) , .p0 ( optlc_net_150 ) ) ; + .out ( chany_bottom_out[14] ) , .p0 ( optlc_net_143 ) ) ; sb_0__1__mux_tree_tapbuf_size5_mem_0 mem_top_track_2 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) , @@ -34190,84 +34175,84 @@ sb_0__1__mux_tree_tapbuf_size4_0 mux_top_track_28 ( .sram ( mux_tree_tapbuf_size4_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 , SYNOPSYS_UNCONNECTED_63 } ) , - .out ( chany_top_out[14] ) , .p0 ( optlc_net_151 ) ) ; + .out ( chany_top_out[14] ) , .p0 ( optlc_net_148 ) ) ; sb_0__1__mux_tree_tapbuf_size4_1 mux_top_track_52 ( .in ( { chanx_right_in[0] , chanx_right_in[11] , chanx_right_in[22] , chany_top_out[19] } ) , .sram ( mux_tree_tapbuf_size4_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_64 , SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 } ) , - .out ( chany_top_out[26] ) , .p0 ( optlc_net_151 ) ) ; + .out ( chany_top_out[26] ) , .p0 ( optlc_net_148 ) ) ; sb_0__1__mux_tree_tapbuf_size4_2 mux_right_track_12 ( .in ( { chany_top_in[9] , chany_bottom_out[13] , right_bottom_grid_pin_36_[0] , chany_top_out[13] } ) , .sram ( mux_tree_tapbuf_size4_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 , SYNOPSYS_UNCONNECTED_69 } ) , - .out ( chanx_right_out[6] ) , .p0 ( optlc_net_151 ) ) ; + .out ( chanx_right_out[6] ) , .p0 ( optlc_net_147 ) ) ; sb_0__1__mux_tree_tapbuf_size4_3 mux_right_track_14 ( .in ( { chany_top_in[13] , chany_bottom_out[15] , right_bottom_grid_pin_37_[0] , chany_top_out[15] } ) , .sram ( mux_tree_tapbuf_size4_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_70 , SYNOPSYS_UNCONNECTED_71 , SYNOPSYS_UNCONNECTED_72 } ) , - .out ( chanx_right_out[7] ) , .p0 ( optlc_net_151 ) ) ; + .out ( chanx_right_out[7] ) , .p0 ( optlc_net_144 ) ) ; sb_0__1__mux_tree_tapbuf_size4_4 mux_right_track_16 ( .in ( { chany_bottom_out[16] , chany_top_in[17] , right_bottom_grid_pin_38_[0] , chany_top_out[16] } ) , .sram ( mux_tree_tapbuf_size4_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_73 , SYNOPSYS_UNCONNECTED_74 , SYNOPSYS_UNCONNECTED_75 } ) , - .out ( chanx_right_out[8] ) , .p0 ( optlc_net_151 ) ) ; + .out ( chanx_right_out[8] ) , .p0 ( optlc_net_144 ) ) ; sb_0__1__mux_tree_tapbuf_size4_5 mux_right_track_18 ( .in ( { chany_bottom_out[17] , chany_top_in[21] , right_bottom_grid_pin_39_[0] , chany_top_out[17] } ) , .sram ( mux_tree_tapbuf_size4_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_76 , SYNOPSYS_UNCONNECTED_77 , SYNOPSYS_UNCONNECTED_78 } ) , - .out ( chanx_right_out[9] ) , .p0 ( optlc_net_151 ) ) ; + .out ( chanx_right_out[9] ) , .p0 ( optlc_net_144 ) ) ; sb_0__1__mux_tree_tapbuf_size4_6 mux_right_track_20 ( .in ( { chany_bottom_out[19] , chany_top_in[25] , right_bottom_grid_pin_40_[0] , chany_top_out[19] } ) , .sram ( mux_tree_tapbuf_size4_6_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_79 , SYNOPSYS_UNCONNECTED_80 , SYNOPSYS_UNCONNECTED_81 } ) , - .out ( chanx_right_out[10] ) , .p0 ( optlc_net_149 ) ) ; + .out ( chanx_right_out[10] ) , .p0 ( optlc_net_146 ) ) ; sb_0__1__mux_tree_tapbuf_size4_7 mux_right_track_22 ( .in ( { chany_bottom_out[20] , chany_top_in[29] , right_bottom_grid_pin_41_[0] , chany_top_out[20] } ) , .sram ( mux_tree_tapbuf_size4_7_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_82 , SYNOPSYS_UNCONNECTED_83 , SYNOPSYS_UNCONNECTED_84 } ) , - .out ( chanx_right_out[11] ) , .p0 ( optlc_net_149 ) ) ; + .out ( chanx_right_out[11] ) , .p0 ( optlc_net_146 ) ) ; sb_0__1__mux_tree_tapbuf_size4_8 mux_right_track_36 ( .in ( { chany_bottom_out[29] , right_bottom_grid_pin_40_[0] , chany_top_out[29] , chany_bottom_in[29] } ) , .sram ( mux_tree_tapbuf_size4_8_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_85 , SYNOPSYS_UNCONNECTED_86 , SYNOPSYS_UNCONNECTED_87 } ) , - .out ( chanx_right_out[18] ) , .p0 ( optlc_net_150 ) ) ; + .out ( chanx_right_out[18] ) , .p0 ( optlc_net_143 ) ) ; sb_0__1__mux_tree_tapbuf_size4_9 mux_bottom_track_3 ( .in ( { chany_bottom_out[7] , chany_bottom_out[21] , chanx_right_in[8] , chanx_right_in[19] } ) , .sram ( mux_tree_tapbuf_size4_9_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_88 , SYNOPSYS_UNCONNECTED_89 , SYNOPSYS_UNCONNECTED_90 } ) , - .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_150 ) ) ; + .out ( chany_bottom_out[1] ) , .p0 ( optlc_net_143 ) ) ; sb_0__1__mux_tree_tapbuf_size4_10 mux_bottom_track_37 ( .in ( { chany_bottom_out[16] , chanx_right_in[1] , chanx_right_in[12] , chanx_right_in[23] } ) , .sram ( mux_tree_tapbuf_size4_10_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_91 , SYNOPSYS_UNCONNECTED_92 , SYNOPSYS_UNCONNECTED_93 } ) , - .out ( chany_bottom_out[18] ) , .p0 ( optlc_net_150 ) ) ; + .out ( chany_bottom_out[18] ) , .p0 ( optlc_net_143 ) ) ; sb_0__1__mux_tree_tapbuf_size4 mux_bottom_track_45 ( .in ( { chany_bottom_out[17] , chanx_right_in[0] , chanx_right_in[11] , chanx_right_in[22] } ) , .sram ( mux_tree_tapbuf_size4_11_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_94 , SYNOPSYS_UNCONNECTED_95 , SYNOPSYS_UNCONNECTED_96 } ) , - .out ( chany_bottom_out[22] ) , .p0 ( optlc_net_150 ) ) ; + .out ( chany_bottom_out[22] ) , .p0 ( optlc_net_144 ) ) ; sb_0__1__mux_tree_tapbuf_size4_mem_0 mem_top_track_28 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) , @@ -34332,59 +34317,59 @@ sb_0__1__mux_tree_tapbuf_size3_0 mux_top_track_36 ( .in ( { chanx_right_in[9] , chanx_right_in[20] , chany_top_out[16] } ) , .sram ( mux_tree_tapbuf_size3_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_97 , SYNOPSYS_UNCONNECTED_98 } ) , - .out ( chany_top_out[18] ) , .p0 ( optlc_net_151 ) ) ; + .out ( chany_top_out[18] ) , .p0 ( optlc_net_144 ) ) ; sb_0__1__mux_tree_tapbuf_size3_1 mux_top_track_44 ( .in ( { chanx_right_in[10] , chanx_right_in[21] , chany_top_out[17] } ) , .sram ( mux_tree_tapbuf_size3_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_99 , SYNOPSYS_UNCONNECTED_100 } ) , - .out ( chany_top_out[22] ) , .p0 ( optlc_net_151 ) ) ; + .out ( chany_top_out[22] ) , .p0 ( optlc_net_144 ) ) ; sb_0__1__mux_tree_tapbuf_size3_2 mux_right_track_24 ( .in ( { chany_bottom_out[21] , right_bottom_grid_pin_42_[0] , chany_top_out[21] } ) , .sram ( mux_tree_tapbuf_size3_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_101 , SYNOPSYS_UNCONNECTED_102 } ) , - .out ( chanx_right_out[12] ) , .p0 ( optlc_net_149 ) ) ; + .out ( chanx_right_out[12] ) , .p0 ( optlc_net_146 ) ) ; sb_0__1__mux_tree_tapbuf_size3_3 mux_right_track_26 ( .in ( { chany_bottom_out[23] , right_bottom_grid_pin_43_[0] , - ropt_net_168 } ) , + chany_top_out[23] } ) , .sram ( mux_tree_tapbuf_size3_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_103 , SYNOPSYS_UNCONNECTED_104 } ) , - .out ( chanx_right_out[13] ) , .p0 ( optlc_net_149 ) ) ; + .out ( chanx_right_out[13] ) , .p0 ( optlc_net_147 ) ) ; sb_0__1__mux_tree_tapbuf_size3_4 mux_right_track_28 ( .in ( { chany_bottom_out[24] , right_bottom_grid_pin_36_[0] , chany_top_out[24] } ) , .sram ( mux_tree_tapbuf_size3_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_105 , SYNOPSYS_UNCONNECTED_106 } ) , - .out ( chanx_right_out[14] ) , .p0 ( optlc_net_149 ) ) ; + .out ( chanx_right_out[14] ) , .p0 ( optlc_net_148 ) ) ; sb_0__1__mux_tree_tapbuf_size3_5 mux_right_track_30 ( .in ( { chany_bottom_out[25] , right_bottom_grid_pin_37_[0] , chany_top_out[25] } ) , .sram ( mux_tree_tapbuf_size3_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_107 , SYNOPSYS_UNCONNECTED_108 } ) , - .out ( chanx_right_out[15] ) , .p0 ( optlc_net_149 ) ) ; + .out ( chanx_right_out[15] ) , .p0 ( optlc_net_148 ) ) ; sb_0__1__mux_tree_tapbuf_size3_6 mux_right_track_32 ( .in ( { chany_bottom_out[27] , right_bottom_grid_pin_38_[0] , chany_top_out[27] } ) , .sram ( mux_tree_tapbuf_size3_6_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_109 , SYNOPSYS_UNCONNECTED_110 } ) , - .out ( chanx_right_out[16] ) , .p0 ( optlc_net_151 ) ) ; + .out ( chanx_right_out[16] ) , .p0 ( optlc_net_147 ) ) ; sb_0__1__mux_tree_tapbuf_size3_7 mux_right_track_34 ( .in ( { chany_bottom_out[28] , right_bottom_grid_pin_39_[0] , chany_top_out[28] } ) , .sram ( mux_tree_tapbuf_size3_7_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_111 , SYNOPSYS_UNCONNECTED_112 } ) , - .out ( chanx_right_out[17] ) , .p0 ( optlc_net_151 ) ) ; + .out ( chanx_right_out[17] ) , .p0 ( optlc_net_144 ) ) ; sb_0__1__mux_tree_tapbuf_size3_8 mux_right_track_50 ( .in ( { right_bottom_grid_pin_39_[0] , right_bottom_grid_pin_43_[0] , chany_bottom_in[4] } ) , .sram ( mux_tree_tapbuf_size3_8_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_113 , SYNOPSYS_UNCONNECTED_114 } ) , - .out ( chanx_right_out[25] ) , .p0 ( optlc_net_150 ) ) ; + .out ( chanx_right_out[25] ) , .p0 ( optlc_net_143 ) ) ; sb_0__1__mux_tree_tapbuf_size3 mux_bottom_track_53 ( .in ( { chany_bottom_out[19] , chanx_right_in[10] , chanx_right_in[21] } ) , .sram ( mux_tree_tapbuf_size3_9_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_115 , SYNOPSYS_UNCONNECTED_116 } ) , - .out ( chany_bottom_out[26] ) , .p0 ( optlc_net_150 ) ) ; + .out ( chany_bottom_out[26] ) , .p0 ( optlc_net_143 ) ) ; sb_0__1__mux_tree_tapbuf_size3_mem_0 mem_top_track_36 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) , @@ -34438,42 +34423,42 @@ sb_0__1__mux_tree_tapbuf_size2_0 mux_right_track_38 ( .in ( { right_bottom_grid_pin_41_[0] , chany_bottom_in[25] } ) , .sram ( mux_tree_tapbuf_size2_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_117 , SYNOPSYS_UNCONNECTED_118 } ) , - .out ( chanx_right_out[19] ) , .p0 ( optlc_net_150 ) ) ; + .out ( chanx_right_out[19] ) , .p0 ( optlc_net_143 ) ) ; sb_0__1__mux_tree_tapbuf_size2_1 mux_right_track_40 ( .in ( { right_bottom_grid_pin_42_[0] , chany_bottom_in[21] } ) , .sram ( mux_tree_tapbuf_size2_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_119 , SYNOPSYS_UNCONNECTED_120 } ) , - .out ( chanx_right_out[20] ) , .p0 ( optlc_net_150 ) ) ; + .out ( chanx_right_out[20] ) , .p0 ( optlc_net_143 ) ) ; sb_0__1__mux_tree_tapbuf_size2_2 mux_right_track_44 ( .in ( { right_bottom_grid_pin_36_[0] , chany_bottom_in[13] } ) , .sram ( mux_tree_tapbuf_size2_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_121 , SYNOPSYS_UNCONNECTED_122 } ) , - .out ( chanx_right_out[22] ) , .p0 ( optlc_net_150 ) ) ; + .out ( chanx_right_out[22] ) , .p0 ( optlc_net_143 ) ) ; sb_0__1__mux_tree_tapbuf_size2_3 mux_right_track_46 ( .in ( { right_bottom_grid_pin_37_[0] , chany_bottom_in[9] } ) , .sram ( mux_tree_tapbuf_size2_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_123 , SYNOPSYS_UNCONNECTED_124 } ) , - .out ( chanx_right_out[23] ) , .p0 ( optlc_net_150 ) ) ; + .out ( chanx_right_out[23] ) , .p0 ( optlc_net_143 ) ) ; sb_0__1__mux_tree_tapbuf_size2_4 mux_right_track_48 ( .in ( { right_bottom_grid_pin_38_[0] , chany_bottom_in[5] } ) , .sram ( mux_tree_tapbuf_size2_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_125 , SYNOPSYS_UNCONNECTED_126 } ) , - .out ( chanx_right_out[24] ) , .p0 ( optlc_net_150 ) ) ; + .out ( chanx_right_out[24] ) , .p0 ( optlc_net_143 ) ) ; sb_0__1__mux_tree_tapbuf_size2_5 mux_right_track_52 ( .in ( { right_bottom_grid_pin_40_[0] , chany_bottom_in[2] } ) , .sram ( mux_tree_tapbuf_size2_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_127 , SYNOPSYS_UNCONNECTED_128 } ) , - .out ( chanx_right_out[26] ) , .p0 ( optlc_net_150 ) ) ; + .out ( chanx_right_out[26] ) , .p0 ( optlc_net_143 ) ) ; sb_0__1__mux_tree_tapbuf_size2_6 mux_right_track_54 ( .in ( { right_bottom_grid_pin_41_[0] , chany_bottom_in[1] } ) , .sram ( mux_tree_tapbuf_size2_6_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_129 , SYNOPSYS_UNCONNECTED_130 } ) , - .out ( chanx_right_out[27] ) , .p0 ( optlc_net_150 ) ) ; + .out ( chanx_right_out[27] ) , .p0 ( optlc_net_143 ) ) ; sb_0__1__mux_tree_tapbuf_size2 mux_right_track_56 ( .in ( { right_bottom_grid_pin_42_[0] , chany_bottom_in[0] } ) , .sram ( mux_tree_tapbuf_size2_7_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_131 , SYNOPSYS_UNCONNECTED_132 } ) , - .out ( chanx_right_out[28] ) , .p0 ( optlc_net_150 ) ) ; + .out ( chanx_right_out[28] ) , .p0 ( optlc_net_143 ) ) ; sb_0__1__mux_tree_tapbuf_size2_mem_0 mem_right_track_38 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_8_ccff_tail ) , @@ -34585,8 +34570,8 @@ sky130_fd_sc_hd__buf_8 FTB_82__81 ( .A ( chany_bottom_in[19] ) , .X ( chany_top_out[20] ) ) ; sky130_fd_sc_hd__buf_8 FTB_83__82 ( .A ( chany_bottom_in[20] ) , .X ( chany_top_out[21] ) ) ; -sky130_fd_sc_hd__buf_1 FTB_84__83 ( .A ( chany_bottom_in[22] ) , - .X ( ropt_net_168 ) ) ; +sky130_fd_sc_hd__buf_8 FTB_84__83 ( .A ( chany_bottom_in[22] ) , + .X ( chany_top_out[23] ) ) ; sky130_fd_sc_hd__buf_8 FTB_85__84 ( .A ( chany_bottom_in[23] ) , .X ( chany_top_out[24] ) ) ; sky130_fd_sc_hd__buf_8 FTB_86__85 ( .A ( chany_bottom_in[24] ) , @@ -34597,16 +34582,18 @@ sky130_fd_sc_hd__buf_8 FTB_88__87 ( .A ( chany_bottom_in[27] ) , .X ( chany_top_out[28] ) ) ; sky130_fd_sc_hd__buf_8 FTB_89__88 ( .A ( chany_bottom_in[28] ) , .X ( chany_top_out[29] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_151 ( .LO ( SYNOPSYS_UNCONNECTED_133 ) , - .HI ( optlc_net_149 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_153 ( .LO ( SYNOPSYS_UNCONNECTED_134 ) , - .HI ( optlc_net_150 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_155 ( .LO ( SYNOPSYS_UNCONNECTED_135 ) , - .HI ( optlc_net_151 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_157 ( .LO ( SYNOPSYS_UNCONNECTED_136 ) , - .HI ( optlc_net_152 ) ) ; -sky130_fd_sc_hd__buf_6 ropt_mt_inst_1340 ( .A ( ropt_net_168 ) , - .X ( chany_top_out[23] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_146 ( .LO ( SYNOPSYS_UNCONNECTED_133 ) , + .HI ( optlc_net_143 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_148 ( .LO ( SYNOPSYS_UNCONNECTED_134 ) , + .HI ( optlc_net_144 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_151 ( .LO ( SYNOPSYS_UNCONNECTED_135 ) , + .HI ( optlc_net_145 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_154 ( .LO ( SYNOPSYS_UNCONNECTED_136 ) , + .HI ( optlc_net_146 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_156 ( .LO ( SYNOPSYS_UNCONNECTED_137 ) , + .HI ( optlc_net_147 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_158 ( .LO ( SYNOPSYS_UNCONNECTED_138 ) , + .HI ( optlc_net_148 ) ) ; endmodule @@ -34889,9 +34876,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_95 ( .A ( BUF_net_96 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_96 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .Y ( BUF_net_96 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_88 ( .A ( BUF_net_89 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_89 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_89 ) ) ; endmodule @@ -34918,9 +34905,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_93 ( .A ( BUF_net_94 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_94 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .Y ( BUF_net_94 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_86 ( .A ( BUF_net_87 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_87 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_87 ) ) ; endmodule @@ -34947,9 +34934,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_99 ( .A ( BUF_net_100 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_100 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .Y ( BUF_net_100 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_90 ( .A ( BUF_net_91 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_91 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_91 ) ) ; endmodule @@ -34976,9 +34963,9 @@ sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ ( .A0 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .A1 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .S ( sram[2] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_91 ( .A ( BUF_net_92 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_92 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , - .Y ( BUF_net_92 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_84 ( .A ( BUF_net_85 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_85 ( .A ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , + .Y ( BUF_net_85 ) ) ; endmodule @@ -35022,14 +35009,14 @@ sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__buf_6 FTB_26__25 ( .A ( copt_net_116 ) , +sky130_fd_sc_hd__buf_8 FTB_26__25 ( .A ( copt_net_108 ) , .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1278 ( .A ( mem_out[1] ) , - .X ( copt_net_114 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1279 ( .A ( copt_net_114 ) , - .X ( copt_net_115 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1280 ( .A ( copt_net_115 ) , - .X ( copt_net_116 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1272 ( .A ( mem_out[1] ) , + .X ( copt_net_106 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1273 ( .A ( copt_net_106 ) , + .X ( copt_net_107 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1274 ( .A ( copt_net_107 ) , + .X ( copt_net_108 ) ) ; endmodule @@ -35425,29 +35412,29 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:1] mem_out ; -sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_194 ) , +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_191 ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1271 ( .A ( ccff_head[0] ) , - .X ( copt_net_107 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1272 ( .A ( copt_net_107 ) , - .X ( copt_net_108 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1273 ( .A ( copt_net_108 ) , - .X ( copt_net_109 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1274 ( .A ( copt_net_112 ) , - .X ( copt_net_110 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1275 ( .A ( copt_net_110 ) , - .X ( copt_net_111 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1276 ( .A ( copt_net_109 ) , - .X ( copt_net_112 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1356 ( .A ( copt_net_111 ) , - .X ( ropt_net_192 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1357 ( .A ( ropt_net_192 ) , - .X ( ropt_net_193 ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 ropt_h_inst_1358 ( .A ( ropt_net_193 ) , - .X ( ropt_net_194 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1265 ( .A ( ccff_head[0] ) , + .X ( copt_net_99 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1266 ( .A ( copt_net_99 ) , + .X ( copt_net_100 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1267 ( .A ( copt_net_103 ) , + .X ( copt_net_101 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1268 ( .A ( copt_net_101 ) , + .X ( copt_net_102 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1269 ( .A ( copt_net_100 ) , + .X ( copt_net_103 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1270 ( .A ( copt_net_102 ) , + .X ( copt_net_104 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1355 ( .A ( copt_net_104 ) , + .X ( ropt_net_189 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1356 ( .A ( ropt_net_189 ) , + .X ( ropt_net_190 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 ropt_h_inst_1357 ( .A ( ropt_net_190 ) , + .X ( ropt_net_191 ) ) ; endmodule @@ -35483,12 +35470,11 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_89 ( .A ( BUF_net_90 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_90 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_90 ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_83 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) ) ; endmodule @@ -35507,7 +35493,7 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_88 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_82 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -35542,14 +35528,13 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_86 ( .A ( BUF_net_87 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_87 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_87 ) ) ; endmodule @@ -35565,12 +35550,11 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_84 ( .A ( BUF_net_85 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_85 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_85 ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_81 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) ) ; endmodule @@ -35584,6 +35568,26 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , + .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , + .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , + .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; +endmodule + + +module sb_0__0__mux_tree_tapbuf_size2_18 ( in , sram , sram_inv , out , p0 ) ; +input [0:1] in ; +input [0:1] sram ; +input [0:1] sram_inv ; +output [0:0] out ; +input p0 ; + +wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; +wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; + sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , @@ -35594,26 +35598,6 @@ sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module sb_0__0__mux_tree_tapbuf_size2_18 ( in , sram , sram_inv , out , p0 ) ; -input [0:1] in ; -input [0:1] sram ; -input [0:1] sram_inv ; -output [0:0] out ; -input p0 ; - -wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; -wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; - -sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , - .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , - .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_83 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .X ( out[0] ) ) ; -endmodule - - module sb_0__0__mux_tree_tapbuf_size2_17 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; @@ -35629,9 +35613,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_81 ( .A ( BUF_net_82 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_82 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_82 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_79 ( .A ( BUF_net_80 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_80 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_80 ) ) ; endmodule @@ -35650,9 +35634,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_79 ( .A ( BUF_net_80 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_80 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_80 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_77 ( .A ( BUF_net_78 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_78 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_78 ) ) ; endmodule @@ -35711,9 +35695,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_77 ( .A ( BUF_net_78 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_78 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_78 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_75 ( .A ( BUF_net_76 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_76 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_76 ) ) ; endmodule @@ -35732,7 +35716,7 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__buf_6 BUFT_RR_76 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , +sky130_fd_sc_hd__buf_6 BUFT_RR_74 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; endmodule @@ -35749,12 +35733,11 @@ wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_2 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_74 ( .A ( BUF_net_75 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_75 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_75 ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_73 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) ) ; endmodule @@ -35793,9 +35776,9 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_73 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_73 ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_101 ( .A ( BUF_net_73 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_72 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .Y ( BUF_net_72 ) ) ; +sky130_fd_sc_hd__inv_6 BINV_R_92 ( .A ( BUF_net_72 ) , .Y ( out[0] ) ) ; endmodule @@ -35814,9 +35797,8 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_6 BINV_R_97 ( .A ( BUF_net_98 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_98 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_98 ) ) ; +sky130_fd_sc_hd__buf_6 BUFT_RR_70 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , + .X ( out[0] ) ) ; endmodule @@ -35850,14 +35832,13 @@ input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ; +sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ ( + .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .X ( out[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_70 ( .A ( BUF_net_71 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_71 ( .A ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , - .Y ( BUF_net_71 ) ) ; endmodule @@ -36013,8 +35994,10 @@ output [0:0] ccff_tail ; input pReset_E_in ; input prog_clk_0_E_in ; -wire ropt_net_139 ; -wire ropt_net_140 ; +wire ropt_net_141 ; +wire ropt_net_133 ; +wire ropt_net_134 ; +wire ropt_net_135 ; wire [0:0] prog_clk ; wire prog_clk_0 ; wire [0:1] mux_tree_tapbuf_size2_0_sram ; @@ -36093,132 +36076,132 @@ sb_0__0__mux_tree_tapbuf_size2_0 mux_top_track_0 ( .in ( { top_left_grid_pin_1_[0] , chanx_right_in[1] } ) , .sram ( mux_tree_tapbuf_size2_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 } ) , - .out ( chany_top_out[0] ) , .p0 ( optlc_net_105 ) ) ; + .out ( chany_top_out[0] ) , .p0 ( optlc_net_95 ) ) ; sb_0__0__mux_tree_tapbuf_size2_1 mux_top_track_6 ( .in ( { top_left_grid_pin_1_[0] , chanx_right_in[4] } ) , .sram ( mux_tree_tapbuf_size2_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , - .out ( chany_top_out[3] ) , .p0 ( optlc_net_105 ) ) ; + .out ( chany_top_out[3] ) , .p0 ( optlc_net_95 ) ) ; sb_0__0__mux_tree_tapbuf_size2_2 mux_top_track_12 ( .in ( { top_left_grid_pin_1_[0] , chanx_right_in[7] } ) , .sram ( mux_tree_tapbuf_size2_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 } ) , - .out ( chany_top_out[6] ) , .p0 ( optlc_net_105 ) ) ; + .out ( chany_top_out[6] ) , .p0 ( optlc_net_95 ) ) ; sb_0__0__mux_tree_tapbuf_size2_3 mux_top_track_28 ( .in ( { top_left_grid_pin_1_[0] , chanx_right_in[15] } ) , .sram ( mux_tree_tapbuf_size2_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) , - .out ( chany_top_out[14] ) , .p0 ( optlc_net_105 ) ) ; + .out ( chany_top_out[14] ) , .p0 ( optlc_net_95 ) ) ; sb_0__0__mux_tree_tapbuf_size2_4 mux_top_track_44 ( .in ( { top_left_grid_pin_1_[0] , chanx_right_in[23] } ) , .sram ( mux_tree_tapbuf_size2_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 } ) , - .out ( chany_top_out[22] ) , .p0 ( optlc_net_105 ) ) ; + .out ( chany_top_out[22] ) , .p0 ( optlc_net_95 ) ) ; sb_0__0__mux_tree_tapbuf_size2_5 mux_right_track_14 ( .in ( { chany_top_in[6] , right_bottom_grid_pin_3_[0] } ) , .sram ( mux_tree_tapbuf_size2_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) , - .out ( chanx_right_out[7] ) , .p0 ( optlc_net_105 ) ) ; + .out ( chanx_right_out[7] ) , .p0 ( optlc_net_95 ) ) ; sb_0__0__mux_tree_tapbuf_size2_6 mux_right_track_16 ( .in ( { chany_top_in[7] , right_bottom_grid_pin_5_[0] } ) , .sram ( mux_tree_tapbuf_size2_6_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 } ) , - .out ( chanx_right_out[8] ) , .p0 ( optlc_net_106 ) ) ; + .out ( chanx_right_out[8] ) , .p0 ( optlc_net_94 ) ) ; sb_0__0__mux_tree_tapbuf_size2_7 mux_right_track_18 ( .in ( { chany_top_in[8] , right_bottom_grid_pin_7_[0] } ) , .sram ( mux_tree_tapbuf_size2_7_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) , - .out ( chanx_right_out[9] ) , .p0 ( optlc_net_106 ) ) ; + .out ( chanx_right_out[9] ) , .p0 ( optlc_net_94 ) ) ; sb_0__0__mux_tree_tapbuf_size2_8 mux_right_track_20 ( .in ( { chany_top_in[9] , right_bottom_grid_pin_9_[0] } ) , .sram ( mux_tree_tapbuf_size2_8_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 } ) , - .out ( chanx_right_out[10] ) , .p0 ( optlc_net_106 ) ) ; + .out ( chanx_right_out[10] ) , .p0 ( optlc_net_96 ) ) ; sb_0__0__mux_tree_tapbuf_size2_9 mux_right_track_22 ( .in ( { chany_top_in[10] , right_bottom_grid_pin_11_[0] } ) , .sram ( mux_tree_tapbuf_size2_9_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) , - .out ( chanx_right_out[11] ) , .p0 ( optlc_net_106 ) ) ; + .out ( chanx_right_out[11] ) , .p0 ( optlc_net_96 ) ) ; sb_0__0__mux_tree_tapbuf_size2_10 mux_right_track_24 ( .in ( { chany_top_in[11] , right_bottom_grid_pin_13_[0] } ) , .sram ( mux_tree_tapbuf_size2_10_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 } ) , - .out ( chanx_right_out[12] ) , .p0 ( optlc_net_103 ) ) ; + .out ( chanx_right_out[12] ) , .p0 ( optlc_net_96 ) ) ; sb_0__0__mux_tree_tapbuf_size2_11 mux_right_track_26 ( .in ( { chany_top_in[12] , right_bottom_grid_pin_15_[0] } ) , .sram ( mux_tree_tapbuf_size2_11_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) , - .out ( chanx_right_out[13] ) , .p0 ( optlc_net_103 ) ) ; + .out ( chanx_right_out[13] ) , .p0 ( optlc_net_94 ) ) ; sb_0__0__mux_tree_tapbuf_size2_12 mux_right_track_30 ( .in ( { chany_top_in[14] , right_bottom_grid_pin_3_[0] } ) , .sram ( mux_tree_tapbuf_size2_12_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 } ) , - .out ( chanx_right_out[15] ) , .p0 ( optlc_net_103 ) ) ; + .out ( chanx_right_out[15] ) , .p0 ( optlc_net_98 ) ) ; sb_0__0__mux_tree_tapbuf_size2_13 mux_right_track_32 ( .in ( { chany_top_in[15] , right_bottom_grid_pin_5_[0] } ) , .sram ( mux_tree_tapbuf_size2_13_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) , - .out ( chanx_right_out[16] ) , .p0 ( optlc_net_103 ) ) ; + .out ( chanx_right_out[16] ) , .p0 ( optlc_net_94 ) ) ; sb_0__0__mux_tree_tapbuf_size2_14 mux_right_track_34 ( .in ( { chany_top_in[16] , right_bottom_grid_pin_7_[0] } ) , .sram ( mux_tree_tapbuf_size2_14_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 } ) , - .out ( chanx_right_out[17] ) , .p0 ( optlc_net_106 ) ) ; + .out ( chanx_right_out[17] ) , .p0 ( optlc_net_96 ) ) ; sb_0__0__mux_tree_tapbuf_size2_15 mux_right_track_36 ( .in ( { chany_top_in[17] , right_bottom_grid_pin_9_[0] } ) , .sram ( mux_tree_tapbuf_size2_15_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) , - .out ( chanx_right_out[18] ) , .p0 ( optlc_net_106 ) ) ; + .out ( chanx_right_out[18] ) , .p0 ( optlc_net_94 ) ) ; sb_0__0__mux_tree_tapbuf_size2_16 mux_right_track_38 ( .in ( { chany_top_in[18] , right_bottom_grid_pin_11_[0] } ) , .sram ( mux_tree_tapbuf_size2_16_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 } ) , - .out ( chanx_right_out[19] ) , .p0 ( optlc_net_103 ) ) ; + .out ( chanx_right_out[19] ) , .p0 ( optlc_net_94 ) ) ; sb_0__0__mux_tree_tapbuf_size2_17 mux_right_track_40 ( .in ( { chany_top_in[19] , right_bottom_grid_pin_13_[0] } ) , .sram ( mux_tree_tapbuf_size2_17_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) , - .out ( chanx_right_out[20] ) , .p0 ( optlc_net_103 ) ) ; + .out ( chanx_right_out[20] ) , .p0 ( optlc_net_96 ) ) ; sb_0__0__mux_tree_tapbuf_size2_18 mux_right_track_42 ( .in ( { chany_top_in[20] , right_bottom_grid_pin_15_[0] } ) , .sram ( mux_tree_tapbuf_size2_18_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 } ) , - .out ( chanx_right_out[21] ) , .p0 ( optlc_net_103 ) ) ; + .out ( chanx_right_out[21] ) , .p0 ( optlc_net_96 ) ) ; sb_0__0__mux_tree_tapbuf_size2_19 mux_right_track_46 ( .in ( { chany_top_in[22] , right_bottom_grid_pin_3_[0] } ) , .sram ( mux_tree_tapbuf_size2_19_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) , - .out ( chanx_right_out[23] ) , .p0 ( optlc_net_106 ) ) ; + .out ( chanx_right_out[23] ) , .p0 ( optlc_net_95 ) ) ; sb_0__0__mux_tree_tapbuf_size2_20 mux_right_track_48 ( .in ( { chany_top_in[23] , right_bottom_grid_pin_5_[0] } ) , .sram ( mux_tree_tapbuf_size2_20_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 } ) , - .out ( chanx_right_out[24] ) , .p0 ( optlc_net_105 ) ) ; + .out ( chanx_right_out[24] ) , .p0 ( optlc_net_95 ) ) ; sb_0__0__mux_tree_tapbuf_size2_21 mux_right_track_50 ( .in ( { chany_top_in[24] , right_bottom_grid_pin_7_[0] } ) , .sram ( mux_tree_tapbuf_size2_21_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) , - .out ( chanx_right_out[25] ) , .p0 ( optlc_net_105 ) ) ; + .out ( chanx_right_out[25] ) , .p0 ( optlc_net_95 ) ) ; sb_0__0__mux_tree_tapbuf_size2_22 mux_right_track_52 ( .in ( { chany_top_in[25] , right_bottom_grid_pin_9_[0] } ) , .sram ( mux_tree_tapbuf_size2_22_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 } ) , - .out ( chanx_right_out[26] ) , .p0 ( optlc_net_103 ) ) ; + .out ( chanx_right_out[26] ) , .p0 ( optlc_net_94 ) ) ; sb_0__0__mux_tree_tapbuf_size2_23 mux_right_track_54 ( .in ( { chany_top_in[26] , right_bottom_grid_pin_11_[0] } ) , .sram ( mux_tree_tapbuf_size2_23_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) , - .out ( chanx_right_out[27] ) , .p0 ( optlc_net_103 ) ) ; + .out ( chanx_right_out[27] ) , .p0 ( optlc_net_94 ) ) ; sb_0__0__mux_tree_tapbuf_size2_24 mux_right_track_56 ( .in ( { chany_top_in[27] , right_bottom_grid_pin_13_[0] } ) , .sram ( mux_tree_tapbuf_size2_24_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 } ) , - .out ( chanx_right_out[28] ) , .p0 ( optlc_net_103 ) ) ; + .out ( chanx_right_out[28] ) , .p0 ( optlc_net_98 ) ) ; sb_0__0__mux_tree_tapbuf_size2 mux_right_track_58 ( .in ( { chany_top_in[28] , right_bottom_grid_pin_15_[0] } ) , .sram ( mux_tree_tapbuf_size2_25_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) , - .out ( chanx_right_out[29] ) , .p0 ( optlc_net_103 ) ) ; + .out ( chanx_right_out[29] ) , .p0 ( optlc_net_94 ) ) ; sb_0__0__mux_tree_tapbuf_size2_mem_0 mem_top_track_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) , .ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) , @@ -36353,42 +36336,42 @@ sb_0__0__mux_tree_tapbuf_size4_0 mux_right_track_0 ( .sram ( mux_tree_tapbuf_size4_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 , SYNOPSYS_UNCONNECTED_55 } ) , - .out ( chanx_right_out[0] ) , .p0 ( optlc_net_104 ) ) ; + .out ( chanx_right_out[0] ) , .p0 ( optlc_net_97 ) ) ; sb_0__0__mux_tree_tapbuf_size4_1 mux_right_track_2 ( .in ( { chany_top_in[0] , right_bottom_grid_pin_3_[0] , right_bottom_grid_pin_9_[0] , right_bottom_grid_pin_15_[0] } ) , .sram ( mux_tree_tapbuf_size4_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_56 , SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 } ) , - .out ( chanx_right_out[1] ) , .p0 ( optlc_net_104 ) ) ; + .out ( chanx_right_out[1] ) , .p0 ( optlc_net_97 ) ) ; sb_0__0__mux_tree_tapbuf_size4_2 mux_right_track_4 ( .in ( { chany_top_in[1] , right_bottom_grid_pin_5_[0] , right_bottom_grid_pin_11_[0] , right_bottom_grid_pin_17_[0] } ) , .sram ( mux_tree_tapbuf_size4_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 , SYNOPSYS_UNCONNECTED_61 } ) , - .out ( chanx_right_out[2] ) , .p0 ( optlc_net_104 ) ) ; + .out ( chanx_right_out[2] ) , .p0 ( optlc_net_97 ) ) ; sb_0__0__mux_tree_tapbuf_size4_3 mux_right_track_6 ( .in ( { chany_top_in[2] , right_bottom_grid_pin_1_[0] , right_bottom_grid_pin_7_[0] , right_bottom_grid_pin_13_[0] } ) , .sram ( mux_tree_tapbuf_size4_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_62 , SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) , - .out ( chanx_right_out[3] ) , .p0 ( optlc_net_104 ) ) ; + .out ( chanx_right_out[3] ) , .p0 ( optlc_net_97 ) ) ; sb_0__0__mux_tree_tapbuf_size4_4 mux_right_track_8 ( .in ( { chany_top_in[3] , right_bottom_grid_pin_3_[0] , right_bottom_grid_pin_9_[0] , right_bottom_grid_pin_15_[0] } ) , .sram ( mux_tree_tapbuf_size4_4_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 , SYNOPSYS_UNCONNECTED_67 } ) , - .out ( chanx_right_out[4] ) , .p0 ( optlc_net_104 ) ) ; + .out ( chanx_right_out[4] ) , .p0 ( optlc_net_97 ) ) ; sb_0__0__mux_tree_tapbuf_size4 mux_right_track_10 ( .in ( { chany_top_in[4] , right_bottom_grid_pin_5_[0] , right_bottom_grid_pin_11_[0] , right_bottom_grid_pin_17_[0] } ) , .sram ( mux_tree_tapbuf_size4_5_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_68 , SYNOPSYS_UNCONNECTED_69 , SYNOPSYS_UNCONNECTED_70 } ) , - .out ( chanx_right_out[5] ) , .p0 ( optlc_net_104 ) ) ; + .out ( chanx_right_out[5] ) , .p0 ( optlc_net_97 ) ) ; sb_0__0__mux_tree_tapbuf_size4_mem_0 mem_right_track_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) , @@ -36424,19 +36407,19 @@ sb_0__0__mux_tree_tapbuf_size3_0 mux_right_track_12 ( right_bottom_grid_pin_17_[0] } ) , .sram ( mux_tree_tapbuf_size3_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_71 , SYNOPSYS_UNCONNECTED_72 } ) , - .out ( chanx_right_out[6] ) , .p0 ( optlc_net_104 ) ) ; + .out ( chanx_right_out[6] ) , .p0 ( optlc_net_98 ) ) ; sb_0__0__mux_tree_tapbuf_size3_1 mux_right_track_28 ( .in ( { chany_top_in[13] , right_bottom_grid_pin_1_[0] , right_bottom_grid_pin_17_[0] } ) , .sram ( mux_tree_tapbuf_size3_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_73 , SYNOPSYS_UNCONNECTED_74 } ) , - .out ( chanx_right_out[14] ) , .p0 ( optlc_net_103 ) ) ; + .out ( chanx_right_out[14] ) , .p0 ( optlc_net_98 ) ) ; sb_0__0__mux_tree_tapbuf_size3 mux_right_track_44 ( .in ( { chany_top_in[21] , right_bottom_grid_pin_1_[0] , right_bottom_grid_pin_17_[0] } ) , .sram ( mux_tree_tapbuf_size3_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_75 , SYNOPSYS_UNCONNECTED_76 } ) , - .out ( chanx_right_out[22] ) , .p0 ( optlc_net_103 ) ) ; + .out ( chanx_right_out[22] ) , .p0 ( optlc_net_98 ) ) ; sb_0__0__mux_tree_tapbuf_size3_mem_0 mem_right_track_12 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) , @@ -36455,39 +36438,39 @@ sb_0__0__mux_tree_tapbuf_size3_mem mem_right_track_44 ( .pReset ( pReset ) , sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_E_in ) , .X ( pReset[0] ) ) ; sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_E_in ) , .X ( prog_clk[0] ) ) ; -sky130_fd_sc_hd__buf_6 FTB_36__35 ( .A ( chanx_right_in[0] ) , - .X ( ropt_net_139 ) ) ; -sky130_fd_sc_hd__buf_8 FTB_37__36 ( .A ( chanx_right_in[2] ) , - .X ( chany_top_out[1] ) ) ; +sky130_fd_sc_hd__buf_8 FTB_36__35 ( .A ( chanx_right_in[0] ) , + .X ( chany_top_out[29] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_37__36 ( .A ( chanx_right_in[2] ) , + .X ( ropt_net_141 ) ) ; sky130_fd_sc_hd__buf_8 FTB_38__37 ( .A ( chanx_right_in[3] ) , .X ( chany_top_out[2] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chanx_right_in[5] ) , - .X ( chany_top_out[4] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_39__38 ( .A ( chanx_right_in[5] ) , + .X ( ropt_net_133 ) ) ; sky130_fd_sc_hd__buf_8 FTB_40__39 ( .A ( chanx_right_in[6] ) , .X ( chany_top_out[5] ) ) ; sky130_fd_sc_hd__buf_8 FTB_41__40 ( .A ( chanx_right_in[8] ) , .X ( chany_top_out[7] ) ) ; sky130_fd_sc_hd__buf_6 FTB_42__41 ( .A ( chanx_right_in[9] ) , .X ( chany_top_out[8] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_43__42 ( .A ( chanx_right_in[10] ) , - .X ( chany_top_out[9] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_43__42 ( .A ( chanx_right_in[10] ) , + .X ( ropt_net_134 ) ) ; sky130_fd_sc_hd__buf_8 FTB_44__43 ( .A ( chanx_right_in[11] ) , .X ( chany_top_out[10] ) ) ; sky130_fd_sc_hd__buf_8 FTB_45__44 ( .A ( chanx_right_in[12] ) , .X ( chany_top_out[11] ) ) ; -sky130_fd_sc_hd__buf_8 FTB_46__45 ( .A ( chanx_right_in[13] ) , - .X ( chany_top_out[12] ) ) ; +sky130_fd_sc_hd__buf_6 FTB_46__45 ( .A ( chanx_right_in[13] ) , + .X ( ropt_net_135 ) ) ; sky130_fd_sc_hd__buf_8 FTB_47__46 ( .A ( chanx_right_in[14] ) , .X ( chany_top_out[13] ) ) ; sky130_fd_sc_hd__buf_8 FTB_48__47 ( .A ( chanx_right_in[16] ) , .X ( chany_top_out[15] ) ) ; -sky130_fd_sc_hd__buf_6 FTB_49__48 ( .A ( chanx_right_in[17] ) , - .X ( ropt_net_140 ) ) ; +sky130_fd_sc_hd__buf_8 FTB_49__48 ( .A ( chanx_right_in[17] ) , + .X ( chany_top_out[16] ) ) ; sky130_fd_sc_hd__buf_8 FTB_50__49 ( .A ( chanx_right_in[18] ) , .X ( chany_top_out[17] ) ) ; sky130_fd_sc_hd__buf_8 FTB_51__50 ( .A ( chanx_right_in[19] ) , .X ( chany_top_out[18] ) ) ; -sky130_fd_sc_hd__buf_6 FTB_52__51 ( .A ( chanx_right_in[20] ) , +sky130_fd_sc_hd__buf_8 FTB_52__51 ( .A ( chanx_right_in[20] ) , .X ( chany_top_out[19] ) ) ; sky130_fd_sc_hd__buf_8 FTB_53__52 ( .A ( chanx_right_in[21] ) , .X ( chany_top_out[20] ) ) ; @@ -36505,18 +36488,24 @@ sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( chanx_right_in[28] ) , .X ( chany_top_out[27] ) ) ; sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( chanx_right_in[29] ) , .X ( chany_top_out[28] ) ) ; -sky130_fd_sc_hd__conb_1 optlc_105 ( .LO ( SYNOPSYS_UNCONNECTED_77 ) , - .HI ( optlc_net_103 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_107 ( .LO ( SYNOPSYS_UNCONNECTED_78 ) , - .HI ( optlc_net_104 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_109 ( .LO ( SYNOPSYS_UNCONNECTED_79 ) , - .HI ( optlc_net_105 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_111 ( .LO ( SYNOPSYS_UNCONNECTED_80 ) , - .HI ( optlc_net_106 ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1303 ( .A ( ropt_net_139 ) , - .X ( chany_top_out[29] ) ) ; -sky130_fd_sc_hd__buf_8 ropt_mt_inst_1304 ( .A ( ropt_net_140 ) , - .X ( chany_top_out[16] ) ) ; +sky130_fd_sc_hd__conb_1 optlc_96 ( .LO ( SYNOPSYS_UNCONNECTED_77 ) , + .HI ( optlc_net_94 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_99 ( .LO ( SYNOPSYS_UNCONNECTED_78 ) , + .HI ( optlc_net_95 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_101 ( .LO ( SYNOPSYS_UNCONNECTED_79 ) , + .HI ( optlc_net_96 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_103 ( .LO ( SYNOPSYS_UNCONNECTED_80 ) , + .HI ( optlc_net_97 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_105 ( .LO ( SYNOPSYS_UNCONNECTED_81 ) , + .HI ( optlc_net_98 ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1299 ( .A ( ropt_net_133 ) , + .X ( chany_top_out[4] ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1300 ( .A ( ropt_net_134 ) , + .X ( chany_top_out[9] ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1301 ( .A ( ropt_net_135 ) , + .X ( chany_top_out[12] ) ) ; +sky130_fd_sc_hd__buf_8 ropt_mt_inst_1307 ( .A ( ropt_net_141 ) , + .X ( chany_top_out[1] ) ) ; endmodule @@ -36534,16 +36523,16 @@ sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; sky130_fd_sc_hd__buf_6 FTB_63__62 ( .A ( copt_net_196 ) , .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1614 ( .A ( copt_net_198 ) , - .X ( copt_net_195 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1615 ( .A ( copt_net_195 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1637 ( .A ( copt_net_200 ) , .X ( copt_net_196 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1616 ( .A ( copt_net_199 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1638 ( .A ( copt_net_199 ) , .X ( copt_net_197 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1617 ( .A ( copt_net_197 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1639 ( .A ( mem_out[1] ) , .X ( copt_net_198 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1618 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1640 ( .A ( copt_net_198 ) , .X ( copt_net_199 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1641 ( .A ( copt_net_197 ) , + .X ( copt_net_200 ) ) ; endmodule @@ -36643,10 +36632,10 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( aps_rename_521_ ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_129 ( .A ( BUF_net_131 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_130 ( .A ( BUF_net_131 ) , .Y ( p_abuf0 ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_131 ( .A ( aps_rename_521_ ) , - .Y ( BUF_net_131 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_130 ( .A ( BUF_net_132 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_131 ( .A ( BUF_net_132 ) , .Y ( p_abuf0 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_132 ( .A ( aps_rename_521_ ) , + .Y ( BUF_net_132 ) ) ; endmodule @@ -36666,10 +36655,10 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( aps_rename_520_ ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_126 ( .A ( BUF_net_128 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_127 ( .A ( BUF_net_128 ) , .Y ( p_abuf0 ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_128 ( .A ( aps_rename_520_ ) , - .Y ( BUF_net_128 ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_127 ( .A ( BUF_net_129 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_128 ( .A ( BUF_net_129 ) , .Y ( p_abuf0 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_129 ( .A ( aps_rename_520_ ) , + .Y ( BUF_net_129 ) ) ; endmodule @@ -36686,10 +36675,12 @@ output p_abuf1 ; sky130_fd_sc_hd__sdfrtp_1 sky130_fd_sc_hd__sdfrtp_1_0_ ( .D ( ff_D[0] ) , .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( ff_clk[0] ) , - .RESET_B ( ff_reset[0] ) , .Q ( p_abuf1 ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_81 ( .A ( BUF_net_83 ) , .Y ( ff_Q[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_82 ( .A ( BUF_net_83 ) , .Y ( p_abuf0 ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_83 ( .A ( p_abuf1 ) , .Y ( BUF_net_83 ) ) ; + .RESET_B ( ff_reset[0] ) , .Q ( aps_rename_519_ ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_81 ( .A ( BUF_net_84 ) , .Y ( ff_Q[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_82 ( .A ( BUF_net_84 ) , .Y ( p_abuf0 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_83 ( .A ( BUF_net_84 ) , .Y ( p_abuf1 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_84 ( .A ( aps_rename_519_ ) , + .Y ( BUF_net_84 ) ) ; endmodule @@ -37051,7 +37042,7 @@ module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric ( pReset , prog_clk , Test_en , fabric_in , fabric_reg_in , fabric_sc_in , fabric_cin , fabric_reset , fabric_clk , ccff_head , fabric_out , fabric_reg_out , fabric_sc_out , fabric_cout , ccff_tail , p_abuf0 , - p_abuf2 , p_abuf3 , p0 ) ; + p_abuf2 , p_abuf3 , p0 , p1 ) ; input [0:0] pReset ; input [0:0] prog_clk ; input [0:0] Test_en ; @@ -37071,6 +37062,7 @@ output p_abuf0 ; output p_abuf2 ; output p_abuf3 ; input p0 ; +input p1 ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ; @@ -37095,7 +37087,7 @@ grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ .frac_logic_cout ( { SYNOPSYS_UNCONNECTED_1 } ) , .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , - .p0 ( p0 ) ) ; + .p0 ( p1 ) ) ; grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_14 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( .Test_en ( Test_en ) , .ff_D ( mux_tree_size2_2_out ) , .ff_DI ( fabric_sc_in ) , .ff_reset ( fabric_reset ) , @@ -37113,14 +37105,14 @@ grid_clb_mux_tree_size2_44 mux_fabric_out_0 ( } ) , .sram ( mux_tree_size2_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 } ) , - .out ( fabric_out[0] ) , .p_abuf0 ( p_abuf2 ) , .p0 ( p0 ) ) ; + .out ( fabric_out[0] ) , .p_abuf0 ( p_abuf2 ) , .p0 ( p1 ) ) ; grid_clb_mux_tree_size2_45 mux_fabric_out_1 ( - .in ( { fabric_sc_out[0] , + .in ( { p_abuf1 , logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] } ) , .sram ( mux_tree_size2_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 } ) , - .out ( fabric_out[1] ) , .p_abuf0 ( p_abuf3 ) , .p0 ( p0 ) ) ; + .out ( fabric_out[1] ) , .p_abuf0 ( p_abuf3 ) , .p0 ( p1 ) ) ; grid_clb_mux_tree_size2_46 mux_ff_0_D_0 ( .in ( { logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] , @@ -37135,7 +37127,7 @@ grid_clb_mux_tree_size2 mux_ff_1_D_0 ( } ) , .sram ( mux_tree_size2_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_8 , SYNOPSYS_UNCONNECTED_9 } ) , - .out ( mux_tree_size2_3_out ) , .p0 ( p0 ) ) ; + .out ( mux_tree_size2_3_out ) , .p0 ( p1 ) ) ; grid_clb_mux_tree_size2_mem_44 mem_fabric_out_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , @@ -37160,7 +37152,7 @@ endmodule module grid_clb_logical_tile_clb_mode_default__fle ( pReset , prog_clk , Test_en , fle_in , fle_reg_in , fle_sc_in , fle_cin , fle_reset , fle_clk , ccff_head , fle_out , fle_reg_out , fle_sc_out , fle_cout , - ccff_tail , p_abuf0 , p_abuf1 , p_abuf2 , p1 ) ; + ccff_tail , p_abuf0 , p_abuf1 , p_abuf2 , p0 , p1 ) ; input [0:0] pReset ; input [0:0] prog_clk ; input [0:0] Test_en ; @@ -37179,6 +37171,7 @@ output [0:0] ccff_tail ; output p_abuf0 ; output p_abuf1 ; output p_abuf2 ; +input p0 ; input p1 ; grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( @@ -37191,7 +37184,7 @@ grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric logical_tile_c .fabric_reg_out ( fle_reg_out ) , .fabric_sc_out ( fle_sc_out ) , .fabric_cout ( fle_cout ) , .ccff_tail ( ccff_tail ) , .p_abuf0 ( p_abuf0 ) , .p_abuf2 ( p_abuf1 ) , .p_abuf3 ( p_abuf2 ) , - .p0 ( p1 ) ) ; + .p0 ( p0 ) , .p1 ( p1 ) ) ; endmodule @@ -37307,33 +37300,33 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( aps_rename_518_ ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_123 ( .A ( BUF_net_125 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_124 ( .A ( BUF_net_125 ) , .Y ( p_abuf0 ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_125 ( .A ( aps_rename_518_ ) , - .Y ( BUF_net_125 ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_124 ( .A ( BUF_net_126 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_125 ( .A ( BUF_net_126 ) , .Y ( p_abuf0 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_126 ( .A ( aps_rename_518_ ) , + .Y ( BUF_net_126 ) ) ; endmodule module grid_clb_mux_tree_size2_38 ( in , sram , sram_inv , out , p_abuf0 , - p3 ) ; + p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; output p_abuf0 ; -input p3 ; +input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p3 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( aps_rename_517_ ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_120 ( .A ( BUF_net_122 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_121 ( .A ( BUF_net_122 ) , .Y ( p_abuf0 ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_122 ( .A ( aps_rename_517_ ) , - .Y ( BUF_net_122 ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_121 ( .A ( BUF_net_123 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_122 ( .A ( BUF_net_123 ) , .Y ( p_abuf0 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_123 ( .A ( aps_rename_517_ ) , + .Y ( BUF_net_123 ) ) ; endmodule @@ -37399,18 +37392,18 @@ sky130_fd_sc_hd__buf_1 FTB_50__49 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module grid_clb_mux_tree_size2_37 ( in , sram , sram_inv , out , p3 ) ; +module grid_clb_mux_tree_size2_37 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; -input p3 ; +input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p3 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; endmodule @@ -37644,7 +37637,7 @@ endmodule module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_6 ( pReset , prog_clk , frac_logic_in , frac_logic_cin , ccff_head , - frac_logic_out , frac_logic_cout , ccff_tail , p3 ) ; + frac_logic_out , frac_logic_cout , ccff_tail , p0 , p3 ) ; input [0:0] pReset ; input [0:0] prog_clk ; input [0:3] frac_logic_in ; @@ -37653,6 +37646,7 @@ input [0:0] ccff_head ; output [0:1] frac_logic_out ; output [0:0] frac_logic_cout ; output [0:0] ccff_tail ; +input p0 ; input p3 ; wire [0:0] direct_interc_5_out ; @@ -37694,7 +37688,7 @@ grid_clb_mux_tree_size2_37 mux_frac_lut4_0_in_2 ( .in ( { frac_logic_cin[0] , frac_logic_in[2] } ) , .sram ( mux_tree_size2_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 } ) , - .out ( mux_tree_size2_1_out ) , .p3 ( p3 ) ) ; + .out ( mux_tree_size2_1_out ) , .p0 ( p0 ) ) ; grid_clb_mux_tree_size2_mem_36 mem_frac_logic_out_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_ccff_tail ) , @@ -37755,7 +37749,7 @@ grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ .frac_logic_cout ( { SYNOPSYS_UNCONNECTED_1 } ) , .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , - .p3 ( p3 ) ) ; + .p0 ( p1 ) , .p3 ( p3 ) ) ; grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_12 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( .Test_en ( Test_en ) , .ff_D ( mux_tree_size2_2_out ) , .ff_DI ( fabric_sc_in ) , .ff_reset ( fabric_reset ) , @@ -37773,7 +37767,7 @@ grid_clb_mux_tree_size2_38 mux_fabric_out_0 ( } ) , .sram ( mux_tree_size2_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 } ) , - .out ( fabric_out[0] ) , .p_abuf0 ( p_abuf0 ) , .p3 ( p3 ) ) ; + .out ( fabric_out[0] ) , .p_abuf0 ( p_abuf0 ) , .p0 ( p1 ) ) ; grid_clb_mux_tree_size2_39 mux_fabric_out_1 ( .in ( { fabric_sc_out[0] , logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] @@ -37795,7 +37789,7 @@ grid_clb_mux_tree_size2_41 mux_ff_1_D_0 ( } ) , .sram ( mux_tree_size2_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_8 , SYNOPSYS_UNCONNECTED_9 } ) , - .out ( mux_tree_size2_3_out ) , .p0 ( p1 ) ) ; + .out ( mux_tree_size2_3_out ) , .p0 ( p0 ) ) ; grid_clb_mux_tree_size2_mem_38 mem_fabric_out_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , @@ -37936,18 +37930,18 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p3 ) , endmodule -module grid_clb_mux_tree_size2_34 ( in , sram , sram_inv , out , p0 ) ; +module grid_clb_mux_tree_size2_34 ( in , sram , sram_inv , out , p3 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; -input p0 ; +input p3 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p3 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; endmodule @@ -37968,10 +37962,10 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p3 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( aps_rename_516_ ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_117 ( .A ( BUF_net_119 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_118 ( .A ( BUF_net_119 ) , .Y ( p_abuf0 ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_119 ( .A ( aps_rename_516_ ) , - .Y ( BUF_net_119 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_118 ( .A ( BUF_net_120 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_119 ( .A ( BUF_net_120 ) , .Y ( p_abuf0 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_120 ( .A ( aps_rename_516_ ) , + .Y ( BUF_net_120 ) ) ; endmodule @@ -37991,10 +37985,10 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p3 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( aps_rename_515_ ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_114 ( .A ( BUF_net_116 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_115 ( .A ( BUF_net_116 ) , .Y ( p_abuf0 ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_116 ( .A ( aps_rename_515_ ) , - .Y ( BUF_net_116 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_115 ( .A ( BUF_net_117 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_116 ( .A ( BUF_net_117 ) , .Y ( p_abuf0 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_117 ( .A ( aps_rename_515_ ) , + .Y ( BUF_net_117 ) ) ; endmodule @@ -38371,7 +38365,7 @@ module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_5 ( pReset , prog_clk , Test_en , fabric_in , fabric_reg_in , fabric_sc_in , fabric_cin , fabric_reset , fabric_clk , ccff_head , fabric_out , fabric_reg_out , fabric_sc_out , fabric_cout , ccff_tail , p_abuf0 , - p_abuf1 , p0 , p3 ) ; + p_abuf1 , p3 ) ; input [0:0] pReset ; input [0:0] prog_clk ; input [0:0] Test_en ; @@ -38389,7 +38383,6 @@ output [0:0] fabric_cout ; output [0:0] ccff_tail ; output p_abuf0 ; output p_abuf1 ; -input p0 ; input p3 ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ; @@ -38447,7 +38440,7 @@ grid_clb_mux_tree_size2_34 mux_ff_0_D_0 ( fabric_reg_in[0] } ) , .sram ( mux_tree_size2_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_6 , SYNOPSYS_UNCONNECTED_7 } ) , - .out ( mux_tree_size2_2_out ) , .p0 ( p0 ) ) ; + .out ( mux_tree_size2_2_out ) , .p3 ( p3 ) ) ; grid_clb_mux_tree_size2_35 mux_ff_1_D_0 ( .in ( { logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] , @@ -38480,7 +38473,7 @@ endmodule module grid_clb_logical_tile_clb_mode_default__fle_5 ( pReset , prog_clk , Test_en , fle_in , fle_reg_in , fle_sc_in , fle_cin , fle_reset , fle_clk , ccff_head , fle_out , fle_reg_out , fle_sc_out , fle_cout , - ccff_tail , p_abuf0 , p_abuf1 , p0 , p3 ) ; + ccff_tail , p_abuf0 , p_abuf1 , p3 ) ; input [0:0] pReset ; input [0:0] prog_clk ; input [0:0] Test_en ; @@ -38498,7 +38491,6 @@ output [0:0] fle_cout ; output [0:0] ccff_tail ; output p_abuf0 ; output p_abuf1 ; -input p0 ; input p3 ; grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_5 logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( @@ -38511,7 +38503,7 @@ grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_5 logical_tile .fabric_reg_out ( fle_reg_out ) , .fabric_sc_out ( fle_sc_out ) , .fabric_cout ( { SYNOPSYS_UNCONNECTED_2 } ) , .ccff_tail ( ccff_tail ) , .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , - .p0 ( p0 ) , .p3 ( p3 ) ) ; + .p3 ( p3 ) ) ; endmodule @@ -38579,34 +38571,34 @@ sky130_fd_sc_hd__buf_1 FTB_36__35 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module grid_clb_mux_tree_size2_29 ( in , sram , sram_inv , out , p0 ) ; +module grid_clb_mux_tree_size2_29 ( in , sram , sram_inv , out , p3 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; -input p0 ; +input p3 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p3 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; endmodule -module grid_clb_mux_tree_size2_28 ( in , sram , sram_inv , out , p0 ) ; +module grid_clb_mux_tree_size2_28 ( in , sram , sram_inv , out , p2 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; -input p0 ; +input p2 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; endmodule @@ -38627,33 +38619,33 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p3 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( aps_rename_514_ ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_111 ( .A ( BUF_net_113 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_112 ( .A ( BUF_net_113 ) , .Y ( p_abuf0 ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_113 ( .A ( aps_rename_514_ ) , - .Y ( BUF_net_113 ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_112 ( .A ( BUF_net_114 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_113 ( .A ( BUF_net_114 ) , .Y ( p_abuf0 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_114 ( .A ( aps_rename_514_ ) , + .Y ( BUF_net_114 ) ) ; endmodule module grid_clb_mux_tree_size2_26 ( in , sram , sram_inv , out , p_abuf0 , - p0 ) ; + p3 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; output p_abuf0 ; -input p0 ; +input p3 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p3 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( aps_rename_513_ ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_108 ( .A ( BUF_net_110 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_109 ( .A ( BUF_net_110 ) , .Y ( p_abuf0 ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_110 ( .A ( aps_rename_513_ ) , - .Y ( BUF_net_110 ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_109 ( .A ( BUF_net_111 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_110 ( .A ( BUF_net_111 ) , .Y ( p_abuf0 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_111 ( .A ( aps_rename_513_ ) , + .Y ( BUF_net_111 ) ) ; endmodule @@ -38735,18 +38727,18 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , endmodule -module grid_clb_mux_tree_size2_24 ( in , sram , sram_inv , out , p0 ) ; +module grid_clb_mux_tree_size2_24 ( in , sram , sram_inv , out , p2 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; -input p0 ; +input p2 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; endmodule @@ -38964,7 +38956,7 @@ endmodule module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_4 ( pReset , prog_clk , frac_logic_in , frac_logic_cin , ccff_head , - frac_logic_out , frac_logic_cout , ccff_tail , p0 , p2 ) ; + frac_logic_out , frac_logic_cout , ccff_tail , p2 ) ; input [0:0] pReset ; input [0:0] prog_clk ; input [0:3] frac_logic_in ; @@ -38973,7 +38965,6 @@ input [0:0] ccff_head ; output [0:1] frac_logic_out ; output [0:0] frac_logic_cout ; output [0:0] ccff_tail ; -input p0 ; input p2 ; wire [0:0] direct_interc_5_out ; @@ -39010,7 +39001,7 @@ grid_clb_mux_tree_size2_24 mux_frac_logic_out_0 ( } ) , .sram ( mux_tree_size2_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 } ) , - .out ( frac_logic_out[0] ) , .p0 ( p0 ) ) ; + .out ( frac_logic_out[0] ) , .p2 ( p2 ) ) ; grid_clb_mux_tree_size2_25 mux_frac_lut4_0_in_2 ( .in ( { frac_logic_cin[0] , frac_logic_in[2] } ) , .sram ( mux_tree_size2_1_sram ) , @@ -39031,7 +39022,7 @@ module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_4 ( pReset , prog_clk , Test_en , fabric_in , fabric_reg_in , fabric_sc_in , fabric_cin , fabric_reset , fabric_clk , ccff_head , fabric_out , fabric_reg_out , fabric_sc_out , fabric_cout , ccff_tail , p_abuf0 , - p_abuf1 , p0 , p2 , p3 ) ; + p_abuf1 , p2 , p3 ) ; input [0:0] pReset ; input [0:0] prog_clk ; input [0:0] Test_en ; @@ -39049,7 +39040,6 @@ output [0:0] fabric_cout ; output [0:0] ccff_tail ; output p_abuf0 ; output p_abuf1 ; -input p0 ; input p2 ; input p3 ; @@ -39076,7 +39066,7 @@ grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ .frac_logic_cout ( { SYNOPSYS_UNCONNECTED_1 } ) , .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , - .p0 ( p0 ) , .p2 ( p2 ) ) ; + .p2 ( p2 ) ) ; grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_8 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( .Test_en ( Test_en ) , .ff_D ( mux_tree_size2_2_out ) , .ff_DI ( fabric_sc_in ) , .ff_reset ( fabric_reset ) , @@ -39094,7 +39084,7 @@ grid_clb_mux_tree_size2_26 mux_fabric_out_0 ( } ) , .sram ( mux_tree_size2_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 } ) , - .out ( fabric_out[0] ) , .p_abuf0 ( p_abuf0 ) , .p0 ( p0 ) ) ; + .out ( fabric_out[0] ) , .p_abuf0 ( p_abuf0 ) , .p3 ( p3 ) ) ; grid_clb_mux_tree_size2_27 mux_fabric_out_1 ( .in ( { fabric_sc_out[0] , logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] @@ -39108,7 +39098,7 @@ grid_clb_mux_tree_size2_28 mux_ff_0_D_0 ( fabric_reg_in[0] } ) , .sram ( mux_tree_size2_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_6 , SYNOPSYS_UNCONNECTED_7 } ) , - .out ( mux_tree_size2_2_out ) , .p0 ( p0 ) ) ; + .out ( mux_tree_size2_2_out ) , .p2 ( p2 ) ) ; grid_clb_mux_tree_size2_29 mux_ff_1_D_0 ( .in ( { logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] , @@ -39116,7 +39106,7 @@ grid_clb_mux_tree_size2_29 mux_ff_1_D_0 ( } ) , .sram ( mux_tree_size2_3_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_8 , SYNOPSYS_UNCONNECTED_9 } ) , - .out ( mux_tree_size2_3_out ) , .p0 ( p0 ) ) ; + .out ( mux_tree_size2_3_out ) , .p3 ( p3 ) ) ; grid_clb_mux_tree_size2_mem_26 mem_fabric_out_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , @@ -39141,7 +39131,7 @@ endmodule module grid_clb_logical_tile_clb_mode_default__fle_4 ( pReset , prog_clk , Test_en , fle_in , fle_reg_in , fle_sc_in , fle_cin , fle_reset , fle_clk , ccff_head , fle_out , fle_reg_out , fle_sc_out , fle_cout , - ccff_tail , p_abuf0 , p_abuf1 , p0 , p2 , p3 ) ; + ccff_tail , p_abuf0 , p_abuf1 , p2 , p3 ) ; input [0:0] pReset ; input [0:0] prog_clk ; input [0:0] Test_en ; @@ -39159,7 +39149,6 @@ output [0:0] fle_cout ; output [0:0] ccff_tail ; output p_abuf0 ; output p_abuf1 ; -input p0 ; input p2 ; input p3 ; @@ -39173,7 +39162,7 @@ grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_4 logical_tile .fabric_reg_out ( fle_reg_out ) , .fabric_sc_out ( fle_sc_out ) , .fabric_cout ( { SYNOPSYS_UNCONNECTED_2 } ) , .ccff_tail ( ccff_tail ) , .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , - .p0 ( p0 ) , .p2 ( p2 ) , .p3 ( p3 ) ) ; + .p2 ( p2 ) , .p3 ( p3 ) ) ; endmodule @@ -39289,10 +39278,10 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( aps_rename_512_ ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_105 ( .A ( BUF_net_107 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_106 ( .A ( BUF_net_107 ) , .Y ( p_abuf0 ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_107 ( .A ( aps_rename_512_ ) , - .Y ( BUF_net_107 ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_106 ( .A ( BUF_net_108 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_107 ( .A ( BUF_net_108 ) , .Y ( p_abuf0 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_108 ( .A ( aps_rename_512_ ) , + .Y ( BUF_net_108 ) ) ; endmodule @@ -39312,10 +39301,10 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( aps_rename_511_ ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_102 ( .A ( BUF_net_104 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_103 ( .A ( BUF_net_104 ) , .Y ( p_abuf0 ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_104 ( .A ( aps_rename_511_ ) , - .Y ( BUF_net_104 ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_103 ( .A ( BUF_net_105 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_104 ( .A ( BUF_net_105 ) , .Y ( p_abuf0 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_105 ( .A ( aps_rename_511_ ) , + .Y ( BUF_net_105 ) ) ; endmodule @@ -39931,25 +39920,25 @@ endmodule module grid_clb_mux_tree_size2_15 ( in , sram , sram_inv , out , p_abuf0 , - p1 ) ; + p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; output p_abuf0 ; -input p1 ; +input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p1 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( aps_rename_510_ ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_99 ( .A ( BUF_net_101 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_100 ( .A ( BUF_net_101 ) , .Y ( p_abuf0 ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_101 ( .A ( aps_rename_510_ ) , - .Y ( BUF_net_101 ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_100 ( .A ( BUF_net_102 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_101 ( .A ( BUF_net_102 ) , .Y ( p_abuf0 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_102 ( .A ( aps_rename_510_ ) , + .Y ( BUF_net_102 ) ) ; endmodule @@ -39969,10 +39958,10 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p4 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( aps_rename_509_ ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_96 ( .A ( BUF_net_98 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_97 ( .A ( BUF_net_98 ) , .Y ( p_abuf0 ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_98 ( .A ( aps_rename_509_ ) , - .Y ( BUF_net_98 ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_97 ( .A ( BUF_net_99 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_98 ( .A ( BUF_net_99 ) , .Y ( p_abuf0 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_99 ( .A ( aps_rename_509_ ) , + .Y ( BUF_net_99 ) ) ; endmodule @@ -40054,18 +40043,18 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p4 ) , endmodule -module grid_clb_mux_tree_size2_12 ( in , sram , sram_inv , out , p2 ) ; +module grid_clb_mux_tree_size2_12 ( in , sram , sram_inv , out , p4 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; -input p2 ; +input p4 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p4 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; endmodule @@ -40283,7 +40272,7 @@ endmodule module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_2 ( pReset , prog_clk , frac_logic_in , frac_logic_cin , ccff_head , - frac_logic_out , frac_logic_cout , ccff_tail , p2 , p4 ) ; + frac_logic_out , frac_logic_cout , ccff_tail , p4 ) ; input [0:0] pReset ; input [0:0] prog_clk ; input [0:3] frac_logic_in ; @@ -40292,7 +40281,6 @@ input [0:0] ccff_head ; output [0:1] frac_logic_out ; output [0:0] frac_logic_cout ; output [0:0] ccff_tail ; -input p2 ; input p4 ; wire [0:0] direct_interc_5_out ; @@ -40329,7 +40317,7 @@ grid_clb_mux_tree_size2_12 mux_frac_logic_out_0 ( } ) , .sram ( mux_tree_size2_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 } ) , - .out ( frac_logic_out[0] ) , .p2 ( p2 ) ) ; + .out ( frac_logic_out[0] ) , .p4 ( p4 ) ) ; grid_clb_mux_tree_size2_13 mux_frac_lut4_0_in_2 ( .in ( { frac_logic_cin[0] , frac_logic_in[2] } ) , .sram ( mux_tree_size2_1_sram ) , @@ -40350,7 +40338,7 @@ module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_2 ( pReset , prog_clk , Test_en , fabric_in , fabric_reg_in , fabric_sc_in , fabric_cin , fabric_reset , fabric_clk , ccff_head , fabric_out , fabric_reg_out , fabric_sc_out , fabric_cout , ccff_tail , p_abuf0 , - p_abuf1 , p1 , p2 , p4 ) ; + p_abuf1 , p0 , p2 , p4 ) ; input [0:0] pReset ; input [0:0] prog_clk ; input [0:0] Test_en ; @@ -40368,7 +40356,7 @@ output [0:0] fabric_cout ; output [0:0] ccff_tail ; output p_abuf0 ; output p_abuf1 ; -input p1 ; +input p0 ; input p2 ; input p4 ; @@ -40395,7 +40383,7 @@ grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ .frac_logic_cout ( { SYNOPSYS_UNCONNECTED_1 } ) , .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , - .p2 ( p2 ) , .p4 ( p4 ) ) ; + .p4 ( p4 ) ) ; grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_4 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( .Test_en ( Test_en ) , .ff_D ( mux_tree_size2_2_out ) , .ff_DI ( fabric_sc_in ) , .ff_reset ( fabric_reset ) , @@ -40420,7 +40408,7 @@ grid_clb_mux_tree_size2_15 mux_fabric_out_1 ( } ) , .sram ( mux_tree_size2_1_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 } ) , - .out ( fabric_out[1] ) , .p_abuf0 ( p_abuf1 ) , .p1 ( p1 ) ) ; + .out ( fabric_out[1] ) , .p_abuf0 ( p_abuf1 ) , .p0 ( p0 ) ) ; grid_clb_mux_tree_size2_16 mux_ff_0_D_0 ( .in ( { logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] , @@ -40460,7 +40448,7 @@ endmodule module grid_clb_logical_tile_clb_mode_default__fle_2 ( pReset , prog_clk , Test_en , fle_in , fle_reg_in , fle_sc_in , fle_cin , fle_reset , fle_clk , ccff_head , fle_out , fle_reg_out , fle_sc_out , fle_cout , - ccff_tail , p_abuf0 , p_abuf1 , p1 , p2 , p4 ) ; + ccff_tail , p_abuf0 , p_abuf1 , p0 , p2 , p4 ) ; input [0:0] pReset ; input [0:0] prog_clk ; input [0:0] Test_en ; @@ -40478,7 +40466,7 @@ output [0:0] fle_cout ; output [0:0] ccff_tail ; output p_abuf0 ; output p_abuf1 ; -input p1 ; +input p0 ; input p2 ; input p4 ; @@ -40492,7 +40480,7 @@ grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_2 logical_tile .fabric_reg_out ( fle_reg_out ) , .fabric_sc_out ( fle_sc_out ) , .fabric_cout ( { SYNOPSYS_UNCONNECTED_2 } ) , .ccff_tail ( ccff_tail ) , .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , - .p1 ( p1 ) , .p2 ( p2 ) , .p4 ( p4 ) ) ; + .p0 ( p0 ) , .p2 ( p2 ) , .p4 ( p4 ) ) ; endmodule @@ -40576,18 +40564,18 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module grid_clb_mux_tree_size2_10 ( in , sram , sram_inv , out , p1 ) ; +module grid_clb_mux_tree_size2_10 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; -input p1 ; +input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p1 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; endmodule @@ -40607,32 +40595,32 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( aps_rename_508_ ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_93 ( .A ( BUF_net_95 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_94 ( .A ( BUF_net_95 ) , .Y ( p_abuf0 ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_95 ( .A ( aps_rename_508_ ) , - .Y ( BUF_net_95 ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_94 ( .A ( BUF_net_96 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_95 ( .A ( BUF_net_96 ) , .Y ( p_abuf0 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_96 ( .A ( aps_rename_508_ ) , + .Y ( BUF_net_96 ) ) ; endmodule -module grid_clb_mux_tree_size2_8 ( in , sram , sram_inv , out , p_abuf0 , p1 ) ; +module grid_clb_mux_tree_size2_8 ( in , sram , sram_inv , out , p_abuf0 , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; output p_abuf0 ; -input p1 ; +input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p1 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( aps_rename_507_ ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_90 ( .A ( BUF_net_92 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_91 ( .A ( BUF_net_92 ) , .Y ( p_abuf0 ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_92 ( .A ( aps_rename_507_ ) , - .Y ( BUF_net_92 ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_91 ( .A ( BUF_net_93 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_92 ( .A ( BUF_net_93 ) , .Y ( p_abuf0 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_93 ( .A ( aps_rename_507_ ) , + .Y ( BUF_net_93 ) ) ; endmodule @@ -41071,7 +41059,7 @@ grid_clb_mux_tree_size2_8 mux_fabric_out_0 ( } ) , .sram ( mux_tree_size2_0_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 } ) , - .out ( fabric_out[0] ) , .p_abuf0 ( p_abuf0 ) , .p1 ( p1 ) ) ; + .out ( fabric_out[0] ) , .p_abuf0 ( p_abuf0 ) , .p0 ( p0 ) ) ; grid_clb_mux_tree_size2_9 mux_fabric_out_1 ( .in ( { fabric_sc_out[0] , logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] @@ -41085,7 +41073,7 @@ grid_clb_mux_tree_size2_10 mux_ff_0_D_0 ( fabric_reg_in[0] } ) , .sram ( mux_tree_size2_2_sram ) , .sram_inv ( { SYNOPSYS_UNCONNECTED_6 , SYNOPSYS_UNCONNECTED_7 } ) , - .out ( mux_tree_size2_2_out ) , .p1 ( p1 ) ) ; + .out ( mux_tree_size2_2_out ) , .p0 ( p0 ) ) ; grid_clb_mux_tree_size2_11 mux_ff_1_D_0 ( .in ( { logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] , @@ -41264,10 +41252,10 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p1 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( aps_rename_506_ ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_87 ( .A ( BUF_net_89 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_88 ( .A ( BUF_net_89 ) , .Y ( p_abuf0 ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_89 ( .A ( aps_rename_506_ ) , - .Y ( BUF_net_89 ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_88 ( .A ( BUF_net_90 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_89 ( .A ( BUF_net_90 ) , .Y ( p_abuf0 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_90 ( .A ( aps_rename_506_ ) , + .Y ( BUF_net_90 ) ) ; endmodule @@ -41286,10 +41274,10 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p1 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( aps_rename_505_ ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_84 ( .A ( BUF_net_86 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_85 ( .A ( BUF_net_86 ) , .Y ( p_abuf0 ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_86 ( .A ( aps_rename_505_ ) , - .Y ( BUF_net_86 ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_85 ( .A ( BUF_net_87 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_86 ( .A ( BUF_net_87 ) , .Y ( p_abuf0 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_87 ( .A ( aps_rename_505_ ) , + .Y ( BUF_net_87 ) ) ; endmodule @@ -41420,7 +41408,7 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:16] mem_out ; -sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_200 ) , +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_201 ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; @@ -41455,20 +41443,20 @@ sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_15_ ( .D ( mem_out[14] ) , sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_16_ ( .D ( mem_out[15] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[16] ) ) ; sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[16] ) , .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1607 ( .A ( ccff_head[0] ) , - .X ( copt_net_188 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1608 ( .A ( copt_net_191 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1630 ( .A ( ccff_head[0] ) , .X ( copt_net_189 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1609 ( .A ( copt_net_192 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1631 ( .A ( copt_net_194 ) , .X ( copt_net_190 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1610 ( .A ( copt_net_190 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1632 ( .A ( copt_net_190 ) , .X ( copt_net_191 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1611 ( .A ( copt_net_188 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1633 ( .A ( copt_net_189 ) , .X ( copt_net_192 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1612 ( .A ( copt_net_189 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1634 ( .A ( copt_net_192 ) , .X ( copt_net_193 ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 ropt_h_inst_1619 ( .A ( copt_net_193 ) , - .X ( ropt_net_200 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1635 ( .A ( copt_net_193 ) , + .X ( copt_net_194 ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 ropt_h_inst_1642 ( .A ( copt_net_191 ) , + .X ( ropt_net_201 ) ) ; endmodule @@ -41949,7 +41937,7 @@ grid_clb_logical_tile_clb_mode_default__fle_2 logical_tile_clb_mode_default__fle .fle_sc_out ( logical_tile_clb_mode_default__fle_2_fle_sc_out ) , .fle_cout ( { SYNOPSYS_UNCONNECTED_6 } ) , .ccff_tail ( logical_tile_clb_mode_default__fle_2_ccff_tail ) , - .p_abuf0 ( p_abuf5 ) , .p_abuf1 ( p_abuf6 ) , .p1 ( p2 ) , .p2 ( p3 ) , + .p_abuf0 ( p_abuf5 ) , .p_abuf1 ( p_abuf6 ) , .p0 ( p0 ) , .p2 ( p3 ) , .p4 ( p5 ) ) ; grid_clb_logical_tile_clb_mode_default__fle_3 logical_tile_clb_mode_default__fle_3 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , @@ -41978,8 +41966,7 @@ grid_clb_logical_tile_clb_mode_default__fle_4 logical_tile_clb_mode_default__fle .fle_sc_out ( logical_tile_clb_mode_default__fle_4_fle_sc_out ) , .fle_cout ( { SYNOPSYS_UNCONNECTED_10 } ) , .ccff_tail ( logical_tile_clb_mode_default__fle_4_ccff_tail ) , - .p_abuf0 ( p_abuf9 ) , .p_abuf1 ( p_abuf10 ) , .p0 ( p0 ) , .p2 ( p3 ) , - .p3 ( p4 ) ) ; + .p_abuf0 ( p_abuf9 ) , .p_abuf1 ( p_abuf10 ) , .p2 ( p3 ) , .p3 ( p4 ) ) ; grid_clb_logical_tile_clb_mode_default__fle_5 logical_tile_clb_mode_default__fle_5 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .fle_in ( { clb_I5[0] , clb_I5[1] , clb_I5i[0] , clb_I5i[1] } ) , @@ -41993,7 +41980,7 @@ grid_clb_logical_tile_clb_mode_default__fle_5 logical_tile_clb_mode_default__fle .fle_sc_out ( logical_tile_clb_mode_default__fle_5_fle_sc_out ) , .fle_cout ( { SYNOPSYS_UNCONNECTED_12 } ) , .ccff_tail ( logical_tile_clb_mode_default__fle_5_ccff_tail ) , - .p_abuf0 ( p_abuf11 ) , .p_abuf1 ( p_abuf12 ) , .p0 ( p0 ) , .p3 ( p4 ) ) ; + .p_abuf0 ( p_abuf11 ) , .p_abuf1 ( p_abuf12 ) , .p3 ( p4 ) ) ; grid_clb_logical_tile_clb_mode_default__fle_6 logical_tile_clb_mode_default__fle_6 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .fle_in ( { clb_I6[0] , clb_I6[1] , clb_I6i[0] , clb_I6i[1] } ) , @@ -42020,7 +42007,7 @@ grid_clb_logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_7 .fle_out ( { clb_O[15] , clb_O[14] } ) , .fle_reg_out ( clb_reg_out ) , .fle_sc_out ( clb_sc_out ) , .fle_cout ( clb_cout ) , .ccff_tail ( ccff_tail ) , .p_abuf0 ( p_abuf0 ) , - .p_abuf1 ( p_abuf15 ) , .p_abuf2 ( p_abuf16 ) , .p1 ( p1 ) ) ; + .p_abuf1 ( p_abuf15 ) , .p_abuf2 ( p_abuf16 ) , .p0 ( p0 ) , .p1 ( p1 ) ) ; endmodule @@ -42251,9 +42238,9 @@ grid_clb_logical_tile_clb_mode_clb_ logical_tile_clb_mode_clb__0 ( .p_abuf13 ( right_width_0_height_0__pin_49_lower[0] ) , .p_abuf14 ( right_width_0_height_0__pin_48_lower[0] ) , .p_abuf15 ( right_width_0_height_0__pin_51_lower[0] ) , - .p_abuf16 ( p_abuf16 ) , .p0 ( optlc_net_178 ) , .p1 ( optlc_net_179 ) , - .p2 ( optlc_net_180 ) , .p3 ( optlc_net_181 ) , .p4 ( optlc_net_182 ) , - .p5 ( optlc_net_183 ) ) ; + .p_abuf16 ( p_abuf16 ) , .p0 ( optlc_net_179 ) , .p1 ( optlc_net_180 ) , + .p2 ( optlc_net_181 ) , .p3 ( optlc_net_182 ) , .p4 ( optlc_net_183 ) , + .p5 ( optlc_net_184 ) ) ; sky130_fd_sc_hd__buf_2 Test_en_FTB00 ( .A ( Test_en_W_in ) , .X ( Test_en[0] ) ) ; sky130_fd_sc_hd__buf_1 Test_en_W_FTB01 ( .A ( Test_en_W_in ) , @@ -42269,13 +42256,13 @@ sky130_fd_sc_hd__buf_1 Reset_E_FTB01 ( .A ( Reset_W_in ) , sky130_fd_sc_hd__buf_6 prog_clk_0_FTB00 ( .A ( prog_clk_0_S_in ) , .X ( prog_clk_0 ) ) ; sky130_fd_sc_hd__clkbuf_1 prog_clk_0_S_FTB01 ( .A ( prog_clk_0_S_in ) , - .X ( ctsbuf_net_1184 ) ) ; -sky130_fd_sc_hd__clkbuf_1 prog_clk_0_E_FTB01 ( .A ( prog_clk_0_S_in ) , - .X ( ctsbuf_net_2185 ) ) ; -sky130_fd_sc_hd__clkbuf_1 prog_clk_0_W_FTB01 ( .A ( prog_clk_0_S_in ) , - .X ( ctsbuf_net_3186 ) ) ; + .X ( ctsbuf_net_1185 ) ) ; +sky130_fd_sc_hd__buf_4 prog_clk_0_E_FTB01 ( .A ( prog_clk_0_S_in ) , + .X ( ctsbuf_net_2186 ) ) ; +sky130_fd_sc_hd__buf_4 prog_clk_0_W_FTB01 ( .A ( prog_clk_0_S_in ) , + .X ( ctsbuf_net_3187 ) ) ; sky130_fd_sc_hd__clkbuf_1 prog_clk_0_N_FTB01 ( .A ( prog_clk_0_S_in ) , - .X ( ctsbuf_net_4187 ) ) ; + .X ( ctsbuf_net_4188 ) ) ; sky130_fd_sc_hd__buf_1 clk_0_FTB00 ( .A ( clk_0_S_in ) , .X ( clk[0] ) ) ; sky130_fd_sc_hd__buf_6 FTB_65__64 ( .A ( aps_rename_522_ ) , .X ( top_width_0_height_0__pin_36_upper[0] ) ) ; @@ -42311,38 +42298,38 @@ sky130_fd_sc_hd__buf_6 FTB_80__79 ( .A ( aps_rename_537_ ) , .X ( right_width_0_height_0__pin_51_upper[0] ) ) ; sky130_fd_sc_hd__buf_6 FTB_81__80 ( .A ( aps_rename_538_ ) , .X ( SC_OUT_TOP ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_132 ( .A ( BUF_net_133 ) , +sky130_fd_sc_hd__inv_8 BINV_R_133 ( .A ( BUF_net_134 ) , .Y ( Test_en_W_out ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_133 ( .A ( aps_rename_539_ ) , - .Y ( BUF_net_133 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_134 ( .A ( BUF_net_135 ) , +sky130_fd_sc_hd__inv_1 BINV_R_134 ( .A ( aps_rename_539_ ) , + .Y ( BUF_net_134 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_135 ( .A ( BUF_net_136 ) , .Y ( Test_en_E_out ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_135 ( .A ( aps_rename_540_ ) , - .Y ( BUF_net_135 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_136 ( .A ( BUF_net_137 ) , .Y ( Reset_W_out ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_137 ( .A ( aps_rename_541_ ) , - .Y ( BUF_net_137 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_140 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_178 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_142 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , +sky130_fd_sc_hd__inv_1 BINV_R_136 ( .A ( aps_rename_540_ ) , + .Y ( BUF_net_136 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_137 ( .A ( BUF_net_138 ) , .Y ( Reset_W_out ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_138 ( .A ( aps_rename_541_ ) , + .Y ( BUF_net_138 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_141 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , .HI ( optlc_net_179 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_144 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , +sky130_fd_sc_hd__conb_1 optlc_143 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , .HI ( optlc_net_180 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_146 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , +sky130_fd_sc_hd__conb_1 optlc_145 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , .HI ( optlc_net_181 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_148 ( .LO ( SYNOPSYS_UNCONNECTED_6 ) , +sky130_fd_sc_hd__conb_1 optlc_147 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , .HI ( optlc_net_182 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_150 ( .LO ( SYNOPSYS_UNCONNECTED_7 ) , +sky130_fd_sc_hd__conb_1 optlc_149 ( .LO ( SYNOPSYS_UNCONNECTED_6 ) , .HI ( optlc_net_183 ) ) ; -sky130_fd_sc_hd__buf_6 ZBUF_6_f_inst_151 ( .A ( aps_rename_542_ ) , +sky130_fd_sc_hd__conb_1 optlc_151 ( .LO ( SYNOPSYS_UNCONNECTED_7 ) , + .HI ( optlc_net_184 ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_6_f_inst_152 ( .A ( aps_rename_542_ ) , .X ( Reset_E_out ) ) ; -sky130_fd_sc_hd__buf_6 cts_buf_3981324 ( .A ( ctsbuf_net_1184 ) , +sky130_fd_sc_hd__buf_6 cts_buf_3981325 ( .A ( ctsbuf_net_1185 ) , .X ( prog_clk_0_S_out ) ) ; -sky130_fd_sc_hd__clkbuf_8 cts_buf_4031329 ( .A ( ctsbuf_net_2185 ) , +sky130_fd_sc_hd__bufbuf_16 cts_buf_4031330 ( .A ( ctsbuf_net_2186 ) , .X ( prog_clk_0_E_out ) ) ; -sky130_fd_sc_hd__buf_6 cts_buf_4081334 ( .A ( ctsbuf_net_3186 ) , +sky130_fd_sc_hd__buf_6 cts_buf_4081335 ( .A ( ctsbuf_net_3187 ) , .X ( prog_clk_0_W_out ) ) ; -sky130_fd_sc_hd__buf_6 cts_buf_4131339 ( .A ( ctsbuf_net_4187 ) , +sky130_fd_sc_hd__buf_6 cts_buf_4131340 ( .A ( ctsbuf_net_4188 ) , .X ( prog_clk_0_N_out ) ) ; endmodule diff --git a/FPGA1212_QLSOFA_HD_PNR/fpga_top/rpts_icc2/module_utilization.tsv b/FPGA1212_QLSOFA_HD_PNR/fpga_top/rpts_icc2/module_utilization.tsv new file mode 100644 index 0000000..4ba7f3e --- /dev/null +++ b/FPGA1212_QLSOFA_HD_PNR/fpga_top/rpts_icc2/module_utilization.tsv @@ -0,0 +1,18 @@ +| Module | Util| Area| Sites| Insts| Std_Cells +|--------------------|----------|-----------------|-------|-------|------- +|fpga_core_uut/sb_0__0_ | 45.82 | 8718.361600 | 6968 | 1 | 1003 +|fpga_core_uut/sb_0__11_ | 75.59 | 9519.129600 | 7608 | 11 | 855 +|fpga_core_uut/sb_0__12_ | 45.97 | 8718.361600 | 6968 | 1 | 1006 +|fpga_core_uut/sb_11__0_ | 71.29 | 11030.579200 | 8816 | 11 | 1078 +|fpga_core_uut/sb_11__11_ | 90.88 | 11831.347200 | 9456 | 121 | 533 +|fpga_core_uut/sb_11__12_ | 70.54 | 11030.579200 | 8816 | 11 | 1089 +|fpga_core_uut/sb_12__0_ | 64.08 | 8718.361600 | 6968 | 1 | 955 +|fpga_core_uut/sb_12__11_ | 82.83 | 9519.129600 | 7608 | 11 | 624 +|fpga_core_uut/sb_12__12_ | 65.1 | 8718.361600 | 6968 | 1 | 943 +|fpga_core_uut/cbx_12__0_ | 74.63 | 5745.510400 | 4592 | 12 | 439 +|fpga_core_uut/cbx_12__11_ | 88.39 | 5745.510400 | 4592 | 132 | 382 +|fpga_core_uut/cbx_12__12_ | 90.81 | 5745.510400 | 4592 | 12 | 267 +|fpga_core_uut/cby_0__12_ | 23.46 | 6406.144000 | 5120 | 12 | 815 +|fpga_core_uut/cby_11__12_ | 82.05 | 6406.144000 | 5120 | 132 | 444 +|fpga_core_uut/cby_12__12_ | 82.64 | 6406.144000 | 5120 | 12 | 486 +|fpga_core_uut/grid_clb_12__12_ | 68.26 | 14814.208000 | 11840 | 144 | 1370 diff --git a/FPGA1212_QLSOFA_HD_PNR/fpga_top/rpts_icc2/std_cell_utilization.tsv b/FPGA1212_QLSOFA_HD_PNR/fpga_top/rpts_icc2/std_cell_utilization.tsv new file mode 100644 index 0000000..6ed6224 --- /dev/null +++ b/FPGA1212_QLSOFA_HD_PNR/fpga_top/rpts_icc2/std_cell_utilization.tsv @@ -0,0 +1,32 @@ + Ref Name Total Area Utilization_% Instance Count + ---------------------------------------------------------------------------------------------------- + sky130_fd_sc_hd__dfrtp_1 1971015.360000 19.18 78765 + sky130_fd_sc_hd__mux2_1 1591488.864000 15.49 141330 + sky130_fd_sc_hd__buf_8 452744.217600 4.41 30154 + sky130_fd_sc_hd__buf_6 150252.854400 1.46 13343 + sky130_fd_sc_hd__buf_1 88960.320000 0.87 23700 + sky130_fd_sc_hd__inv_8 76584.700800 0.75 6801 + sky130_fd_sc_hd__sdfrtp_1 72069.120000 0.70 2304 + sky130_fd_sc_hd__dlygate4sd3_1 56293.990400 0.55 5624 + sky130_fd_sc_hd__mux2_2 44311.248000 0.43 3935 + sky130_fd_sc_hd__inv_1 42156.681600 0.41 11231 + sky130_fd_sc_hd__buf_4 39112.512000 0.38 5210 + sky130_fd_sc_hd__bufbuf_16 36239.756800 0.35 1114 + sky130_fd_sc_hd__conb_1 25592.044800 0.25 6818 + sky130_fd_sc_hd__inv_2 13696.886400 0.13 3649 + sky130_fd_sc_hd__or2_0 7206.912000 0.07 1152 + sky130_fd_sc_hd__inv_6 6235.980800 0.06 712 + sky130_fd_sc_hd__ebufn_4 5758.022400 0.06 354 + sky130_fd_sc_hd__clkbuf_1 2747.635200 0.03 732 + sky130_fd_sc_hd__dlygate4sd2_1 2417.318400 0.02 276 + sky130_fd_sc_hd__buf_2 1436.377600 0.01 287 + sky130_fd_sc_hd__dlygate4sd1_1 1366.310400 0.01 156 + sky130_fd_sc_hd__nand2b_1 825.792000 0.01 132 + sky130_fd_sc_hd__buf_16 633.107200 0.01 23 + sky130_fd_sc_hd__inv_4 450.432000 0.00 72 + sky130_fd_sc_hd__buf_12 220.211200 0.00 11 + sky130_fd_sc_hd__clkbuf_8 165.158400 0.00 12 + sky130_fd_sc_hd__or2b_4 135.129600 0.00 12 +FPGA_BBOX_AREA 6714279.5264 +CORE_BBOX_AREA 10276128.1216 +FPGA_BBOX_UTIL 65.3386124321 diff --git a/FPGA1212_QLSOFA_HD_PNR/fpga_top/rpts_icc2/timing_reports.txt b/FPGA1212_QLSOFA_HD_PNR/fpga_top/rpts_icc2/timing_reports.txt new file mode 100644 index 0000000..5f575fc --- /dev/null +++ b/FPGA1212_QLSOFA_HD_PNR/fpga_top/rpts_icc2/timing_reports.txt @@ -0,0 +1,75 @@ +**************************************** +Report : clock timing + -type latency + -launch + -nworst 1 + -setup +Design : fpga_top +Version: P-2019.03-SP4 +Date : Mon Dec 14 01:56:02 2020 +**************************************** +Information: Timer using 'PrimeTime Delay Calculation, AWP'. (TIM-050) + + Mode: full_chip + Clock: PROG_CLK + + --- Latency --- + Clock Pin Trans Source Offset Network Total Corner +--------------------------------------------------------------------------------------------------- + fpga_core_uut/sb_11__11_/mem_right_track_2/sky130_fd_sc_hd__dfrtp_1_3_/CLK 6.164 0.000 -- 11.143 11.143 rp-+ nominal +--------------------------------------------------------------------------------------------------- + + Mode: full_chip + Clock: CLK + + --- Latency --- + Clock Pin Trans Source Offset Network Total Corner +--------------------------------------------------------------------------------------------------- + fpga_core_uut/grid_clb_11__12_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1/sky130_fd_sc_hd__sdfrtp_1_0_/CLK 0.710 0.000 -- 6.927 6.927 rp-+ nominal +--------------------------------------------------------------------------------------------------- +**************************************** +Report : clock timing + -type skew + -nworst 1 + -setup +Design : fpga_top +Version: P-2019.03-SP4 +Date : Mon Dec 14 01:56:02 2020 +**************************************** +Information: Timer using 'PrimeTime Delay Calculation, AWP'. (TIM-050) + + Mode: full_chip + Clock: PROG_CLK + + Clock Pin Latency Skew Corner +--------------------------------------------------------------------------------------------------- + fpga_core_uut/sb_10__8_/mem_left_track_53/sky130_fd_sc_hd__dfrtp_1_2_/CLK 9.828 rp-+ nominal + fpga_core_uut/cbx_10__8_/mem_top_ipin_0/sky130_fd_sc_hd__dfrtp_1_0_/CLK 5.994 3.835 rp-+ nominal + +--------------------------------------------------------------------------------------------------- + + Mode: full_chip + Clock: CLK + + Clock Pin Latency Skew Corner +--------------------------------------------------------------------------------------------------- + fpga_core_uut/grid_clb_6__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1/sky130_fd_sc_hd__sdfrtp_1_0_/CLK 6.115 rp-+ nominal + fpga_core_uut/grid_clb_6__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0/sky130_fd_sc_hd__sdfrtp_1_0_/CLK 5.386 0.729 rp-+ nominal + +--------------------------------------------------------------------------------------------------- +Information: Timer using 'PrimeTime Delay Calculation, AWP'. (TIM-050) +**************************************** +Report : global timing + -format { narrow } +Design : fpga_top +Version: P-2019.03-SP4 +Date : Mon Dec 14 01:56:04 2020 +**************************************** + +No setup violations found. + + +No hold violations found. + + +1