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Merge pull request #69 from lnis-uofu/xt_dev 

Update on post-pnr verification files for CHD version
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tangxifan 2020-12-14 15:16:49 -07:00 committed by GitHub
parent 2a9ddcd9a2 e78b234e00
commit f9868a77b1
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22 changed files with 800 additions and 49 deletions
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*.gds filter=lfs diff=lfs merge=lfs -text
*.spef filter=lfs diff=lfs merge=lfs -text
TESTBENCH/*/pnr/verilog_testbench/*_tb.v filter=lfs diff=lfs merge=lfs -text
TESTBENCH/*/*pnr/verilog_testbench/*_tb.v filter=lfs diff=lfs merge=lfs -text

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TESTBENCH/common/post_pnr_fpga_cells.v (Stored with Git LFS)
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TESTBENCH/digital_io_hd_test/digital_io_hd_test.v (Stored with Git LFS)
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TESTBENCH/digital_io_hd_test/digital_io_hd_test_include_netlists.v (Stored with Git LFS)
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TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/and2_latch_post_pnr_include_netlists.v (Stored with Git LFS)
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TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/and2_latch_post_pnr_wrapper_include_netlists.v (Stored with Git LFS)
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TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/and2_or2_post_pnr_include_netlists.v (Stored with Git LFS)
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TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/and2_or2_post_pnr_wrapper_include_netlists.v (Stored with Git LFS)
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TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/and2_post_pnr_include_netlists.v (Stored with Git LFS)
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TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/and2_post_pnr_wrapper_include_netlists.v (Stored with Git LFS)
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TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/bin2bcd_post_pnr_include_netlists.v Normal file
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//-------------------------------------------
// FPGA Synthesizable Verilog Netlist
// Description: Netlist Summary
// Author: Xifan TANG
// Organization: University of Utah
// Date: Wed Nov 11 16:01:30 2020
//-------------------------------------------
//----- Time scale -----
`timescale 1ns / 1ps
// ------ Include simulation defines -----
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/prepnr/verilog_testbench/define_simulation.v"
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/skywater_function_verification.v"
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/fd_hd_mux_custom_cells_tt.v"
// ------ Include Skywater cell netlists -----
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/common/post_pnr_fpga_cells.v"
// ------ Include fabric top-level netlists -----
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/FPGA1212_SOFA_CHD_PNR/fpga_top/fpga_top_icv_in_design.pt.v"
`ifdef AUTOCHECKED_SIMULATION
`include "bin2bcd_output_verilog.v"
`endif
`ifdef AUTOCHECKED_SIMULATION
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/bin2bcd_post_pnr_autocheck_top_tb.v"
`endif

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TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/bin2bcd_post_pnr_wrapper_include_netlists.v Normal file
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//-------------------------------------------
// FPGA Synthesizable Verilog Netlist
// Description: Netlist Summary
// Author: Xifan TANG
// Organization: University of Utah
// Date: Wed Nov 11 16:01:30 2020
//-------------------------------------------
//----- Time scale -----
`timescale 1ns / 1ps
// ------ Include simulation defines -----
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/prepnr/verilog_testbench/define_simulation.v"
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/caravel_defines.v"
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/skywater_function_verification.v"
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/fd_hd_mux_custom_cells_tt.v"
// ------ Include Skywater cell netlists -----
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/common/post_pnr_fpga_cells.v"
// ------ Include fabric top-level netlists -----
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/FPGA1212_SOFA_CHD_PNR/fpga_top/fpga_top_icv_in_design.pt.v"
`ifdef AUTOCHECKED_SIMULATION
`include "bin2bcd_output_verilog.v"
`endif
`ifdef AUTOCHECKED_SIMULATION
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/bin2bcd_post_pnr_wrapper_autocheck_top_tb.v"
`endif

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TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/ccff_test_post_pnr_include_netlists.v (Stored with Git LFS)
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TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/ccff_test_post_pnr_wrapper_include_netlists.v (Stored with Git LFS)
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TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/counter_post_pnr_include_netlists.v (Stored with Git LFS)
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TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/counter_post_pnr_wrapper_include_netlists.v Normal file
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//-------------------------------------------
// FPGA Synthesizable Verilog Netlist
// Description: Netlist Summary
// Author: Xifan TANG
// Organization: University of Utah
// Date: Wed Nov 11 16:01:30 2020
//-------------------------------------------
//----- Time scale -----
`timescale 1ns / 1ps
// ------ Include simulation defines -----
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/prepnr/verilog_testbench/define_simulation.v"
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/caravel_defines.v"
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/skywater_function_verification.v"
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/fd_hd_mux_custom_cells_tt.v"
// ------ Include Skywater cell netlists -----
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/common/post_pnr_fpga_cells.v"
// ------ Include fabric top-level netlists -----
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/FPGA1212_SOFA_CHD_PNR/fpga_top/fpga_top_icv_in_design.pt.v"
`ifdef AUTOCHECKED_SIMULATION
`include "counter_output_verilog.v"
`endif
`ifdef AUTOCHECKED_SIMULATION
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/counter_post_pnr_wrapper_autocheck_top_tb.v"
`endif

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TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/routing_test_post_pnr_include_netlists.v (Stored with Git LFS)
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TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/routing_test_post_pnr_wrapper_include_netlists.v (Stored with Git LFS)
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TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_include_netlists.v (Stored with Git LFS)
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TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_wrapper_include_netlists.v (Stored with Git LFS)
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TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/top_module_post_pnr_include_netlists.v Normal file
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//-------------------------------------------
// FPGA Synthesizable Verilog Netlist
// Description: Netlist Summary
// Author: Xifan TANG
// Organization: University of Utah
// Date: Wed Nov 11 16:01:30 2020
//-------------------------------------------
//----- Time scale -----
`timescale 1ns / 1ps
// ------ Include simulation defines -----
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/prepnr/verilog_testbench/define_simulation.v"
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/skywater_function_verification.v"
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/fd_hd_mux_custom_cells_tt.v"
// ------ Include Skywater cell netlists -----
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/common/post_pnr_fpga_cells.v"
// ------ Include fabric top-level netlists -----
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/FPGA1212_SOFA_CHD_PNR/fpga_top/fpga_top_icv_in_design.pt.v"
`ifdef AUTOCHECKED_SIMULATION
`include "top_module_output_verilog.v"
`endif
`ifdef AUTOCHECKED_SIMULATION
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/top_module_post_pnr_autocheck_top_tb.v"
`endif

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TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/top_module_post_pnr_wrapper_include_netlists.v Normal file
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//-------------------------------------------
// FPGA Synthesizable Verilog Netlist
// Description: Netlist Summary
// Author: Xifan TANG
// Organization: University of Utah
// Date: Wed Nov 11 16:01:30 2020
//-------------------------------------------
//----- Time scale -----
`timescale 1ns / 1ps
// ------ Include simulation defines -----
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/prepnr/verilog_testbench/define_simulation.v"
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/caravel_defines.v"
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/skywater_function_verification.v"
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/fd_hd_mux_custom_cells_tt.v"
// ------ Include Skywater cell netlists -----
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/common/post_pnr_fpga_cells.v"
// ------ Include fabric top-level netlists -----
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/FPGA1212_SOFA_CHD_PNR/fpga_top/fpga_top_icv_in_design.pt.v"
`ifdef AUTOCHECKED_SIMULATION
`include "top_module_output_verilog.v"
`endif
`ifdef AUTOCHECKED_SIMULATION
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_customhd_cc/postpnr/verilog_testbench/top_module_post_pnr_wrapper_autocheck_top_tb.v"
`endif