Merge pull request #72 from lnis-uofu/ganesh_dev

Minor updates to SOFA-HD and QLSOFA-HD to fix LVS test

.github/buildactionScripts.sh

@@ -1,13 +1,13 @@
 #!/bin/bash
 
-SCAN_SOFA_HD_KEY="FPGA1212_FLAT_HD_SKY_PNR"
-SCAN_QLSOFA_HD_KEY="FPGA1212_RESET_HD_SKY_PNR"
+SCAN_SOFA_HD_KEY="FPGA1212_SOFA_HD_PNR"
+SCAN_QLSOFA_HD_KEY="FPGA1212_QLSOFA_HD_PNR"
 SCAN_SOFA_CHD_KEY="FPGA1212_SOFA_CHD_PNR"
 SCAN_QLAP3_KEY="FPGA1212_QLAP3_PNR"
 
 # TODO: Strip comments while reading using yq
 # TODO: Add SOFA_CHD and QLAP3 for later
-for repo in SOFA_HD  QLSOFA_HD ; do
+for repo in SOFA_HD ; do
     ScanDir=$(eval "echo \$SCAN_${repo}_KEY")
     action_filename=$(echo "$repo" | awk '{print tolower($0)}')
     repo_name=$(echo "$repo" | sed "s/_/-/")

.github/deploy_sofa.yaml

@@ -64,6 +64,8 @@ jobs:
           -e DEST_DIR=$DEST_DIR
           -e SCAN_DIRECTORY=$SCAN_DIRECTORY
           --workdir /usr/local/workspace
+          --memory 2g
+          --memory-swap 4g
         run: cd /usr/local/workspace && pwd && ls && bash ./SOFA-Chips/.github/workflows/perform_precheck.sh
 
     - name: Deploy files

.github/workflows/build.yml

@@ -48,17 +48,18 @@ jobs:
         with:
           repository: lnis-uofu/OpenFPGA
           path: OpenFPGA
+          submodules: true
 
       - name: Install dependency
-        run: source ./.github/workflows/install_dependency.sh 
+        run: source ./.github/workflows/install_dependency.sh
 
       - name: Checkout CMake version
-        run: cmake --version 
+        run: cmake --version
 
       - name: Checkout iVerilog version
         run: |
-          iverilog -V 
-          vvp -V 
+          iverilog -V
+          vvp -V
 
       - name: Create CMake build environment
         # Some projects don't allow in-source building, so create a separate build directory
@@ -70,8 +71,8 @@ jobs:
         # access regardless of the host operating system
         shell: bash
         working-directory: ${{runner.workspace}}/OpenFPGA/build
-        # Note the current convention is to use the -S and -B options here to specify source 
-        # and build directories, but this is only available with CMake 3.13 and higher.  
+        # Note the current convention is to use the -S and -B options here to specify source
+        # and build directories, but this is only available with CMake 3.13 and higher.
         # The CMake binaries on the Github Actions machines are (as of this writing) 3.12
         run: |
           export CC=${{ matrix.config.cc }}
@@ -83,10 +84,10 @@ jobs:
         shell: bash
         # Execute the build.  You can specify a specific target with "--target <NAME>"
         run: |
-          cmake --build . --config $BUILD_TYPE 
+          cmake --build . --config $BUILD_TYPE
 
       - name: ${{matrix.config.name}}
         if: contains(matrix.config.name, 'Quick Test')
         shell: bash
-        # Execute the test. 
+        # Execute the test.
         run: source ./.github/workflows/${{matrix.config.reg_script}}

.github/workflows/install_dependency.sh

@@ -28,6 +28,8 @@ sudo apt-get install perl
 sudo apt-get install python
 sudo apt-get install python3-setuptools
 sudo apt-get install python-lxml
+sudo apt-get install tcllib
+sudo apt-get install tcl8.6-dev
 sudo apt-get install texinfo
 sudo apt-get install time
 sudo apt-get install valgrind
@@ -48,4 +50,4 @@ sudo apt-get install gcc-9
 sudo apt-get install clang-6.0
 sudo apt-get install clang-8
 # Python dependencies
-python3 -m pip install -r /home/runner/work/SOFA/SOFA/OpenFPGA/requirements.txt
+python3 -m pip install -r /home/runner/work/SOFA/SOFA/OpenFPGA/requirements.txt

.github/workflows/perform_precheck.sh

@@ -44,8 +44,7 @@ mv ./gds/caravel_merged.gds ./gds/caravel.gds
 # rm -f gds/caravel.old.gds
 
 # = = = = = = = = = = = = = Perform Open MPW Checks = = = = = = = = = = = = = =
-if [[ ! -n "$SKIP_PRECHECK" ]]; then
-    echo $SKIP_PRECHECK
+if [[ "$SKIP_PRECHECK" != 1 ]]; then
     echo "[Info] Running MPW Prechecker"
     cd /usr/local/bin
     python3 open_mpw_prechecker.py \

.github/workflows/sync_repo.sh

@@ -5,10 +5,13 @@
 # Working directory in github workspace
 # Original repo is places SOFA-Chips
 # for conditional file copy use PROJ_SUFFIX (example SOFA_HD)
-
-tail -n +2 ./SOFA-Chips/SynRepoConfig/sync_files.csv | while  IFS=, read -r srcLoc dstLoc; do
-    Copying "./SOFA-Chips/$srcLoc --> ${DEST_DIR}/$dstLoc"
-    rsync -avp ./SOFA-Chips/$srcLoc ${DEST_DIR}/$dstLoc
+COPY_FILE="./SOFA-Chips/SynRepoConfig/sync_files_${PROJ_SUFFIX,,}.csv"
+echo "[Info] Using file for rsync $COPY_FILE"
+tail -n +2 $COPY_FILE | while  IFS=, read -r srcLoc dstLoc; do
+    srcLoc=$(echo $(eval "echo $srcLoc"))
+    dstLoc=$(echo $(eval "echo $dstLoc"))
+    echo "Copying ./SOFA-Chips/$srcLoc --> ${DEST_DIR}/$dstLoc"
+    rsync -ap ./SOFA-Chips/$srcLoc ${DEST_DIR}/$dstLoc
 done
 
 cd ${DEST_DIR}

FPGA1212_SOFA_HD_PNR/README.md

@@ -0,0 +1,5 @@
+FPGA1212_FLAT_HD_SKY_PNR
+====================
+
+12x12 FPGA designed using hierarchical flow and `SKY130_FD_SC_HD`.
+Flat Module design style

SynRepoConfig/sync_files.csv

@@ -1,2 +0,0 @@
-SrcLoc, DestLoc
-FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_task/,OpenFPGA_task

SynRepoConfig/sync_files_qlsofa_hd.csv

@@ -0,0 +1,4 @@
+SrcLoc, DestLoc
+FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_task/,OpenFPGA_task
+FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_Verilog/SRC/,verilog/OpenFPGA_Verilog/
+FPGA1212_QLSOFA_HD_PNR/fpga_top/fpga_top*.pt.v,verilog/gl/caravel_${PROJ_SUFFIX,,}_top.v

SynRepoConfig/sync_files_sofa_chd.csv

@@ -0,0 +1,4 @@
+SrcLoc, DestLoc
+FPGA1212_SOFA_CHD_PNR/FPGA1212_SOFA_CHD_task/,OpenFPGA_task
+FPGA1212_SOFA_CHD_PNR/FPGA1212_SOFA_CHD_Verilog/SRC/,verilog/OpenFPGA_Verilog/
+FPGA1212_SOFA_CHD_PNR/fpga_top/fpga_top*.pt.v,verilog/gl/caravel_${PROJ_SUFFIX,,}_top.v

SynRepoConfig/sync_files_sofa_hd.csv

@@ -0,0 +1,4 @@
+SrcLoc, DestLoc
+FPGA1212_SOFA_HD_PNR/FPGA1212_SOFA_HD_task/,OpenFPGA_task
+FPGA1212_SOFA_HD_PNR/FPGA1212_SOFA_HD_Verilog/SRC/,verilog/OpenFPGA_Verilog/
+FPGA1212_SOFA_HD_PNR/fpga_top/fpga_top*.pt.v,verilog/gl/caravel_${PROJ_SUFFIX,,}_top.v