[Cleanup] Renamed projects to SOFA-HD and QLSOFA-HD

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Ganesh Gore 2020-12-14 00:45:11 -07:00

parent 9f9897c5e2

commit fa87753d62

335 changed files with 0 additions and 75238 deletions

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33666

FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/SRC/top_top_formal_verification.v

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FPGA1212_RESET_HD_SKY_PNR/FPGA1212_RESET_HD_SKY_Verilog/OpenFPGAEngine.info → FPGA1212_QLSOFA_HD_PNR/FPGA1212_RESET_HD_SKY_Verilog/OpenFPGAEngine.info

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FPGA1212_RESET_HD_SKY_PNR/FPGA1212_RESET_HD_SKY_Verilog/SDC/disable_configure_ports.sdc → FPGA1212_QLSOFA_HD_PNR/FPGA1212_RESET_HD_SKY_Verilog/SDC/disable_configure_ports.sdc

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FPGA1212_RESET_HD_SKY_PNR/FPGA1212_RESET_HD_SKY_Verilog/SRC/InstancesMap.txt → FPGA1212_QLSOFA_HD_PNR/FPGA1212_RESET_HD_SKY_Verilog/SRC/InstancesMap.txt

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FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/SRC/define_simulation.v → FPGA1212_QLSOFA_HD_PNR/FPGA1212_RESET_HD_SKY_Verilog/SRC/define_simulation.v

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FPGA1212_RESET_HD_SKY_PNR/FPGA1212_RESET_HD_SKY_Verilog/SRC/fabric_netlists.v → FPGA1212_QLSOFA_HD_PNR/FPGA1212_RESET_HD_SKY_Verilog/SRC/fabric_netlists.v

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FPGA1212_RESET_HD_SKY_PNR/FPGA1212_RESET_HD_SKY_Verilog/SRC/fpga_core.v → FPGA1212_QLSOFA_HD_PNR/FPGA1212_RESET_HD_SKY_Verilog/SRC/fpga_core.v

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FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/SRC/fpga_defines.v → FPGA1212_QLSOFA_HD_PNR/FPGA1212_RESET_HD_SKY_Verilog/SRC/fpga_defines.v

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FPGA1212_RESET_HD_SKY_PNR/FPGA1212_RESET_HD_SKY_Verilog/SRC/fpga_top.v → FPGA1212_QLSOFA_HD_PNR/FPGA1212_RESET_HD_SKY_Verilog/SRC/fpga_top.v

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FPGA1212_RESET_HD_SKY_PNR/FPGA1212_RESET_HD_SKY_Verilog/SRC/lb/grid_clb.v → FPGA1212_QLSOFA_HD_PNR/FPGA1212_RESET_HD_SKY_Verilog/SRC/lb/grid_clb.v

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FPGA1212_RESET_HD_SKY_PNR/FPGA1212_RESET_HD_SKY_Verilog/SRC/lb/logical_tile_clb_mode_clb_.v → FPGA1212_QLSOFA_HD_PNR/FPGA1212_RESET_HD_SKY_Verilog/SRC/lb/logical_tile_clb_mode_clb_.v

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FPGA1212_RESET_HD_SKY_PNR/FPGA1212_RESET_HD_SKY_Verilog/SRC/lb/logical_tile_clb_mode_default__fle.v → FPGA1212_QLSOFA_HD_PNR/FPGA1212_RESET_HD_SKY_Verilog/SRC/lb/logical_tile_clb_mode_default__fle.v

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FPGA1212_RESET_HD_SKY_PNR/FPGA1212_RESET_HD_SKY_Verilog/SRC/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric.v → FPGA1212_QLSOFA_HD_PNR/FPGA1212_RESET_HD_SKY_Verilog/SRC/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric.v

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FPGA1212_RESET_HD_SKY_PNR/FPGA1212_RESET_HD_SKY_Verilog/SRC/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff.v → FPGA1212_QLSOFA_HD_PNR/FPGA1212_RESET_HD_SKY_Verilog/SRC/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff.v

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FPGA1212_RESET_HD_SKY_PNR/FPGA1212_RESET_HD_SKY_Verilog/SRC/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic.v → FPGA1212_QLSOFA_HD_PNR/FPGA1212_RESET_HD_SKY_Verilog/SRC/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic.v

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FPGA1212_RESET_HD_SKY_PNR/FPGA1212_RESET_HD_SKY_Verilog/SRC/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower.v → FPGA1212_QLSOFA_HD_PNR/FPGA1212_RESET_HD_SKY_Verilog/SRC/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower.v

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FPGA1212_RESET_HD_SKY_PNR/FPGA1212_RESET_HD_SKY_Verilog/SRC/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4.v → FPGA1212_QLSOFA_HD_PNR/FPGA1212_RESET_HD_SKY_Verilog/SRC/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4.v

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FPGA1212_RESET_HD_SKY_PNR/FPGA1212_RESET_HD_SKY_Verilog/SRC/lb/logical_tile_io_mode_io_.v → FPGA1212_QLSOFA_HD_PNR/FPGA1212_RESET_HD_SKY_Verilog/SRC/lb/logical_tile_io_mode_io_.v

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FPGA1212_RESET_HD_SKY_PNR/FPGA1212_RESET_HD_SKY_Verilog/SRC/lb/logical_tile_io_mode_physical__iopad.v → FPGA1212_QLSOFA_HD_PNR/FPGA1212_RESET_HD_SKY_Verilog/SRC/lb/logical_tile_io_mode_physical__iopad.v

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FPGA1212_RESET_HD_SKY_PNR/FPGA1212_RESET_HD_SKY_Verilog/SRC/routing/cbx_1__0_.v → FPGA1212_QLSOFA_HD_PNR/FPGA1212_RESET_HD_SKY_Verilog/SRC/routing/cbx_1__0_.v

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FPGA1212_RESET_HD_SKY_PNR/FPGA1212_RESET_HD_SKY_Verilog/SRC/routing/cbx_1__1_.v → FPGA1212_QLSOFA_HD_PNR/FPGA1212_RESET_HD_SKY_Verilog/SRC/routing/cbx_1__1_.v

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FPGA1212_RESET_HD_SKY_PNR/FPGA1212_RESET_HD_SKY_Verilog/SRC/routing/cbx_1__2_.v → FPGA1212_QLSOFA_HD_PNR/FPGA1212_RESET_HD_SKY_Verilog/SRC/routing/cbx_1__2_.v

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FPGA1212_RESET_HD_SKY_PNR/FPGA1212_RESET_HD_SKY_Verilog/SRC/routing/cby_0__1_.v → FPGA1212_QLSOFA_HD_PNR/FPGA1212_RESET_HD_SKY_Verilog/SRC/routing/cby_0__1_.v

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FPGA1212_RESET_HD_SKY_PNR/FPGA1212_RESET_HD_SKY_Verilog/SRC/routing/cby_1__1_.v → FPGA1212_QLSOFA_HD_PNR/FPGA1212_RESET_HD_SKY_Verilog/SRC/routing/cby_1__1_.v

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FPGA1212_RESET_HD_SKY_PNR/FPGA1212_RESET_HD_SKY_Verilog/SRC/routing/cby_2__1_.v → FPGA1212_QLSOFA_HD_PNR/FPGA1212_RESET_HD_SKY_Verilog/SRC/routing/cby_2__1_.v

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FPGA1212_RESET_HD_SKY_PNR/FPGA1212_RESET_HD_SKY_Verilog/SRC/routing/sb_0__0_.v → FPGA1212_QLSOFA_HD_PNR/FPGA1212_RESET_HD_SKY_Verilog/SRC/routing/sb_0__0_.v

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FPGA1212_RESET_HD_SKY_PNR/FPGA1212_RESET_HD_SKY_Verilog/SRC/routing/sb_0__1_.v → FPGA1212_QLSOFA_HD_PNR/FPGA1212_RESET_HD_SKY_Verilog/SRC/routing/sb_0__1_.v

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FPGA1212_RESET_HD_SKY_PNR/FPGA1212_RESET_HD_SKY_Verilog/SRC/routing/sb_0__2_.v → FPGA1212_QLSOFA_HD_PNR/FPGA1212_RESET_HD_SKY_Verilog/SRC/routing/sb_0__2_.v

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FPGA1212_RESET_HD_SKY_PNR/FPGA1212_RESET_HD_SKY_Verilog/SRC/routing/sb_1__0_.v → FPGA1212_QLSOFA_HD_PNR/FPGA1212_RESET_HD_SKY_Verilog/SRC/routing/sb_1__0_.v

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FPGA1212_RESET_HD_SKY_PNR/FPGA1212_RESET_HD_SKY_Verilog/SRC/routing/sb_1__1_.v → FPGA1212_QLSOFA_HD_PNR/FPGA1212_RESET_HD_SKY_Verilog/SRC/routing/sb_1__1_.v

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FPGA1212_RESET_HD_SKY_PNR/FPGA1212_RESET_HD_SKY_Verilog/SRC/routing/sb_1__2_.v → FPGA1212_QLSOFA_HD_PNR/FPGA1212_RESET_HD_SKY_Verilog/SRC/routing/sb_1__2_.v

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FPGA1212_RESET_HD_SKY_PNR/FPGA1212_RESET_HD_SKY_Verilog/SRC/routing/sb_2__0_.v → FPGA1212_QLSOFA_HD_PNR/FPGA1212_RESET_HD_SKY_Verilog/SRC/routing/sb_2__0_.v

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FPGA1212_RESET_HD_SKY_PNR/FPGA1212_RESET_HD_SKY_Verilog/SRC/routing/sb_2__1_.v → FPGA1212_QLSOFA_HD_PNR/FPGA1212_RESET_HD_SKY_Verilog/SRC/routing/sb_2__1_.v

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FPGA1212_RESET_HD_SKY_PNR/FPGA1212_RESET_HD_SKY_Verilog/SRC/routing/sb_2__2_.v → FPGA1212_QLSOFA_HD_PNR/FPGA1212_RESET_HD_SKY_Verilog/SRC/routing/sb_2__2_.v

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FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/SRC/sub_module/arch_encoder.v → FPGA1212_QLSOFA_HD_PNR/FPGA1212_RESET_HD_SKY_Verilog/SRC/sub_module/arch_encoder.v

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FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/SRC/sub_module/digital_io_hd.v → FPGA1212_QLSOFA_HD_PNR/FPGA1212_RESET_HD_SKY_Verilog/SRC/sub_module/digital_io_hd.v

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FPGA1212_RESET_HD_SKY_PNR/FPGA1212_RESET_HD_SKY_Verilog/SRC/sub_module/fpga_top.v → FPGA1212_QLSOFA_HD_PNR/FPGA1212_RESET_HD_SKY_Verilog/SRC/sub_module/fpga_top.v

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FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/SRC/sub_module/inv_buf_passgate.v → FPGA1212_QLSOFA_HD_PNR/FPGA1212_RESET_HD_SKY_Verilog/SRC/sub_module/inv_buf_passgate.v

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FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/SRC/sub_module/local_encoder.v → FPGA1212_QLSOFA_HD_PNR/FPGA1212_RESET_HD_SKY_Verilog/SRC/sub_module/local_encoder.v

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FPGA1212_RESET_HD_SKY_PNR/FPGA1212_RESET_HD_SKY_Verilog/SRC/sub_module/luts.v → FPGA1212_QLSOFA_HD_PNR/FPGA1212_RESET_HD_SKY_Verilog/SRC/sub_module/luts.v

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FPGA1212_RESET_HD_SKY_PNR/FPGA1212_RESET_HD_SKY_Verilog/SRC/sub_module/memories.v → FPGA1212_QLSOFA_HD_PNR/FPGA1212_RESET_HD_SKY_Verilog/SRC/sub_module/memories.v

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FPGA1212_RESET_HD_SKY_PNR/FPGA1212_RESET_HD_SKY_Verilog/SRC/sub_module/muxes.v → FPGA1212_QLSOFA_HD_PNR/FPGA1212_RESET_HD_SKY_Verilog/SRC/sub_module/muxes.v

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FPGA1212_RESET_HD_SKY_PNR/FPGA1212_RESET_HD_SKY_Verilog/SRC/sub_module/sky130_fd_sc_hd_wrapper .v → FPGA1212_QLSOFA_HD_PNR/FPGA1212_RESET_HD_SKY_Verilog/SRC/sub_module/sky130_fd_sc_hd_wrapper .v

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FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/SRC/sub_module/wires.v → FPGA1212_QLSOFA_HD_PNR/FPGA1212_RESET_HD_SKY_Verilog/SRC/sub_module/wires.v

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FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/SRC/top_include_netlists.v → FPGA1212_QLSOFA_HD_PNR/FPGA1212_RESET_HD_SKY_Verilog/SRC/top_include_netlists.v

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FPGA1212_RESET_HD_SKY_PNR/FPGA1212_RESET_HD_SKY_Verilog/TESTBENCH/top/fabric_bitstream.bit → FPGA1212_QLSOFA_HD_PNR/FPGA1212_RESET_HD_SKY_Verilog/TESTBENCH/top/fabric_bitstream.bit

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FPGA1212_RESET_HD_SKY_PNR/FPGA1212_RESET_HD_SKY_Verilog/TESTBENCH/top/fabric_bitstream.xml → FPGA1212_QLSOFA_HD_PNR/FPGA1212_RESET_HD_SKY_Verilog/TESTBENCH/top/fabric_bitstream.xml

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FPGA1212_RESET_HD_SKY_PNR/FPGA1212_RESET_HD_SKY_Verilog/TESTBENCH/top/fabric_indepenent_bitstream.xml → FPGA1212_QLSOFA_HD_PNR/FPGA1212_RESET_HD_SKY_Verilog/TESTBENCH/top/fabric_indepenent_bitstream.xml

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FPGA1212_RESET_HD_SKY_PNR/FPGA1212_RESET_HD_SKY_Verilog/Testbench_Case/case_top.tcl → FPGA1212_QLSOFA_HD_PNR/FPGA1212_RESET_HD_SKY_Verilog/Testbench_Case/case_top.tcl

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FPGA1212_RESET_HD_SKY_PNR/FPGA1212_RESET_HD_SKY_Verilog/openfpgashell.log → FPGA1212_QLSOFA_HD_PNR/FPGA1212_RESET_HD_SKY_Verilog/openfpgashell.log

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FPGA1212_RESET_HD_SKY_PNR/FPGA1212_RESET_HD_SKY_Verilog/proj_const.tcl → FPGA1212_QLSOFA_HD_PNR/FPGA1212_RESET_HD_SKY_Verilog/proj_const.tcl

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FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/scandef/cbx_1__0__scandef.def → FPGA1212_QLSOFA_HD_PNR/FPGA1212_RESET_HD_SKY_Verilog/scandef/cbx_1__0__scandef.def

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FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/scandef/cbx_1__1__scandef.def → FPGA1212_QLSOFA_HD_PNR/FPGA1212_RESET_HD_SKY_Verilog/scandef/cbx_1__1__scandef.def

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FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/scandef/cbx_1__2__scandef.def → FPGA1212_QLSOFA_HD_PNR/FPGA1212_RESET_HD_SKY_Verilog/scandef/cbx_1__2__scandef.def

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FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/scandef/cby_0__1__scandef.def → FPGA1212_QLSOFA_HD_PNR/FPGA1212_RESET_HD_SKY_Verilog/scandef/cby_0__1__scandef.def

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FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/scandef/cby_1__1__scandef.def → FPGA1212_QLSOFA_HD_PNR/FPGA1212_RESET_HD_SKY_Verilog/scandef/cby_1__1__scandef.def

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FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_Verilog/scandef/cby_2__1__scandef.def → FPGA1212_QLSOFA_HD_PNR/FPGA1212_RESET_HD_SKY_Verilog/scandef/cby_2__1__scandef.def

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FPGA1212_RESET_HD_SKY_PNR/FPGA1212_RESET_HD_SKY_Verilog/scandef/grid_clb_scandef.def → FPGA1212_QLSOFA_HD_PNR/FPGA1212_RESET_HD_SKY_Verilog/scandef/grid_clb_scandef.def

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FPGA1212_RESET_HD_SKY_PNR/FPGA1212_RESET_HD_SKY_Verilog/scandef/sb_0__0__scandef.def → FPGA1212_QLSOFA_HD_PNR/FPGA1212_RESET_HD_SKY_Verilog/scandef/sb_0__0__scandef.def

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FPGA1212_RESET_HD_SKY_PNR/FPGA1212_RESET_HD_SKY_Verilog/scandef/sb_0__1__scandef.def → FPGA1212_QLSOFA_HD_PNR/FPGA1212_RESET_HD_SKY_Verilog/scandef/sb_0__1__scandef.def

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FPGA1212_RESET_HD_SKY_PNR/FPGA1212_RESET_HD_SKY_Verilog/scandef/sb_0__2__scandef.def → FPGA1212_QLSOFA_HD_PNR/FPGA1212_RESET_HD_SKY_Verilog/scandef/sb_0__2__scandef.def

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FPGA1212_RESET_HD_SKY_PNR/FPGA1212_RESET_HD_SKY_Verilog/scandef/sb_1__0__scandef.def → FPGA1212_QLSOFA_HD_PNR/FPGA1212_RESET_HD_SKY_Verilog/scandef/sb_1__0__scandef.def

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FPGA1212_RESET_HD_SKY_PNR/FPGA1212_RESET_HD_SKY_Verilog/scandef/sb_1__1__scandef.def → FPGA1212_QLSOFA_HD_PNR/FPGA1212_RESET_HD_SKY_Verilog/scandef/sb_1__1__scandef.def

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FPGA1212_RESET_HD_SKY_PNR/FPGA1212_RESET_HD_SKY_Verilog/scandef/sb_1__2__scandef.def → FPGA1212_QLSOFA_HD_PNR/FPGA1212_RESET_HD_SKY_Verilog/scandef/sb_1__2__scandef.def

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FPGA1212_RESET_HD_SKY_PNR/FPGA1212_RESET_HD_SKY_Verilog/scandef/sb_2__0__scandef.def → FPGA1212_QLSOFA_HD_PNR/FPGA1212_RESET_HD_SKY_Verilog/scandef/sb_2__0__scandef.def

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FPGA1212_RESET_HD_SKY_PNR/FPGA1212_RESET_HD_SKY_Verilog/scandef/sb_2__1__scandef.def → FPGA1212_QLSOFA_HD_PNR/FPGA1212_RESET_HD_SKY_Verilog/scandef/sb_2__1__scandef.def

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FPGA1212_RESET_HD_SKY_PNR/FPGA1212_RESET_HD_SKY_Verilog/scandef/sb_2__2__scandef.def → FPGA1212_QLSOFA_HD_PNR/FPGA1212_RESET_HD_SKY_Verilog/scandef/sb_2__2__scandef.def

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FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_task/arch/fabric_key.xml → FPGA1212_QLSOFA_HD_PNR/FPGA1212_RESET_HD_SKY_task/arch/fabric_key.xml

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FPGA1212_RESET_HD_SKY_PNR/FPGA1212_RESET_HD_SKY_task/arch/openfpga_arch.xml → FPGA1212_QLSOFA_HD_PNR/FPGA1212_RESET_HD_SKY_task/arch/openfpga_arch.xml

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FPGA1212_RESET_HD_SKY_PNR/FPGA1212_RESET_HD_SKY_task/arch/vpr_arch.xml → FPGA1212_QLSOFA_HD_PNR/FPGA1212_RESET_HD_SKY_task/arch/vpr_arch.xml

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FPGA1212_RESET_HD_SKY_PNR/FPGA1212_RESET_HD_SKY_task/config/task.conf → FPGA1212_QLSOFA_HD_PNR/FPGA1212_RESET_HD_SKY_task/config/task.conf

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FPGA1212_RESET_HD_SKY_PNR/FPGA1212_RESET_HD_SKY_task/config/task_generation.conf → FPGA1212_QLSOFA_HD_PNR/FPGA1212_RESET_HD_SKY_task/config/task_generation.conf

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FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_task/config/task_simulation.conf → FPGA1212_QLSOFA_HD_PNR/FPGA1212_RESET_HD_SKY_task/config/task_simulation.conf

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FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_task/design_variables.yml → FPGA1212_QLSOFA_HD_PNR/FPGA1212_RESET_HD_SKY_task/design_variables.yml

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FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_task/generate_fabric.openfpga → FPGA1212_QLSOFA_HD_PNR/FPGA1212_RESET_HD_SKY_task/generate_fabric.openfpga

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FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_task/generate_testbench.openfpga → FPGA1212_QLSOFA_HD_PNR/FPGA1212_RESET_HD_SKY_task/generate_testbench.openfpga

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FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_task/micro_benchmark/and.act → FPGA1212_QLSOFA_HD_PNR/FPGA1212_RESET_HD_SKY_task/micro_benchmark/and.act

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FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_task/micro_benchmark/and.blif → FPGA1212_QLSOFA_HD_PNR/FPGA1212_RESET_HD_SKY_task/micro_benchmark/and.blif

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FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_task/micro_benchmark/and.v → FPGA1212_QLSOFA_HD_PNR/FPGA1212_RESET_HD_SKY_task/micro_benchmark/and.v

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FPGA1212_FLAT_HD_SKY_PNR/FPGA1212_FLAT_HD_SKY_task/process_top_def.sh → FPGA1212_QLSOFA_HD_PNR/FPGA1212_RESET_HD_SKY_task/process_top_def.sh

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