tangxifan
|
7649d9228e
|
fixed bugs in refactored bitstream generation
|
2019-10-26 16:40:14 -06:00 |
|
tangxifan
|
0a9c89be0b
|
add bitstream writers and start debugging
|
2019-10-26 12:41:23 -06:00 |
|
tangxifan
|
3310bac65b
|
refactored grid bitstream generation
|
2019-10-25 21:49:47 -06:00 |
|
tangxifan
|
4b7a9dfa63
|
add instance name correlation between module and bitstream generation
|
2019-10-25 13:06:48 -06:00 |
|
tangxifan
|
0b687669c8
|
affliate configuration bitstream to sb blocks
|
2019-10-25 10:42:12 -06:00 |
|
tangxifan
|
c38513c838
|
add local encoder support in bitstream generation refactoring
|
2019-10-24 22:49:24 -06:00 |
|
tangxifan
|
97193794c4
|
correct bugs in organizing child modules in top-level module
|
2019-10-24 21:27:42 -06:00 |
|
tangxifan
|
838173f3c4
|
start refactoring bitstream generator
|
2019-10-24 21:01:11 -06:00 |
|
tangxifan
|
13c62fdcf8
|
add more methods to bitstream manager (renamed from bitstream context)
|
2019-10-24 15:43:29 -06:00 |
|
tangxifan
|
f26dbfe080
|
add instance name for top-level modules to ease readability
|
2019-10-23 20:24:52 -06:00 |
|
tangxifan
|
2787a07f0d
|
start refactoring bitstream generation
|
2019-10-23 17:34:21 -06:00 |
|
tangxifan
|
a18f1305cd
|
add configurable child list to module manager
|
2019-10-23 15:44:13 -06:00 |
|
tangxifan
|
12162a02bc
|
critical bug fixing for compact routing hierarchy and top module generation
|
2019-10-23 14:20:04 -06:00 |
|
tangxifan
|
fb2f003d5b
|
add top module generation and refactored verilog generation for top module
|
2019-10-23 12:16:58 -06:00 |
|
tangxifan
|
dafab3907e
|
refactored routing module generation and verilog writing
|
2019-10-23 11:46:55 -06:00 |
|
tangxifan
|
89c8d089a3
|
add grid module generation
|
2019-10-22 16:14:11 -06:00 |
|
tangxifan
|
9cf8683acd
|
add module generation for memories
|
2019-10-22 15:31:08 -06:00 |
|
tangxifan
|
3cf7950bc1
|
add wire module generation and simplify Verilog generation for wires
|
2019-10-21 20:20:34 -06:00 |
|
tangxifan
|
c076da9bab
|
remove redundant codes
|
2019-10-21 18:48:34 -06:00 |
|
tangxifan
|
81093f0db6
|
add lut module generation and simplify Verilog generation codes
|
2019-10-21 17:54:15 -06:00 |
|
tangxifan
|
f002f7e30f
|
add const 0 and 1 module Verilog generation
|
2019-10-21 14:17:09 -06:00 |
|
tangxifan
|
bd37f0d542
|
correct bugs in decoder data port alignment to memory ports of multiplexing structure
|
2019-10-21 13:16:15 -06:00 |
|
tangxifan
|
fe433f3e50
|
bug fixed for local encoders and module nets creation
|
2019-10-21 12:23:00 -06:00 |
|
tangxifan
|
b2f57ecf81
|
plug in MUX module graph generation, still local encoders contain dangling net, bug fixing
|
2019-10-21 00:00:30 -06:00 |
|
tangxifan
|
520e145af2
|
move mux_lib to fpga_x2p_setup
|
2019-10-19 19:13:52 -06:00 |
|
tangxifan
|
04f0fbebf7
|
plug in module graph to feed verilog writers
|
2019-10-18 21:59:22 -06:00 |
|
tangxifan
|
b1cafcdbde
|
add missing files
|
2019-10-18 21:04:35 -06:00 |
|
tangxifan
|
fbe56a06c4
|
add decoder module builders
|
2019-10-18 21:01:10 -06:00 |
|
tangxifan
|
7c1bce4b59
|
add module builders for essential gates
|
2019-10-18 20:41:05 -06:00 |
|
tangxifan
|
3b82d62d03
|
start developing module graph builders
|
2019-10-18 20:02:02 -06:00 |
|
tangxifan
|
db38f21412
|
add netlist manager class
|
2019-10-18 17:59:03 -06:00 |
|
tangxifan
|
8c1158fc5c
|
refactor memory organization at the top-level module
|
2019-10-18 15:33:25 -06:00 |
|
tangxifan
|
cfec8d70ab
|
improved refactoring on clb2clb connection by considering flexible arch
|
2019-10-18 11:20:09 -06:00 |
|
tangxifan
|
4171a674b1
|
refactored clb2clb direct connects for cross-column/row
|
2019-10-17 23:06:59 -06:00 |
|
tangxifan
|
190449c06f
|
refactoring top-level module with clb2clb direct connection
|
2019-10-17 17:29:04 -06:00 |
|
tangxifan
|
945e138e62
|
debugged the gsb-grid connection in top module.
|
2019-10-15 22:02:25 -06:00 |
|
tangxifan
|
c9d8311a93
|
bug fixing for grid-gsb connections in top module when using compact routing
|
2019-10-15 18:00:55 -06:00 |
|
tangxifan
|
6a13120208
|
rename grid modules to be clear
|
2019-10-15 16:28:46 -06:00 |
|
tangxifan
|
071757dc52
|
add module nets to connect grids and sbs
|
2019-10-15 16:08:51 -06:00 |
|
tangxifan
|
4b56b755f2
|
refactored instanciation of routing modules in top module
|
2019-10-14 21:06:10 -06:00 |
|
tangxifan
|
bd6a0c6a55
|
refactored grid instance addition to top module
|
2019-10-14 17:47:10 -06:00 |
|
tangxifan
|
f779ad7ecf
|
bug fixing for global and gpio port wiring; start refactoring top-level module
|
2019-10-14 15:53:04 -06:00 |
|
tangxifan
|
6793c67c8d
|
refactored pb_type and grid Verilog generation
|
2019-10-13 21:07:30 -06:00 |
|
tangxifan
|
b581399761
|
add memory ports and nets to intermediate pb_types
|
2019-10-13 17:45:32 -06:00 |
|
tangxifan
|
cab4bd6807
|
add gpio ports to pb_type modules
|
2019-10-13 16:23:22 -06:00 |
|
tangxifan
|
0f50251b3b
|
add mux and associated memory modules in refactoring Verilog generation for pb_types
|
2019-10-13 11:11:19 -06:00 |
|
tangxifan
|
85644d07ae
|
refactoring pb interc Verilog generation
|
2019-10-12 21:55:53 -06:00 |
|
tangxifan
|
d1948c82eb
|
Refactoring Verilog generation intermediate level of pb_types and SRAM port generation
|
2019-10-11 21:43:47 -06:00 |
|
tangxifan
|
b3ca0d32a4
|
remove configuration bus naming dependency on SRAM circuit models
|
2019-10-11 19:47:36 -06:00 |
|
tangxifan
|
73a5977e0d
|
Debugged Verilog generation for primitive pb_types
|
2019-10-11 18:00:37 -06:00 |
|
tangxifan
|
50f7d1eae3
|
bug fixing in Verilog port merging and instanciation
|
2019-10-11 14:20:04 -06:00 |
|
tangxifan
|
663b1b7665
|
refactorint net addition for configuration signals in module graph
|
2019-10-11 13:07:14 -06:00 |
|
tangxifan
|
c9950162d1
|
start plug in new Verilog writer. Start debugging
|
2019-10-10 22:02:46 -06:00 |
|
tangxifan
|
1f650aac73
|
add local direct connection Verilog code generation
|
2019-10-10 20:54:31 -06:00 |
|
tangxifan
|
f2b3341d87
|
developing verilog writer for generic module graph
|
2019-10-10 20:09:55 -06:00 |
|
tangxifan
|
e5956467fd
|
developing verilog writer for modules
|
2019-10-10 14:43:32 -06:00 |
|
tangxifan
|
edad988ebb
|
add net accessor and mutators to module manager
|
2019-10-09 21:14:30 -06:00 |
|
tangxifan
|
557d8b60f3
|
start implementing module graph-based connection
|
2019-10-09 20:30:16 -06:00 |
|
tangxifan
|
9cb6e64ab3
|
refactoring instanciation inside primitive pb_type Verilog module
|
2019-10-08 21:29:42 -06:00 |
|
tangxifan
|
6f42aac626
|
add wire connection in Verilog module declaration
|
2019-10-08 20:14:38 -06:00 |
|
tangxifan
|
6bed89c237
|
refactored counting config bits for circuit model and update Verilog generation for primitive pb_types
|
2019-10-08 18:00:04 -06:00 |
|
tangxifan
|
ea2942640e
|
refactored port addition for pb_types in Verilog generation
|
2019-10-08 14:03:17 -06:00 |
|
tangxifan
|
512e9f4e8e
|
refactoring Verilog generation for primitive pb_types
|
2019-10-08 12:10:26 -06:00 |
|
tangxifan
|
173b886314
|
add module name generation for pb_types
|
2019-10-07 21:09:54 -06:00 |
|
tangxifan
|
86c9af872e
|
refactoring physical block Verilog generation
|
2019-10-07 17:39:00 -06:00 |
|
tangxifan
|
997bfdbb95
|
move the refactored function for physical block Verilog generation to a new source file
|
2019-10-07 16:03:15 -06:00 |
|
tangxifan
|
3ca6f08aa4
|
start refactoring physical block Verilog generation
|
2019-10-06 19:27:55 -06:00 |
|
tangxifan
|
1e183e7885
|
refactored shared config bits calculation
|
2019-10-06 16:57:53 -06:00 |
|
tangxifan
|
393f0b0ac3
|
align formal verification port inside refactored routing blocks
|
2019-10-05 21:16:48 -06:00 |
|
tangxifan
|
86387ff79c
|
Merge branch 'refactoring' into dev
|
2019-10-05 18:15:31 -06:00 |
|
tangxifan
|
c920047ee8
|
refactored Verilog generation for connection blocks
|
2019-10-05 18:14:23 -06:00 |
|
tangxifan
|
2d7e8d9811
|
add check codes for memory buses
|
2019-10-05 11:07:26 -06:00 |
|
tangxifan
|
6b301d9f44
|
Merge branch 'dev' into refactoring
|
2019-10-04 22:47:29 -06:00 |
|
tangxifan
|
b905c0c68c
|
refactored memory module Verilog generation for scan-chains
|
2019-10-04 22:45:45 -06:00 |
AurelienUoU
|
7aa24f407e
|
Fix explicit port name in CBs
|
2019-10-04 11:20:46 -06:00 |
Baudouin Chauviere
|
6f7023658e
|
Revert "Correction on the cb vs sb corrdinator. Does not fix the problem though"
This reverts commit 95596bb4f8.
|
2019-10-03 14:59:04 -06:00 |
|
Baudouin Chauviere
|
95596bb4f8
|
Correction on the cb vs sb corrdinator. Does not fix the problem though
|
2019-10-03 13:50:01 -06:00 |
|
Baudouin Chauviere
|
01ff484158
|
Explicit verilog passing all tests
|
2019-10-02 10:22:28 -06:00 |
|
Baudouin Chauviere
|
6b3e1fd410
|
Get backup verilog_routing.c
|
2019-10-02 08:54:56 -06:00 |
|
Baudouin Chauviere
|
33e50bbc8c
|
fix
|
2019-10-01 16:54:16 -06:00 |
|
Baudouin Chauviere
|
7c3ab38410
|
Hot fix
|
2019-10-01 16:40:16 -06:00 |
|
Baudouin Chauviere
|
633a12ee08
|
Buggy version but need help on debugging
|
2019-10-01 14:49:42 -06:00 |
|
tangxifan
|
b082e60c10
|
start refactoring instanciation of memory modules
|
2019-09-29 18:20:56 -06:00 |
|
tangxifan
|
3726e691f4
|
simplify the local wire generation for ccffs
|
2019-09-28 21:36:56 -06:00 |
|
tangxifan
|
1983e56557
|
make local configuration bus generation more general
|
2019-09-28 21:02:14 -06:00 |
Ganesh Gore
|
069f628bb0
|
Merge branch 'dev' of github.com:LNIS-Projects/OpenFPGA into ganesh_dev
|
2019-09-28 11:21:37 -06:00 |
|
tangxifan
|
433fc73460
|
refactored local encoder support for Verilog MUX generation
|
2019-09-27 23:10:43 -06:00 |
|
tangxifan
|
4da5035627
|
Connect CCFFs in a chain in a Verilog module
|
2019-09-27 20:50:12 -06:00 |
|
tangxifan
|
f0949fea2f
|
Merge branch 'dev' into refactoring
|
2019-09-27 18:09:58 -06:00 |
|
tangxifan
|
1e187f3d15
|
start adding memory circuit to Switch blocks
|
2019-09-27 18:08:37 -06:00 |
|
AurelienUoU
|
640922accd
|
Merge remote-tracking branch 'origin/dev' into heterogeneous
|
2019-09-27 16:54:13 -06:00 |
|
AurelienUoU
|
a93d7e57f7
|
Scan chain support in directlist
|
2019-09-27 16:53:00 -06:00 |
|
tangxifan
|
167778cf57
|
refactoring MUX Verilog instanciation in Switch block
|
2019-09-27 16:05:47 -06:00 |
|
Ganesh Gore
|
438b592a8a
|
Appended VPR to genereate INI File
|
2019-09-27 14:00:27 -06:00 |
|
Ganesh Gore
|
a3e9b4aea9
|
Added mINI/lib - INI Read write to project
|
2019-09-27 13:58:48 -06:00 |
|
tangxifan
|
dbe1625267
|
Refactored Verilog wiring for formal verification ports in Switch Blocks
|
2019-09-27 13:51:22 -06:00 |
|
tangxifan
|
ead014e7d8
|
refactoring the configuration bus Verilog generation for MUXes
|
2019-09-27 11:47:34 -06:00 |
|
tangxifan
|
091bbd4d9c
|
start refactoring the num_config_bits for circuit model
|
2019-09-26 22:53:07 -06:00 |
|
tangxifan
|
8ccf681749
|
Merge branch 'dev' into refactoring
|
2019-09-26 21:00:19 -06:00 |
|
tangxifan
|
f0589cc2cf
|
refactoring mux Verilog generation for switch blocks
|
2019-09-26 20:59:19 -06:00 |
|
tangxifan
|
05eaa412b1
|
refactored short-connection of switch block
|
2019-09-26 14:31:05 -06:00 |
|
AurelienUoU
|
3b13c959f3
|
Finish renaming SCFF to CCFF
|
2019-09-26 14:04:40 -06:00 |
|
AurelienUoU
|
c4449b667f
|
Merge remote-tracking branch 'origin/dev' into heterogeneous
|
2019-09-26 11:34:59 -06:00 |
|
AurelienUoU
|
056219f180
|
Rename SCFF to CCFF, configuration chain flip flop
|
2019-09-26 11:32:57 -06:00 |
|
tangxifan
|
ea0da49e04
|
Merge branch 'dev' into refactoring
|
2019-09-25 21:06:06 -06:00 |
|
tangxifan
|
5bb40e7f74
|
refactored local wire generation for Switch block
|
2019-09-25 21:05:02 -06:00 |
|
AurelienUoU
|
e5faeb1400
|
Merge remote-tracking branch 'origin/dev' into heterogeneous
|
2019-09-25 16:50:53 -06:00 |
|
AurelienUoU
|
a35e2936b2
|
Fix verilog generation for direct connexion from directlist
|
2019-09-25 16:44:00 -06:00 |
|
tangxifan
|
2b0e2615fa
|
refactored sram port addition to module manager
|
2019-09-25 16:09:58 -06:00 |
|
tangxifan
|
c911f15a67
|
add formal verification port to SB Verilog generation
|
2019-09-23 21:15:45 -06:00 |
|
tangxifan
|
e1742b68ef
|
add pre-processing flag support for module manager
|
2019-09-23 20:25:53 -06:00 |
|
tangxifan
|
d2ddbc19a3
|
refactoring the reserved sram port generation
|
2019-09-22 16:38:16 -06:00 |
|
tangxifan
|
2c4372c506
|
add reserved BLB/WL port naming
|
2019-09-22 12:16:43 -06:00 |
|
tangxifan
|
1e4177067d
|
remove port size in the module definition
|
2019-09-22 11:21:43 -06:00 |
|
tangxifan
|
0ff0c8cf06
|
bug fix for IO=1
|
2019-09-19 15:43:25 -06:00 |
|
tangxifan
|
e0b253d30a
|
minor fix for non-LUT intermedate buffer case
|
2019-09-18 15:15:03 -06:00 |
|
tangxifan
|
0f0d06aad7
|
add non-LUT intermediate buffer to test and apply minor bug fix
|
2019-09-18 15:04:51 -06:00 |
|
tangxifan
|
d7ac7d3649
|
start refactoring the switch block verilog generation
|
2019-09-17 20:40:26 -06:00 |
|
tangxifan
|
2294aecef2
|
remove old codes and compact new codes
|
2019-09-16 20:19:14 -06:00 |
|
tangxifan
|
c5ee81541a
|
remove dead codes in routing module generation
|
2019-09-16 18:47:01 -06:00 |
|
tangxifan
|
0963852091
|
remove useless global ports for routing channel modules
Need to rework the top-netlist generator before the new module generator can be plugged-in
|
2019-09-16 18:38:37 -06:00 |
|
tangxifan
|
d83cad7c2e
|
refactoring Verilog generation for routing channels
|
2019-09-16 17:35:51 -06:00 |
|
Baudouin Chauviere
|
d5ebe66ad9
|
Bug fix
|
2019-09-16 10:57:52 -06:00 |
|
Ganesh Gore
|
d90329678a
|
Merge remote-tracking branch 'lnis_origin/dev' into ganesh_dev
|
2019-09-14 12:11:36 -06:00 |
|
Ganesh Gore
|
ec3854a648
|
Merge remote-tracking branch 'origin/ganesh_dev' into dev
|
2019-09-14 00:14:17 -06:00 |
|
tangxifan
|
f69ce708ca
|
rework on the order of top-level functions
|
2019-09-13 21:59:52 -06:00 |
|
tangxifan
|
29e80d157c
|
Start developing BitstreamContext
|
2019-09-13 21:27:47 -06:00 |
|
tangxifan
|
e64cfc5852
|
start refactoring memory decoders
|
2019-09-13 20:58:55 -06:00 |
|
Baudouin Chauviere
|
737cfb1086
|
Correction to the explicit Verilog for FPGAs above 2x2
|
2019-09-13 16:02:06 -06:00 |
|
Baudouin Chauviere
|
63e6ed21b5
|
Fully functional
|
2019-09-13 16:02:06 -06:00 |
|
tangxifan
|
d6fc9c1c71
|
Find out the mem circuit is so correlated to the new MUX Verilog. Plug-in later
|
2019-09-13 15:36:35 -06:00 |
|
tangxifan
|
009c0d63b5
|
refactored the memory bank. Ready to plug-in the test
|
2019-09-13 15:05:31 -06:00 |
|
tangxifan
|
99c30fa7dd
|
keep refactoring the memory Verilog generation
|
2019-09-13 14:02:04 -06:00 |
|
tangxifan
|
56f40cf46c
|
light modification on Verilog Mux generation and start refactoring memory Verilog generation
|
2019-09-13 12:22:57 -06:00 |
|
tangxifan
|
d8b9349066
|
remove legacy codes
|
2019-09-13 11:48:25 -06:00 |
|
tangxifan
|
b920f0fc38
|
refactored user template Verilog generation
|
2019-09-13 11:41:54 -06:00 |
|
tangxifan
|
0e6c88dd52
|
delete legacy codes for wire Verilog generation
|
2019-09-12 21:06:53 -06:00 |
|
tangxifan
|
c20e182484
|
plugged in the refactored wire Verilog generation
|
2019-09-12 20:56:30 -06:00 |
|
tangxifan
|
2b829238b5
|
refactored wire Verilog generation
|
2019-09-12 20:49:02 -06:00 |
|
tangxifan
|
79fa858f36
|
remove unused ports for Verilog modules
|
2019-09-11 19:39:59 -06:00 |
|
tangxifan
|
2bed51bf29
|
minor bug fix for echo
|
2019-09-11 17:41:45 -06:00 |
|
tangxifan
|
0399319212
|
refactored LUT Verilog generation
|
2019-09-11 17:04:43 -06:00 |
|
tangxifan
|
6a5b50facf
|
refactored RRAM MUX verilog generation
|
2019-09-10 20:45:44 -06:00 |
|
tangxifan
|
0711aa1bd6
|
minor bug fixing
|
2019-09-10 16:56:14 -06:00 |
|
tangxifan
|
82683d49cf
|
remove legacy codes of local encoders
|
2019-09-10 15:34:20 -06:00 |
|
tangxifan
|
5f561ef5e3
|
pass regression test when plug in refactored local encoders
|
2019-09-10 15:26:47 -06:00 |
|
tangxifan
|
62853c092f
|
refactoring local encoders. Ready to plug in
|
2019-09-10 15:16:29 -06:00 |
|
Ganesh Gore
|
d64bb18346
|
Separated Modelsim tcl script generation
|
2019-09-07 12:36:22 -04:00 |
|
tangxifan
|
59edd49862
|
refactored CMOS MUX buffering
|
2019-09-06 16:39:34 -06:00 |
|
tangxifan
|
bc9d95408e
|
bug fixed and refactored intermediate buffer addition
|
2019-09-05 16:09:28 -06:00 |