start developing module graph builders

vpr7_x2p/vpr/SRC/device/mux_library_builder.h

@@ -6,6 +6,10 @@
 #ifndef MUX_LIBRARY_BUILDER_H
 #define MUX_LIBRARY_BUILDER_H
 
+#include "vpr_types.h"
+#include "circuit_library.h"
+#include "mux_library.h"
+
 MuxLibrary build_device_mux_library(int LL_num_rr_nodes, t_rr_node* LL_rr_node,
                                     t_switch_inf* switches,
                                     const CircuitLibrary& circuit_lib,

vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_api.c

@@ -30,11 +30,14 @@
 #include "verilog_api.h"
 #include "fpga_bitstream.h"
 
+#include "mux_library_builder.h"
+#include "build_device_modules.h"
+
 #include "fpga_x2p_api.h"
 
 /* Top-level API of FPGA-SPICE */
 void vpr_fpga_x2p_tool_suites(t_vpr_setup vpr_setup,
-                                t_arch Arch) {
+                              t_arch Arch) {
   t_sram_orgz_info* sram_bitstream_orgz_info = NULL;
 
   /* Common initializations and malloc operations */
@@ -43,6 +46,12 @@ void vpr_fpga_x2p_tool_suites(t_vpr_setup vpr_setup,
     fpga_x2p_setup(vpr_setup, &Arch);
   }
 
+  /* Build multiplexer graphs */
+  MuxLibrary mux_lib = build_device_mux_library(num_rr_nodes, rr_node, switch_inf, Arch.spice->circuit_lib, &vpr_setup.RoutingArch);
+
+  /* Build module graphs */
+  ModuleManager module_manager = build_device_module_graph(vpr_setup, Arch, mux_lib);
+
   /* Xifan TANG: SPICE Modeling, SPICE Netlist Output  */ 
   if (TRUE == vpr_setup.FPGA_SPICE_Opts.SpiceOpts.do_spice) {
     vpr_fpga_spice(vpr_setup, Arch, vpr_setup.FileNameOpts.CircuitName);

vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_device_modules.cpp

@@ -0,0 +1,73 @@
+/********************************************************************
+ * This file includes the main function to build module graphs
+ * for the FPGA fabric
+ *******************************************************************/
+#include <time.h>
+#include <unistd.h>
+
+#include "vtr_assert.h"
+#include "util.h"
+#include "spice_types.h"
+#include "fpga_x2p_utils.h"
+
+#include "build_device_modules.h"
+
+/********************************************************************
+ * The main function to be called for building module graphs 
+ * for a FPGA fabric
+ *******************************************************************/
+ModuleManager build_device_module_graph(const t_vpr_setup& vpr_setup,
+                                        const t_arch& arch,
+                                        const MuxLibrary& mux_lib) {
+  /* Check if the routing architecture we support*/
+  if (UNI_DIRECTIONAL != vpr_setup.RoutingArch.directionality) {
+    vpr_printf(TIO_MESSAGE_ERROR, 
+               "FPGA X2P only supports uni-directional routing architecture!\n");
+    exit(1);
+  }
+
+  /* We don't support mrFPGA */
+#ifdef MRFPGA_H
+  if (is_mrFPGA) {
+    vpr_printf(TIO_MESSAGE_ERROR, 
+               "FPGA X2P does not support mrFPGA!\n");
+    exit(1);
+  }
+#endif
+
+  /* Module Graph builder formally starts*/
+  vpr_printf(TIO_MESSAGE_INFO, "\nStart building module graphs for FPGA fabric...\n");
+
+  /* Module manager to be built */
+  ModuleManager module_manager;
+
+  /* Start time count */
+  clock_t t_start = clock();
+
+  /* Assign the SRAM model applied to the FPGA fabric */
+  VTR_ASSERT(NULL != arch.sram_inf.verilog_sram_inf_orgz); /* Check !*/
+  t_spice_model* mem_model = arch.sram_inf.verilog_sram_inf_orgz->spice_model;
+  /* initialize the SRAM organization information struct */
+  CircuitModelId sram_model = arch.spice->circuit_lib.model(mem_model->name);  
+  VTR_ASSERT(CircuitModelId::INVALID() != sram_model);
+
+  /* TODO: This should be moved to FPGA-X2P setup 
+   * Check all the SRAM port is using the correct SRAM circuit model 
+   */
+  config_spice_models_sram_port_spice_model(arch.spice->num_spice_model, 
+                                            arch.spice->spice_models,
+                                            arch.sram_inf.verilog_sram_inf_orgz->spice_model);
+  config_circuit_models_sram_port_to_default_sram_model(arch.spice->circuit_lib, arch.sram_inf.verilog_sram_inf_orgz->circuit_model); 
+
+  /* TODO: Build elmentary modules */
+
+
+  /* End time count */
+  clock_t t_end = clock();
+
+  float run_time_sec = (float)(t_end - t_start) / CLOCKS_PER_SEC;
+  vpr_printf(TIO_MESSAGE_INFO, "Building module graphs took %g seconds\n", run_time_sec);  
+
+
+  return module_manager;
+}

vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_device_modules.h

@@ -0,0 +1,12 @@
+#ifndef BUILD_DEVICE_MODULES_H
+#define BUILD_DEVICE_MODULES_H
+
+#include "vpr_types.h"
+#include "mux_library.h"
+#include "module_manager.h"
+
+ModuleManager build_device_module_graph(const t_vpr_setup& vpr_setup,
+                                        const t_arch& arch,
+                                        const MuxLibrary& mux_lib);
+
+#endif