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add grid module generation

This commit is contained in:
tangxifan 2019-10-22 16:14:11 -06:00
parent 9cf8683acd
commit 89c8d089a3
7 changed files with 1167 additions and 953 deletions
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1124
vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_grid_modules.cpp Normal file
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18
vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_grid_modules.h Normal file
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@ -0,0 +1,18 @@
/********************************************************************
* Header file for build_grid_modules.cpp
*******************************************************************/
#ifndef BUILD_GRID_MODULES_H
#define BUILD_GRID_MODULES_H
/* Only include headers related to the data structures used in the following function declaration */
#include "vpr_types.h"
#include "module_manager.h"
#include "mux_library.h"
void build_grid_modules(ModuleManager& module_manager,
const CircuitLibrary& circuit_lib,
const MuxLibrary& mux_lib,
const e_sram_orgz& sram_orgz_type,
const CircuitModelId& sram_model);
#endif

6
vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_memory_modules.h
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@ -1,9 +1,9 @@
/***********************************************
* Header file for verilog_memory.cpp
* Header file for build_memory_modules.cpp
**********************************************/
#ifndef BUILD_MEMORY_MODULE_H
#define BUILD_MEMORY_MODULE_H
#ifndef BUILD_MEMORY_MODULES_H
#define BUILD_MEMORY_MODULES_H
/* Include other header files which are dependency on the function declared below */

7
vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_module_graph.cpp
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@ -16,6 +16,7 @@
#include "build_lut_modules.h"
#include "build_wire_modules.h"
#include "build_memory_modules.h"
#include "build_grid_modules.h"
#include "build_module_graph.h"
/********************************************************************
@ -63,7 +64,7 @@ ModuleManager build_device_module_graph(const t_vpr_setup& vpr_setup,
config_spice_models_sram_port_spice_model(arch.spice->num_spice_model,
arch.spice->spice_models,
arch.sram_inf.verilog_sram_inf_orgz->spice_model);
config_circuit_models_sram_port_to_default_sram_model(arch.spice->circuit_lib, arch.sram_inf.verilog_sram_inf_orgz->circuit_model);
config_circuit_models_sram_port_to_default_sram_model(arch.spice->circuit_lib, sram_model);
/* Create a vector of segments. TODO: should come from DeviceContext */
std::vector<t_segment_inf> L_segment_vec;
@ -99,7 +100,9 @@ ModuleManager build_device_module_graph(const t_vpr_setup& vpr_setup,
build_memory_modules(module_manager, mux_lib, arch.spice->circuit_lib,
arch.sram_inf.verilog_sram_inf_orgz->type);
/* TODO: Build grid and programmable block modules */
/* Build grid and programmable block modules */
build_grid_modules(module_manager, arch.spice->circuit_lib, mux_lib,
arch.sram_inf.verilog_sram_inf_orgz->type, sram_model);
/* TODO: Build global routing architecture modules */

3
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c
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@ -294,8 +294,7 @@ void vpr_fpga_verilog(ModuleManager& module_manager,
lb_dir_path, Arch,
vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts.dump_explicit_verilog);
print_verilog_grids(module_manager, Arch.spice->circuit_lib, mux_lib,
sram_verilog_orgz_info,
print_verilog_grids(module_manager,
std::string(src_dir_path), std::string(lb_dir_path),
TRUE == vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts.dump_explicit_verilog);

957
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_grid.cpp
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5
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_grid.h
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@ -11,11 +11,8 @@
#include "mux_library.h"
void print_verilog_grids(ModuleManager& module_manager,
const CircuitLibrary& circuit_lib,
const MuxLibrary& mux_lib,
t_sram_orgz_info* cur_sram_orgz_info,
const std::string& verilog_dir,
const std::string& subckt_dir,
const bool& is_explicit_mapping);
const bool& use_explicit_mapping);
#endif