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rename grid modules to be clear

This commit is contained in:
tangxifan 2019-10-15 16:28:46 -06:00
parent 071757dc52
commit 6a13120208
2 changed files with 4 additions and 9 deletions
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7
vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp
View File

@ -679,8 +679,8 @@ std::string generate_grid_block_prefix(const std::string& prefix,
if (NUM_SIDES != io_side) {
Side side_manager(io_side);
block_prefix += std::string("_");
block_prefix += std::string(side_manager.to_string());
block_prefix += std::string("_");
}
return block_prefix;
@ -697,7 +697,9 @@ std::string generate_grid_block_netlist_name(const std::string& block_name,
std::string module_name(block_name);
if (true == is_block_io) {
module_name = generate_grid_block_prefix(block_name, io_side);
Side side_manager(io_side);
module_name += std::string("_");
module_name += std::string(side_manager.to_string());
}
module_name += postfix;
@ -719,7 +721,6 @@ std::string generate_grid_block_module_name(const std::string& prefix,
return module_name;
}
/*********************************************************************
* Generate the module name of a physical block
* To ensure a unique name for each physical block inside the graph of complex blocks

6
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_module.cpp
View File

@ -59,8 +59,6 @@ size_t add_top_module_grid_instance(ModuleManager& module_manager,
/* Add the module to top_module */
module_manager.add_child_module(top_module, grid_module);
printf("Added grid module %s to top-level module\n", grid_module_name.c_str());
return grid_instance;
}
@ -348,10 +346,6 @@ void add_top_module_nets_connect_grids_and_sb(ModuleManager& module_manager,
for (size_t pin_id = 0; pin_id < src_grid_port.pins().size(); ++pin_id) {
ModuleNetId net = module_manager.create_module_net(top_module);
/* Configure the net source */
printf("src_grid_module_name: %s[%lu][%lu], src_grid_instance_id: %lu (%lu)\n",
src_grid_module_name.c_str(),
grid_coordinate.x(),grid_coordinate.y(),
src_grid_instance, module_manager.num_instance(top_module, src_grid_module));
module_manager.add_module_net_source(top_module, net, src_grid_module, src_grid_instance, src_grid_port_id, src_grid_port.pins()[pin_id]);
/* Configure the net sink */
module_manager.add_module_net_sink(top_module, net, sink_sb_module, sink_sb_instance, sink_sb_port_id, sink_sb_port.pins()[pin_id]);