riscv
/
OpenFPGA
mirror of https://github.com/lnis-uofu/OpenFPGA.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

correct bugs in organizing child modules in top-level module

This commit is contained in:
tangxifan 2019-10-24 21:27:42 -06:00
parent 838173f3c4
commit 97193794c4
1 changed files with 2 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_top_module_memory.cpp
View File

@ -233,12 +233,12 @@ void organize_top_module_memory_modules(ModuleManager& module_manager,
}
/* TOP side I/Os */
for (size_t ix = 1; ix < device_size.x() - 1; ++ix) {
for (size_t ix = device_size.x() - 2; ix >= 1; --ix) {
io_coords[TOP].push_back(vtr::Point<size_t>(ix, device_size.y() - 1));
}
/* LEFT side I/Os */
for (size_t iy = 1; iy < device_size.y() - 1; ++iy) {
for (size_t iy = device_size.y() - 2; iy >= 1; --iy) {
io_coords[LEFT].push_back(vtr::Point<size_t>(0, iy));
}