riscv
/
OpenFPGA
mirror of https://github.com/lnis-uofu/OpenFPGA.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

plug in module graph to feed verilog writers

This commit is contained in:
tangxifan 2019-10-18 21:59:22 -06:00
parent b1cafcdbde
commit 04f0fbebf7
11 changed files with 114 additions and 23 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

9
vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_api.c
View File

@ -26,13 +26,14 @@
#include "fpga_x2p_utils.h"
#include "fpga_x2p_backannotate_utils.h"
#include "fpga_x2p_setup.h"
#include "spice_api.h"
#include "verilog_api.h"
#include "fpga_bitstream.h"
#include "mux_library_builder.h"
#include "build_module_graph.h"
#include "spice_api.h"
#include "verilog_api.h"
#include "fpga_bitstream.h"
#include "fpga_x2p_api.h"
/* Top-level API of FPGA-SPICE */
@ -59,7 +60,7 @@ void vpr_fpga_x2p_tool_suites(t_vpr_setup vpr_setup,
/* Xifan TANG: Synthesizable verilog dumping */
if (TRUE == vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts.dump_syn_verilog) {
vpr_fpga_verilog(vpr_setup, Arch, vpr_setup.FileNameOpts.CircuitName);
vpr_fpga_verilog(module_manager, vpr_setup, Arch, vpr_setup.FileNameOpts.CircuitName);
}
/* Xifan Tang: Bitstream Generator */

54
vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_essential_modules.cpp
View File

@ -6,6 +6,7 @@
#include "util.h"
#include "vtr_assert.h"
#include "fpga_x2p_naming.h"
#include "module_manager_utils.h"
#include "build_essential_modules.h"
@ -163,3 +164,56 @@ void build_essential_modules(ModuleManager& module_manager,
}
}
/*********************************************************************
* Register all the user-defined modules in the module manager
* Walk through the circuit library and add user-defined circuit models
* to the module_manager
********************************************************************/
void build_user_defined_modules(ModuleManager& module_manager,
const CircuitLibrary& circuit_lib,
const std::vector<t_segment_inf>& routing_segments) {
/* Iterate over Verilog modules */
for (const auto& model : circuit_lib.models()) {
/* We only care about user-defined models */
if ( (true == circuit_lib.model_verilog_netlist(model).empty())
&& (true == circuit_lib.model_verilog_netlist(model).empty()) ) {
continue;
}
/* Skip Routing channel wire models because they need a different name. Do it later */
if (SPICE_MODEL_CHAN_WIRE == circuit_lib.model_type(model)) {
continue;
}
/* Reach here, the model requires a user-defined Verilog netlist,
* Register it in the module_manager
*/
add_circuit_model_to_module_manager(module_manager, circuit_lib, model);
}
/* Register the routing channel wires */
for (const auto& seg : routing_segments) {
VTR_ASSERT( CircuitModelId::INVALID() != seg.circuit_model);
VTR_ASSERT( SPICE_MODEL_CHAN_WIRE == circuit_lib.model_type(seg.circuit_model));
/* We care only user-defined circuit models */
if ( (circuit_lib.model_verilog_netlist(seg.circuit_model).empty())
&& (circuit_lib.model_verilog_netlist(seg.circuit_model).empty()) ) {
continue;
}
/* Give a unique name for subckt of wire_model of segment,
* circuit_model name is unique, and segment id is unique as well
*/
std::string segment_wire_subckt_name = generate_segment_wire_subckt_name(circuit_lib.model_name(seg.circuit_model), &seg - &routing_segments[0]);
/* Create a Verilog Module based on the circuit model, and add to module manager */
ModuleId module_id = add_circuit_model_to_module_manager(module_manager, circuit_lib, seg.circuit_model, segment_wire_subckt_name);
/* Find the output port*/
std::vector<CircuitPortId> output_ports = circuit_lib.model_ports_by_type(seg.circuit_model, SPICE_MODEL_PORT_OUTPUT, true);
/* Make sure the port size is what we want */
VTR_ASSERT (1 == circuit_lib.port_size(output_ports[0]));
/* Add a mid-output port to the module */
BasicPort module_mid_output_port(generate_segment_wire_mid_output_name(circuit_lib.port_lib_name(output_ports[0])), circuit_lib.port_size(output_ports[0]));
module_manager.add_port(module_id, module_mid_output_port, ModuleManager::MODULE_OUTPUT_PORT);
}
}

4
vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_essential_modules.h
View File

@ -7,4 +7,8 @@
void build_essential_modules(ModuleManager& module_manager,
const CircuitLibrary& circuit_lib);
void build_user_defined_modules(ModuleManager& module_manager,
const CircuitLibrary& circuit_lib,
const std::vector<t_segment_inf>& routing_segments);
#endif

11
vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_module_graph.cpp
View File

@ -61,6 +61,17 @@ ModuleManager build_device_module_graph(const t_vpr_setup& vpr_setup,
arch.sram_inf.verilog_sram_inf_orgz->spice_model);
config_circuit_models_sram_port_to_default_sram_model(arch.spice->circuit_lib, arch.sram_inf.verilog_sram_inf_orgz->circuit_model);
/* Create a vector of segments. TODO: should come from DeviceContext */
std::vector<t_segment_inf> L_segment_vec;
for (int i = 0; i < arch.num_segments; ++i) {
L_segment_vec.push_back(arch.Segments[i]);
}
/* Register all the user-defined modules in the module manager
* This should be done prior to other steps in this function,
* because they will be instanciated by other primitive modules
*/
build_user_defined_modules(module_manager, arch.spice->circuit_lib, L_segment_vec);
/* Build elmentary modules */
build_essential_modules(module_manager, arch.spice->circuit_lib);

2
vpr7_x2p/vpr/SRC/fpga_x2p/shell/cmd_fpga_verilog.c
View File

@ -51,7 +51,7 @@ void shell_execute_fpga_verilog(t_shell_env* env, t_opt_info* opts) {
return;
}
vpr_fpga_verilog(env->vpr_setup, env->arch,
vpr_fpga_verilog(env->module_manager, env->vpr_setup, env->arch,
env->vpr_setup.FileNameOpts.CircuitName);
return;

9
vpr7_x2p/vpr/SRC/fpga_x2p/shell/shell_types.h
View File

@ -1,3 +1,9 @@
#ifndef SHELL_TYPES_H
#define SHELL_TYPES_H
#include "vpr_types.h"
#include "module_manager.h"
typedef struct s_cmd_category t_cmd_category;
typedef struct s_shell_cmd t_shell_cmd;
@ -28,6 +34,7 @@ struct s_shell_cmd {
};
struct s_shell_env {
ModuleManager module_manager;
t_arch arch;
t_vpr_setup vpr_setup;
t_shell_cmd* cmd;
@ -36,4 +43,4 @@ struct s_shell_env {
#define LAST_CMD_NAME NULL
#endif

6
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c
View File

@ -117,7 +117,8 @@ void free_global_routing_conf_bits() {
}
/* Top-level function*/
void vpr_fpga_verilog(t_vpr_setup vpr_setup,
void vpr_fpga_verilog(ModuleManager& module_manager,
t_vpr_setup vpr_setup,
t_arch Arch,
char* circuit_name) {
/* Timer */
@ -158,9 +159,6 @@ void vpr_fpga_verilog(t_vpr_setup vpr_setup,
t_sram_orgz_info* sram_verilog_orgz_info = NULL;
/* Module manager for the Verilog modules created */
ModuleManager module_manager;
/* Build Multiplexer library */
MuxLibrary mux_lib = build_device_mux_library(num_rr_nodes, rr_node, switch_inf, Arch.spice->circuit_lib, &vpr_setup.RoutingArch);

10
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.h
View File

@ -1,4 +1,12 @@
#ifndef VERILOG_API_H
#define VERILOG_API_H
void vpr_fpga_verilog(t_vpr_setup vpr_setup,
#include "vpr_types.h"
#include "module_manager.h"
void vpr_fpga_verilog(ModuleManager& module_manager,
t_vpr_setup vpr_setup,
t_arch Arch,
char* circuit_name);
#endif

8
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_decoders.cpp
View File

@ -55,23 +55,19 @@ void print_verilog_mux_local_decoder_module(std::fstream& fp,
std::string module_name = generate_mux_local_decoder_subckt_name(addr_size, data_size);
/* Create a Verilog Module based on the circuit model, and add to module manager */
ModuleId module_id = module_manager.add_module(module_name);
VTR_ASSERT(ModuleId::INVALID() != module_id);
ModuleId module_id = module_manager.find_module(module_name);
VTR_ASSERT(true == module_manager.valid_module_id(module_id));
/* Add module ports */
/* Add each input port */
BasicPort addr_port(generate_mux_local_decoder_addr_port_name(), addr_size);
module_manager.add_port(module_id, addr_port, ModuleManager::MODULE_INPUT_PORT);
/* Add each output port */
BasicPort data_port(generate_mux_local_decoder_data_port_name(), data_size);
module_manager.add_port(module_id, data_port, ModuleManager::MODULE_OUTPUT_PORT);
/* Data port is registered. It should be outputted as
* output reg [lsb:msb] data
*/
module_manager.set_port_is_register(module_id, data_port.get_name(), true);
/* Add data_in port */
BasicPort data_inv_port(generate_mux_local_decoder_data_inv_port_name(), data_size);
VTR_ASSERT(true == decoder_lib.use_data_inv_port(decoder));
module_manager.add_port(module_id, data_inv_port, ModuleManager::MODULE_OUTPUT_PORT);
/* dump module definition + ports */
print_verilog_module_declaration(fp, module_manager, module_id);

9
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_essential_gates.cpp
View File

@ -182,7 +182,8 @@ void print_verilog_invbuf_module(ModuleManager& module_manager,
}
/* Create a Verilog Module based on the circuit model, and add to module manager */
ModuleId module_id = add_circuit_model_to_module_manager(module_manager, circuit_lib, circuit_model);
ModuleId module_id = module_manager.find_module(circuit_lib.model_name(circuit_model));
VTR_ASSERT(true == module_manager.valid_module_id(module_id));
/* dump module definition + ports */
print_verilog_module_declaration(fp, module_manager, module_id);
@ -270,7 +271,8 @@ void print_verilog_passgate_module(ModuleManager& module_manager,
VTR_ASSERT( (1 == output_ports.size()) && (1 == circuit_lib.port_size(output_ports[0])) );
/* Create a Verilog Module based on the circuit model, and add to module manager */
ModuleId module_id = add_circuit_model_to_module_manager(module_manager, circuit_lib, circuit_model);
ModuleId module_id = module_manager.find_module(circuit_lib.model_name(circuit_model));
VTR_ASSERT(true == module_manager.valid_module_id(module_id));
/* dump module definition + ports */
print_verilog_module_declaration(fp, module_manager, module_id);
@ -453,7 +455,8 @@ void print_verilog_gate_module(ModuleManager& module_manager,
VTR_ASSERT( (1 == output_ports.size()) && (1 == circuit_lib.port_size(output_ports[0])) );
/* Create a Verilog Module based on the circuit model, and add to module manager */
ModuleId module_id = add_circuit_model_to_module_manager(module_manager, circuit_lib, circuit_model);
ModuleId module_id = module_manager.find_module(circuit_lib.model_name(circuit_model));
VTR_ASSERT(true == module_manager.valid_module_id(module_id));
/* dump module definition + ports */
print_verilog_module_declaration(fp, module_manager, module_id);

15
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c
View File

@ -3098,9 +3098,13 @@ void add_user_defined_verilog_modules(ModuleManager& module_manager,
continue;
}
/* Reach here, the model requires a user-defined Verilog netlist,
* Register it in the module_manager
* Try to find it in the module manager
* If not found, register it in the module_manager
*/
add_circuit_model_to_module_manager(module_manager, circuit_lib, model);
ModuleId module_id = module_manager.find_module(circuit_lib.model_name(model));
if (ModuleId::INVALID() == module_id) {
add_circuit_model_to_module_manager(module_manager, circuit_lib, model);
}
}
/* Register the routing channel wires */
@ -3116,7 +3120,12 @@ void add_user_defined_verilog_modules(ModuleManager& module_manager,
*/
std::string segment_wire_subckt_name = generate_segment_wire_subckt_name(circuit_lib.model_name(seg.circuit_model), &seg - &routing_segments[0]);
/* Create a Verilog Module based on the circuit model, and add to module manager */
/* Try to find the module in the module manager,
* If not found, create a Verilog Module based on the circuit model,
* and add to module manager */
if (ModuleId::INVALID() != module_manager.find_module(segment_wire_subckt_name)) {
continue;
}
ModuleId module_id = add_circuit_model_to_module_manager(module_manager, circuit_lib, seg.circuit_model, segment_wire_subckt_name);
/* Find the output port*/