0d03d7b483
[core] now fabric tile cache both grid and gsb coord for pb
2023-07-19 17:20:53 -07:00
778d03610c
[core] debugging
2023-07-19 15:27:05 -07:00
001b3b3f8b
[core] debugging
2023-07-19 14:38:07 -07:00
d03fa92ddf
[core] debugging
2023-07-19 12:49:35 -07:00
48e207d3e4
[core] debugging
2023-07-19 12:22:57 -07:00
6607bb7e48
[core] now fpga verilog supports tile modules
2023-07-18 22:35:22 -07:00
5ae146bd86
[core] finish up tile module builder
2023-07-18 21:17:40 -07:00
403ed4ea60
[core] still developing tile module port and net builder
2023-07-18 16:03:47 -07:00
aabcc25567
[core] developing tile module port and net builder
2023-07-17 23:06:55 -07:00
ba4b7e3522
[core] developing tile module builder
2023-07-16 15:18:09 -07:00
98c598cec2
[core] unique tile identifier done
2023-07-15 22:54:33 -07:00
ea8d128789
[core] syntax
2023-07-15 20:29:21 -07:00
c2ef5ca408
[core] developing top-left style tile info
2023-07-14 22:48:44 -07:00
327f7f4dab
[core] now adapt to latest API of DeviceGrid
2023-06-07 18:54:48 -07:00
aeeee6d8bd
[core] code format
2023-04-20 15:07:54 +08:00
40598d25a3
[core] fixed a bug which causes multi-clock programmable network failed in routing
2023-04-20 15:05:45 +08:00
928c7d5736
Merge branch 'master' into xt_clk_arch
2023-04-19 22:17:33 +08:00
cb4512b925
[core] code format
2023-04-19 11:10:42 +08:00
a84cc52d7c
[core] fixed a few bugs due to the changes in vtr regarding flat router
2023-04-19 11:08:18 +08:00
11f09db556
[core] fixed a bug where clock tracks do not pass through at higher level
2023-03-07 15:05:56 -08:00
50e201feeb
[core] now clock routing for programmable clock network works for 1 clock design
2023-03-07 13:13:25 -08:00
2ff3ad61ce
[core] format
2023-03-06 21:57:44 -08:00
45107bf14f
[core] debugging
2023-03-06 21:48:19 -08:00
c23b8e579d
[core] fixed a bug
2023-03-06 17:10:14 -08:00
9823983b30
[core] debuggign
2023-03-06 15:57:37 -08:00
1633279c65
[core] fixed a bug in building edges for nodes
2023-03-06 14:50:28 -08:00
953625b1ca
[core] format
2023-03-05 22:32:05 -08:00
de1e300ec7
[core] now resize rr_node for clock graph is working
2023-03-05 22:21:55 -08:00
81e9187aac
[core] debugging
2023-03-03 22:55:14 -08:00
4423d917fa
[core] debugging
2023-03-03 18:00:43 -08:00
29ee6e7136
[core] debugging
2023-03-03 17:33:53 -08:00
5a43b451c1
[core] debugging
2023-03-03 16:56:20 -08:00
c4ad21451c
[core] debugging
2023-03-02 21:54:48 -08:00
46510388be
[core] now fabric generator can wire clock ports to routing blocks
2023-03-02 12:33:26 -08:00
7732907623
[core] format
2023-02-28 17:01:11 -08:00
2ff8fb8737
[core] wrapping up clock routing command
2023-02-28 16:52:54 -08:00
bd2608d3e0
[core] dev
2023-02-28 15:41:37 -08:00
6f2572324e
[core] developing route clock rr_graph command
2023-02-28 11:52:38 -08:00
8d5c21b14d
[core] code format
2023-02-27 23:00:15 -08:00
2735b708d3
[core] reworked the tapping XML syntax
2023-02-27 22:59:44 -08:00
ff69664c14
[core] syntax
2023-02-27 22:39:12 -08:00
d4e19edc71
[core] finishing up clock rr_graph appending
2023-02-27 22:31:16 -08:00
0dfe96bcf1
[core] dev
2023-02-27 19:37:49 -08:00
b3dec93eb9
[core] code format
2023-02-27 15:12:59 -08:00
9ec4d690db
[core] clock edges interconnecting clock tracks across levels
2023-02-27 15:10:36 -08:00
b6eace8fac
[core] now switch id is linked in clock network
2023-02-27 13:10:54 -08:00
cae05a14e1
[core] dev
2023-02-26 23:10:50 -08:00
009d711ba5
[core] code format
2023-02-26 22:23:41 -08:00
87a9146082
[core] adding rr spatial lookup for clock nodes only
2023-02-26 22:23:17 -08:00
db36f87dfa
[core] enhance clock tree arch validation
2023-02-26 18:39:53 -08:00
b9e5ae7ae9
[core] developing
2023-02-26 18:31:08 -08:00
780fc0f26d
[core] developing validators and annotate rr_segment for clock arch
2023-02-26 18:03:55 -08:00
4bd952027f
[core] dev
2023-02-26 15:31:07 -08:00
75773ddd4e
[code] format
2023-02-26 12:46:29 -08:00
3db5acfb37
[core] dev
2023-02-26 12:40:13 -08:00
06f77d0435
[core] dev
2023-02-25 22:59:07 -08:00
8f0d94ba73
[code] format
2023-02-25 22:43:21 -08:00
0b33650761
[core] dev
2023-02-25 22:41:33 -08:00
8be6e7d0a0
[core] dev
2023-02-25 11:04:48 -08:00
cf84e1df53
[core] dev
2023-02-24 22:50:27 -08:00
7f07a9d031
[lib] add default seg/switch to clock arch. Fixed syntax
2023-02-24 19:15:39 -08:00
ee0459d729
[core] developing append_clock_rr_graph function
2023-02-24 17:58:37 -08:00
aa55c692d7
[core] starting developing core function for clock rr_graph build-up
2023-02-23 18:04:07 -08:00
f00acf1e62
[code] fixed all the compiler warnings under openfpga/src
2023-01-31 12:51:52 -08:00
9b5b1b0da7
[core] clang syntax error
2023-01-07 09:18:58 -08:00
2fc047daff
[core] format
2023-01-06 21:11:12 -08:00
26c294679a
[core] now setup commands follow templates
2023-01-06 20:52:37 -08:00
6d31b319a2
[engine] update source files subject to code formatting rules
2022-10-06 17:08:50 -07:00
0d8d8446ee
[test] fixed a bug where OPIN for direct connection is included in GSB
2022-09-30 15:24:51 -07:00
36b3e64b35
[engine] now pb_fixup can also accept vtr's post-routing-clustering sync up results
2022-09-28 12:17:16 -07:00
3285af4107
[engine] syntax
2022-09-28 11:39:37 -07:00
51f54bbf20
[engine] developing the steps to annotate clustering results
2022-09-27 16:54:48 -07:00
90ddd2ce32
[engine] now get incoming edges for IPINs only from GSB
2022-09-19 14:02:13 -07:00
3c6ef1925c
[engine] now sort ipin incoming edges
2022-09-19 11:00:08 -07:00
56619f9a47
Merge branch 'master' of https://github.com/lnis-uofu/OpenFPGA into vtr_upgrade
2022-09-07 15:04:05 -07:00
eab3580f79
[engine] now consider circuit model rather than switchId and SegmentId when identifying GSB structure similarity
2022-09-06 13:40:29 -07:00
2f84ce5955
[engine] now move rr_gsb mirror function outside the class, because of the circuit_lib should be used
2022-09-06 11:48:21 -07:00
b26b2d0ed0
Merge branch 'master' into vtr_upgrade
2022-09-02 10:05:23 -07:00
04abd1a36f
add <array> declaration to fix gcc error
2022-09-02 19:26:28 +05:30
e4aa6e0ee5
[engine] syntax
2022-09-01 15:17:39 -07:00
ee87b5c348
[engine] fixed all the remaining syntax errors due to API mismatches
2022-09-01 09:57:12 -07:00
7c5046cf4e
[engine] include the correct header file
2022-09-01 09:23:05 -07:00
71ad0721a1
Merge branch 'master' into vtr_upgrade
2022-08-31 13:56:17 -07:00
26388dfb2f
[engine] fixed a bug which causes errors when writing unique GSB to files
2022-08-30 15:45:00 -07:00
3656154913
[engine] fixed syntax errors
2022-08-29 21:17:48 -07:00
2321ea6274
[engine] complete the code required to output rr_gsb with options
2022-08-29 20:44:16 -07:00
12a30196e0
[engine] updating gsb writer; Unfinished!!!
2022-08-29 16:58:48 -07:00
e9d6e7e38a
[engine] update vtr and enable more debugging info
2022-08-27 19:12:43 -07:00
d1edc51165
[engine] clean up header files that include rr_graph_obj
2022-08-23 18:38:21 -07:00
892770a8fb
[engine] debugging subtile index failures
2022-08-23 14:13:10 -07:00
019e663e12
[engine] fixing the bugs on building global nets to sub tile pins
2022-08-23 11:58:44 -07:00
ba0ddd01d3
[engine] fixing the bugs on subtiles
2022-08-23 10:52:05 -07:00
c17e5d46ab
[engine] fixed a bug due to the API of subtile data structure
2022-08-22 21:44:05 -07:00
800ce6a290
[engine] avoid function naming conflicts
2022-08-18 19:33:56 -07:00
e9c4d102c1
[engine] rename files to avoid conflicts with VPR files
2022-08-17 20:01:50 -07:00
8f1aac885e
[engine] fixing mismatches in APIs
2022-08-17 14:19:02 -07:00
4e871be357
[engine] adapt the use of API in RRGraph for annotation functions
2022-08-17 10:50:16 -07:00
01d53db484
[script] Adapt timing analysis APIs
2022-08-17 10:28:58 -07:00
ade8f43a36
[engine] Updating RRGraph Annotation and VTr
2022-08-17 10:16:55 -07:00
716929536d
[engine] adapting source files for new APIs in VTR
2022-08-17 09:54:31 -07:00
d3d81f0b18
[engine] keep adapting to latest VTR
2022-08-16 21:05:50 -07:00
0c329866da
[engine] Use RRGraphView in openfpga source codes
2022-08-16 16:48:32 -07:00
ce7204daec
[engine] debugging
2022-08-16 16:35:08 -07:00
a20f6eaf06
[Engine] Fixed a few bugs
2022-04-10 21:29:38 +08:00
755be78b39
[Engine] Now GSB output file contains segments name and pin name in SB module
2022-04-10 21:22:30 +08:00
a9a56686e2
[Engine] Add a new option ``--unique`` to command ``write_gsb_to_xml``
2022-01-26 11:10:29 -08:00
148da80869
[Tool] Add new syntax about physical_pb_port_rotate_offset to support fracturable heterogeneous block mapping between operating modes and physical modes
2021-04-24 14:53:29 -06:00
0aec30bac6
[Tool] Update FPGA core engine to support mux default path overloading through bitstream setting file
2021-04-19 15:53:33 -06:00
87006e1374
Merge branch 'master' into netlist_name_patch
2021-03-15 10:06:24 -06:00
d2fbda4070
Merge branch 'master' into netlist_name_patch
2021-03-15 09:13:04 -06:00
b080bcf018
Merge branch 'master' into ganesh_dev
2021-03-15 09:12:50 -06:00
02967f2870
Added writing rr graph node indices to GSB dump.
...
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
2021-03-15 09:28:38 +01:00
2c5634ee76
[Tool] Change pin naming of grid modules to be related to architecture port names
2021-03-13 20:05:18 -07:00
d877a02534
[Tool] Patch the extended bitstream setting support on mode-select bits
2021-03-10 21:28:09 -07:00
85640a7403
[Tool] Extend bitstream setting to support mode bits overload from eblif file
2021-03-10 20:45:48 -07:00
0c409b5bcc
[Tool] Add bitstream annotation support
2021-02-01 20:49:36 -07:00
4b77a3a574
[Tool] Now activity file is not a manadatory input of openfpga tools
2021-01-29 11:33:40 -07:00
87b2c1f3b8
[Tool] Upgrade openfpga engine to support multi-clock frequency definiton and their usage in testbench/SDC generation
2021-01-15 12:01:53 -07:00
852f5bb72e
[Tool] Update simulation setting object to support multi-clock and associated XML parsers/writers
2021-01-14 15:38:24 -07:00
b661c39b04
[Tool] Force the number of simulation clock cycles to be >= 2 to avoid false-positive self-testing in testbenches
2020-12-02 19:36:36 -07:00
04070fd4ca
[Debug aid] add pb_type full hierarchy path in the error message of architecture binding checker
2020-09-02 22:16:10 -06:00
3eea12ceae
added a new XML syntax: initial offset for physical mode pin mapping
2020-08-19 14:43:44 -06:00
f631245b2b
bug fix and enriched debugging info print out
2020-08-19 13:41:04 -06:00
79b6ff3cb0
relax checking for device annotation as we support multi-port during physical mode pin mapping
2020-08-19 12:44:51 -06:00
2712c354a9
now physical pb_port binding support multiple ports
2020-08-18 12:38:56 -06:00
4f8260a7ba
remove obselete codes and update regression tests
2020-07-04 17:31:34 -06:00
ebf5636e7b
add verbose output to edge sorting for GSBs
2020-06-26 17:10:51 -06:00
5d79a3f69f
critical bug fixed when annotating the routing results.
...
Add previous node check. This is due to that some loops between SB/CBs may exist
when routing congestion is high, which leads to same nets appear in the inputs
of a routing multiplexer. Actually one of them is driven by the other as a downstream node
Using previous node check can identify which one to pick
2020-06-17 11:17:57 -06:00
2e3a811f4f
critical bug fixed in repacking. This is due to depop50% local routing where the same net may be mapped to two different pins in the same pb_graph_pin. Now we restrict the pin searching. But in long term, we should sync the pb_route results to post routing results
2020-04-18 21:04:46 -06:00
72e8824a87
bug fixed on removing undriven pins (direct connection between clbs) from cb
2020-04-15 20:41:15 -06:00
b9dab2baaf
add exit codes to command execution in shell context
2020-04-08 16:18:05 -06:00
1fb37f4c71
improve directory creator to support same functionality as 'mkdir -p'
2020-04-08 12:55:09 -06:00
0b1c8ac139
bug fixed in identifying the physical interconnect for pb_graph nodes
2020-04-07 19:46:42 -06:00
62276f9e28
minor code format
2020-04-07 18:43:11 -06:00
ff474d87de
fixed critical bug in uniquifying GSBs. Now it can guarantee minimum number of unique GSBs
2020-03-22 16:11:00 -06:00
fdf6a6bd3e
use chan_node_in_edges from rr_gsb in XML writer
2020-03-22 15:48:11 -06:00
7b9384f3b2
add write_gsb command to shell interface
2020-03-21 19:40:26 -06:00
637be076dc
adding xml writer for device rr_gsb to help debugging the compress routing; current compress routing is not working
2020-03-21 18:49:20 -06:00
28123b8052
remove the direct connected IPIN/OPIN from RR GSB builder
2020-03-21 11:38:39 -06:00
aff73bdd74
deployed edge sorting and make it as an option to link_arch command
2020-03-08 15:59:53 -06:00
0c7aa2581d
update vpr8 version with hotfix on undriven pins in GSB
2020-03-08 14:58:56 -06:00
6e83154703
move rr_gsb and rr_chan to tileable rr_graph builder
2020-03-04 14:14:28 -07:00
aa66042dfb
move simulation setting annotation to a separated source file
2020-02-29 15:19:02 -07:00
2dd80e4830
add more methods to acquire physical truth table from physical pb
2020-02-25 21:21:44 -07:00
8e9660b816
add mapped block fast look-up as placement annotation
2020-02-24 16:09:29 -07:00
921bf7dd7b
use constant in device annotation
2020-02-21 20:45:22 -07:00
12f2888c7c
add physical pb data structure and basic allocator
2020-02-21 17:47:27 -07:00
b035b4c87f
debugged with Lbrouter. Next step is to output routing traces to physical pb data structure
2020-02-21 12:16:50 -07:00
62e4f14e30
add lb_rr_graph to device annotation
2020-02-17 17:26:27 -07:00
59c13550e0
add direct annotation with inter-column/row syntax
2020-02-14 17:40:59 -07:00
ce63b1cc62
add circuit model binding for direct connections and enhance model type checking
2020-02-12 11:40:20 -07:00
4a05cec037
add rr_segment binding to circuit model
2020-02-12 11:21:40 -07:00
a736e09c29
add rr_switch binding in link openfpga arch command
2020-02-12 10:52:20 -07:00
feccbc5780
add more methods to link routing to circuit models in device annotation
2020-02-12 10:08:54 -07:00
a31d6c6d1e
rename pb_type annotation to device annotation
2020-02-12 09:52:18 -07:00
175bef014a
add compact_routing hierarchy command
2020-02-11 17:40:37 -07:00
1372f748f1
put GSB builder online
2020-02-11 16:37:14 -07:00
85f3826939
put device rr_gsb online. Ready to plug-in
2020-02-09 14:58:23 -07:00
230c7b709a
put rr_gsb data structure online
2020-02-09 00:20:44 -07:00
0b6b3bc029
start adapting rr_gsb related data structure
2020-02-07 11:32:33 -07:00
ed9e038845
add functionality of LUT truth table fix-up
2020-02-06 17:14:29 -07:00
99f5a86b49
bug fixed for routing annotation and routing net fix-up
2020-02-06 12:54:55 -07:00
cccbb9fd49
add missing files
2020-02-05 22:12:44 -07:00
dad204674b
done an initial version of clustering net fix-up based on routing results. Debugging on the way
2020-02-05 21:50:52 -07:00
75c3507acf
add verbose output option for openfpga linking architecture
2020-01-31 11:36:58 -07:00
392ab0f027
move duplicated codes on message printing to functions
2020-01-31 10:53:41 -07:00
afde9808da
add check codes for physical pb_graph_node and pb_graph_pin annotation
2020-01-31 10:47:05 -07:00
fdc304a0fb
fixed a bug in mapping pb_graph pins using rotation offset
2020-01-30 22:00:53 -07:00
02d6256e95
pass simple test on pb_type annotation for frac_lut5 architecture
2020-01-30 21:39:44 -07:00
007e1997e6
add pb_graph pin annotation
2020-01-30 19:40:40 -07:00
d62c9fe86f
adding pb_graph_node annotation
2020-01-30 16:40:13 -07:00
e48ab8cb44
move annotation source files to a separated folder
2020-01-30 13:37:41 -07:00
tangxifan
coolbreeze413
Maciej Kurc