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[core] debugging

This commit is contained in:
tangxifan 2023-03-06 21:48:19 -08:00
parent c23b8e579d
commit 45107bf14f
6 changed files with 14 additions and 4 deletions
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8
openfpga/src/annotation/annotate_rr_graph.cpp
View File

@ -96,7 +96,8 @@ static RRChan build_one_rr_chan(const DeviceContext& vpr_device_ctx,
*/
static RRGSB build_rr_gsb(const DeviceContext& vpr_device_ctx,
const vtr::Point<size_t>& gsb_range,
const vtr::Point<size_t>& gsb_coord) {
const vtr::Point<size_t>& gsb_coord,
const bool& include_clock) {
/* Create an object to return */
RRGSB rr_gsb;
@ -370,7 +371,7 @@ static RRGSB build_rr_gsb(const DeviceContext& vpr_device_ctx,
/* Collect IPIN rr_nodes*/
temp_ipin_rr_nodes =
find_rr_graph_grid_nodes(vpr_device_ctx.rr_graph, vpr_device_ctx.grid, ix,
iy, IPIN, ipin_rr_node_grid_side);
iy, IPIN, ipin_rr_node_grid_side, include_clock);
/* Fill the ipin nodes of RRGSB */
for (const RRNodeId& inode : temp_ipin_rr_nodes) {
/* Skip those has no configurable outgoing, they should NOT appear in the
@ -405,6 +406,7 @@ static RRGSB build_rr_gsb(const DeviceContext& vpr_device_ctx,
*******************************************************************/
void annotate_device_rr_gsb(const DeviceContext& vpr_device_ctx,
DeviceRRGSB& device_rr_gsb,
const bool& include_clock,
const bool& verbose_output) {
vtr::ScopedStartFinishTimer timer(
"Build General Switch Block(GSB) annotation on top of routing resource "
@ -431,7 +433,7 @@ void annotate_device_rr_gsb(const DeviceContext& vpr_device_ctx,
build_rr_gsb(vpr_device_ctx,
vtr::Point<size_t>(vpr_device_ctx.grid.width() - 2,
vpr_device_ctx.grid.height() - 2),
vtr::Point<size_t>(ix, iy));
vtr::Point<size_t>(ix, iy), include_clock);
/* Add to device_rr_gsb */
vtr::Point<size_t> gsb_coordinate = rr_gsb.get_sb_coordinate();

1
openfpga/src/annotation/annotate_rr_graph.h
View File

@ -17,6 +17,7 @@ namespace openfpga {
void annotate_device_rr_gsb(const DeviceContext& vpr_device_ctx,
DeviceRRGSB& device_rr_gsb,
const bool& include_clock,
const bool& verbose_output);
void sort_device_rr_gsb_chan_node_in_edges(const RRGraphView& rr_graph,

1
openfpga/src/base/openfpga_link_arch_template.h
View File

@ -110,6 +110,7 @@ int link_arch_template(T& openfpga_ctx, const Command& cmd,
VTR_ASSERT(g_vpr_ctx.device().rr_graph.validate_in_edges());
annotate_device_rr_gsb(g_vpr_ctx.device(),
openfpga_ctx.mutable_device_rr_gsb(),
!openfpga_ctx.clock_arch().empty(), /* FIXME: consider to be more robust! */
cmd_context.option_enable(cmd, opt_verbose));
if (true == cmd_context.option_enable(cmd, opt_sort_edge)) {

3
openfpga/src/fpga_bitstream/build_mux_bitstream.cpp
View File

@ -68,6 +68,9 @@ static std::vector<bool> build_cmos_mux_bitstream(
find_mux_implementation_num_inputs(circuit_lib, mux_model, mux_size);
/* Note that the mux graph is indexed using datapath MUX size!!!! */
MuxId mux_graph_id = mux_lib.mux_graph(mux_model, mux_size);
if (!mux_lib.valid_mux_id(mux_graph_id)) {
VTR_ASSERT(mux_lib.valid_mux_id(mux_graph_id));
}
const MuxGraph mux_graph = mux_lib.mux_graph(mux_graph_id);
size_t datapath_id = path_id;

3
openfpga/src/mux_lib/mux_library_builder.cpp
View File

@ -231,6 +231,9 @@ MuxLibrary build_device_mux_library(const DeviceContext& vpr_device_ctx,
VTR_LOG("Built a multiplexer library of %lu physical multiplexers.\n",
mux_lib.muxes().size());
VTR_LOG("Maximum multiplexer size is %lu.\n", mux_lib.max_mux_size());
for (auto mux_id : mux_lib.muxes()) {
VTR_LOG("\tmodel '%s', input_size='%lu'\n", openfpga_ctx.arch().circuit_lib.model_name(mux_lib.mux_circuit_model(mux_id)).c_str(), mux_lib.mux_graph(mux_id).num_inputs());
}
return mux_lib;
}

2
vtr-verilog-to-routing

@ -1 +1 @@
Subproject commit 8e623dc487f9ba671f65f5fe896daac62bda9952
Subproject commit 1a9b9708bbbf7ddd8f4786a0b5afd5db5f1404eb