Merge branch 'master' into xt_clk_arch
This commit is contained in:
commit
928c7d5736
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@ -36,7 +36,7 @@ jobs:
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access_token: ${{ github.token }}
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- name: Checkout OpenFPGA repo
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uses: actions/checkout@v2
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uses: actions/checkout@v3
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with:
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fetch-depth: 0
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@ -114,7 +114,7 @@ jobs:
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access_token: ${{ github.token }}
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- name: Checkout OpenFPGA repo
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uses: actions/checkout@v2
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uses: actions/checkout@v3
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- name: Install dependencies
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run: sudo bash ./.github/workflows/install_dependencies_build.sh
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@ -127,10 +127,14 @@ jobs:
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- uses: hendrikmuhs/ccache-action@v1
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- name: Build
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- name: checkout submodules
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shell: bash
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run: |
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make checkout
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- name: Build
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shell: bash
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run: |
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make compile BUILD_TYPE=$BUILD_TYPE
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# Check the cache size and see if it is over the limit
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@ -199,7 +203,7 @@ jobs:
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access_token: ${{ github.token }}
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- name: Checkout OpenFPGA repo
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uses: actions/checkout@v2
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uses: actions/checkout@v3
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- name: Install dependencies
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run: sudo bash ./.github/workflows/install_dependencies_build.sh
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@ -212,10 +216,14 @@ jobs:
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- uses: hendrikmuhs/ccache-action@v1
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- name: Build
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- name: checkout submodules
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shell: bash
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run: |
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make checkout
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- name: Build
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shell: bash
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run: |
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make compile BUILD_TYPE=$BUILD_TYPE CMAKE_FLAGS="${{ matrix.config.cmake_flags }}"
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ubuntu_support:
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@ -241,7 +249,7 @@ jobs:
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access_token: ${{ github.token }}
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- name: Checkout OpenFPGA repo
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uses: actions/checkout@v2
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uses: actions/checkout@v3
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- name: Install dependencies
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run: sudo bash ./.github/workflows/install_dependencies_build_ubuntu22p04.sh
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@ -254,10 +262,14 @@ jobs:
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- uses: hendrikmuhs/ccache-action@v1
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- name: Build
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- name: checkout submodules
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shell: bash
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run: |
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make checkout
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- name: Build
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shell: bash
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run: |
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make compile BUILD_TYPE=$BUILD_TYPE
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debug_build:
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@ -287,7 +299,7 @@ jobs:
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access_token: ${{ github.token }}
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- name: Checkout OpenFPGA repo
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uses: actions/checkout@v2
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uses: actions/checkout@v3
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- name: Install dependencies
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run: |
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@ -303,10 +315,14 @@ jobs:
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- uses: hendrikmuhs/ccache-action@v1
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- name: Build
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- name: checkout submodules
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shell: bash
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run: |
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make checkout
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- name: Build
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shell: bash
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run: |
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make compile BUILD_TYPE=${{ matrix.config.build_type }} -j ${{ matrix.config.cores }}
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- name: Quick Test
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access_token: ${{ github.token }}
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- name: Checkout OpenFPGA repo
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uses: actions/checkout@v2
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uses: actions/checkout@v3
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- name: Install dependencies
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run: |
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@ -355,10 +371,14 @@ jobs:
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- uses: hendrikmuhs/ccache-action@v1
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- name: Build
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- name: checkout submodules
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shell: bash
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run: |
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make checkout
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- name: Build
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shell: bash
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run: |
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make compile BUILD_TYPE=${{ matrix.config.build_type }} -j ${{ matrix.config.cores }} CMAKE_FLAGS="-DOPENFPGA_ENABLE_STRICT_COMPILE=ON"
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- name: Quick Test
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@ -377,7 +397,7 @@ jobs:
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access_token: ${{ github.token }}
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- name: Checkout OpenFPGA repo
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uses: actions/checkout@v2
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uses: actions/checkout@v3
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- name: Download a built artifacts
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uses: actions/download-artifact@v2
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with:
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@ -430,7 +450,7 @@ jobs:
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access_token: ${{ github.token }}
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- name: Checkout OpenFPGA repo
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uses: actions/checkout@v2
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uses: actions/checkout@v3
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- name: Download a built artifacts
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uses: actions/download-artifact@v2
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with:
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|
@ -488,7 +508,8 @@ jobs:
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access_token: ${{ github.token }}
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- name: Checkout OpenFPGA repo
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uses: actions/checkout@v2
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uses: actions/checkout@v3
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- name: ${{matrix.config.name}}_GCC-8_(Ubuntu 20.04)
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shell: bash
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run: |
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|
|
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@ -21,7 +21,7 @@ jobs:
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access_token: ${{ github.token }}
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- name: Checkout OpenFPGA repo
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uses: actions/checkout@v2
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uses: actions/checkout@v3
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- name: Install Dependencies
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run: |
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|
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@ -80,7 +80,11 @@ set(ODIN_WARN OFF CACHE BOOL "Enable building odin with extra warning flags in V
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set(ODIN_COVERAGE OFF CACHE BOOL "Enable building odin with coverage flags in Verilog-to-Routing")
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set(ODIN_TIDY OFF CACHE BOOL "Enable building odin with clang tidy in Verilog-to-Routing")
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set(ODIN_SANITIZE OFF CACHE BOOL "Enable building odin with sanitize flags in Verilog-to-Routing")
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set(WITH_YOSYS OFF CACHE BOOL "Enable building Yosys in Verilog-to-Routing")
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set(WITH_PARMYS OFF CACHE BOOL "Enable Yosys as elaborator and parmys-plugin as partial mapper")
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set(ODIN_YOSYS OFF CACHE BOOL "Enable building odin with yosys in Verilog-to-Routing")
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set(YOSYS_SV_UHDM_PLUGIN OFF CACHE BOOL "Enable building and installing Yosys SystemVerilog and UHDM plugins in Verilog-to-Routing")
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set(YOSYS_F4PGA_PLUGINS OFF CACHE BOOL "Enable building and installing Yosys SystemVerilog and UHDM plugins")
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set(VTR_ENABLE_VERSION ${OPENFPGA_WITH_VERSION} CACHE BOOL "Enable version always-up-to-date when building codebase. Disable only when you do not care an accurate version number")
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set(WITH_PARMYS OFF CACHE BOOL "Enable Yosys as elaborator and parmys-plugin as partial mapper")
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# TODO: OpenFPGA and VPR has different requirements on no-warning build, e.g., on OS and compiler versions
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@ -1 +1 @@
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1.2.759
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1.2.799
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@ -40,7 +40,7 @@ create-task () {
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echo "Task $1 already exists"
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return
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fi
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template="template_tasks/yosys_vpr_template"
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template="template_tasks/fabric_netlist_gen_template"
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if [ ${#2} -ge 1 ]; then
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if [[ "$2" == "fabric_netlist_gen" ]]; then template="template_tasks/${2}_template/";
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elif [[ "$2" == "fabric_verification" ]]; then template="template_tasks/${2}_template/";
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@ -208,14 +208,15 @@ int annotate_simulation_setting(
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* - MUST mention in documentation that VPR should be run in timing
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* enabled mode
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*/
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ClbNetPinsMatrix<float> net_delay =
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make_net_pins_matrix<float>(cluster_ctx.clb_nlist);
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NetPinsMatrix<float> net_delay =
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make_net_pins_matrix<float>((const Netlist<>&)cluster_ctx.clb_nlist);
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/* Load the net delays */
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load_net_delay_from_routing(net_delay);
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load_net_delay_from_routing((const Netlist<>&)cluster_ctx.clb_nlist,
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net_delay, false);
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/* Do final timing analysis */
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auto analysis_delay_calc = std::make_shared<AnalysisDelayCalculator>(
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atom_ctx.nlist, atom_ctx.lookup, net_delay);
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atom_ctx.nlist, atom_ctx.lookup, net_delay, false);
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auto timing_info = make_setup_hold_timing_info(analysis_delay_calc,
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e_timing_update_type::FULL);
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timing_info->update();
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@ -22,12 +22,14 @@ void annotate_vpr_rr_node_nets(const DeviceContext& device_ctx,
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const RoutingContext& routing_ctx,
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VprRoutingAnnotation& vpr_routing_annotation,
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const bool& verbose) {
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vtr::vector<RRNodeId, ClusterNetId> node2net = annotate_rr_node_nets(
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device_ctx, clustering_ctx, routing_ctx, verbose, false);
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vtr::vector<RRNodeId, ParentNetId> node2net =
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annotate_rr_node_nets((const Netlist<>&)clustering_ctx.clb_nlist,
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device_ctx, routing_ctx, verbose, false);
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for (size_t node_id = 0; node_id < device_ctx.rr_graph.num_nodes();
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++node_id) {
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vpr_routing_annotation.set_rr_node_net(RRNodeId(node_id),
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node2net[RRNodeId(node_id)]);
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vpr_routing_annotation.set_rr_node_net(
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RRNodeId(node_id),
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convert_to_cluster_net_id(node2net[RRNodeId(node_id)]));
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}
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VTR_LOG("Loaded node-to-net mapping\n");
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}
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|
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@ -56,7 +56,7 @@ static void build_routing_arch_mux_library(
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if (CircuitModelId::INVALID() == rr_switch_circuit_model) {
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VTR_LOG_ERROR(
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"Unable to find the circuit model for rr_switch '%s'!\n",
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rr_graph.rr_switch_inf(driver_switches[0]).name);
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rr_graph.rr_switch_inf(driver_switches[0]).name.c_str());
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VTR_LOG("Node type: %s\n", rr_graph.node_type_string(node));
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VTR_LOG("Node coordinate: %s\n",
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rr_graph.node_coordinate_to_string(node).c_str());
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|
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|
@ -118,16 +118,20 @@ static int vpr_standalone(int argc, char** argv) {
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/* Read options, architecture, and circuit netlist */
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vpr_init(argc, const_cast<const char**>(argv), &Options, &vpr_setup, &Arch);
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const Netlist<>& net_list =
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vpr_setup.RouterOpts.flat_routing
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? (const Netlist<>&)g_vpr_ctx.atom().nlist
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: (const Netlist<>&)g_vpr_ctx.clustering().clb_nlist;
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if (Options.show_version) {
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vpr_free_all(Arch, vpr_setup);
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vpr_free_all(net_list, Arch, vpr_setup);
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return SUCCESS_EXIT_CODE;
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}
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|
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bool flow_succeeded = vpr_flow(vpr_setup, Arch);
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if (!flow_succeeded) {
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VTR_LOG("VPR failed to implement circuit\n");
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vpr_free_all(Arch, vpr_setup);
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vpr_free_all(net_list, Arch, vpr_setup);
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return UNIMPLEMENTABLE_EXIT_CODE;
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}
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|
@ -135,31 +139,43 @@ static int vpr_standalone(int argc, char** argv) {
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print_timing_stats("Flow", timing_ctx.stats);
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/* free data structures */
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vpr_free_all(Arch, vpr_setup);
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vpr_free_all(net_list, Arch, vpr_setup);
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VTR_LOG("VPR succeeded\n");
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|
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} catch (const tatum::Error& tatum_error) {
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VTR_LOG_ERROR("%s\n", format_tatum_error(tatum_error).c_str());
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vpr_free_all(Arch, vpr_setup);
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const Netlist<>& net_list =
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vpr_setup.RouterOpts.flat_routing
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? (const Netlist<>&)g_vpr_ctx.atom().nlist
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: (const Netlist<>&)g_vpr_ctx.clustering().clb_nlist;
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vpr_free_all(net_list, Arch, vpr_setup);
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return ERROR_EXIT_CODE;
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|
||||
} catch (const VprError& vpr_error) {
|
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vpr_print_error(vpr_error);
|
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const Netlist<>& net_list =
|
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vpr_setup.RouterOpts.flat_routing
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? (const Netlist<>&)g_vpr_ctx.atom().nlist
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: (const Netlist<>&)g_vpr_ctx.clustering().clb_nlist;
|
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|
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if (vpr_error.type() == VPR_ERROR_INTERRUPTED) {
|
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vpr_free_all(Arch, vpr_setup);
|
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vpr_free_all(net_list, Arch, vpr_setup);
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return INTERRUPTED_EXIT_CODE;
|
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} else {
|
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vpr_free_all(Arch, vpr_setup);
|
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vpr_free_all(net_list, Arch, vpr_setup);
|
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return ERROR_EXIT_CODE;
|
||||
}
|
||||
|
||||
} catch (const vtr::VtrError& vtr_error) {
|
||||
VTR_LOG_ERROR("%s:%d %s\n", vtr_error.filename_c_str(), vtr_error.line(),
|
||||
vtr_error.what());
|
||||
vpr_free_all(Arch, vpr_setup);
|
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const Netlist<>& net_list =
|
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vpr_setup.RouterOpts.flat_routing
|
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? (const Netlist<>&)g_vpr_ctx.atom().nlist
|
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: (const Netlist<>&)g_vpr_ctx.clustering().clb_nlist;
|
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vpr_free_all(net_list, Arch, vpr_setup);
|
||||
|
||||
return ERROR_EXIT_CODE;
|
||||
}
|
||||
|
|
|
@ -1 +1 @@
|
|||
Subproject commit 0f40ecba43479b0f830151adcecbf641fb2e9fe3
|
||||
Subproject commit d70659f424425dbaa6ecdb6dea40bf1841f02dac
|
2
yosys
2
yosys
|
@ -1 +1 @@
|
|||
Subproject commit b58664d441764b4de1d01c4efcdd45094ba71535
|
||||
Subproject commit a9c792dceef4be21059ff4732d1aff62e67d96bc
|
|
@ -1 +1 @@
|
|||
Subproject commit 35a3c3c2e4e85d08cc40713346bb296f1a0e44d1
|
||||
Subproject commit 96a0853eba5691f54a5e0bfc044d847743e09cef
|
Loading…
Reference in New Issue