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[core] debugging

This commit is contained in:
tangxifan 2023-03-03 16:56:20 -08:00
parent b009798ddb
commit 5a43b451c1
2 changed files with 5 additions and 1 deletions
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4
openfpga/src/annotation/append_clock_rr_graph.cpp
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@ -584,6 +584,7 @@ int append_clock_rr_graph(DeviceContext& vpr_device_ctx,
size_t orig_num_nodes = vpr_device_ctx.rr_graph.num_nodes();
size_t num_clock_nodes = estimate_clock_rr_graph_num_nodes(
vpr_device_ctx.grid, vpr_device_ctx.arch->through_channel, clk_ntwk);
vpr_device_ctx.rr_graph_builder.unlock_storage();
vpr_device_ctx.rr_graph_builder.reserve_nodes(num_clock_nodes +
orig_num_nodes);
@ -603,6 +604,9 @@ int append_clock_rr_graph(DeviceContext& vpr_device_ctx,
vpr_device_ctx.arch->through_channel, clk_ntwk);
/* TODO: Sanity checks */
vpr_device_ctx.rr_graph_builder.init_fan_in();
vpr_device_ctx.rr_graph_builder.partition_edges();
vpr_device_ctx.rr_graph_builder.build_in_edges();
/* Report number of added clock nodes and edges */
VTR_LOGV(verbose,

2
vtr-verilog-to-routing

@ -1 +1 @@
Subproject commit 52bd89f36ad5445aea3835c312ef56c2c18b2f9d
Subproject commit 5795b7df753903b215c1273cfe910113375f6aa8