[core] starting developing core function for clock rr_graph build-up

openfpga/src/annotation/append_clock_rr_graph.cpp

@@ -0,0 +1,21 @@
+#include "annotate_clock_rr_graph.h"
+#include "vtr_assert.h"
+#include "vtr_geometry.h"
+#include "vtr_log.h"
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+/********************************************************************
+ * Assign mapped blocks to grid locations
+ * This is used by bitstream generator mainly as a fast look-up to
+ * get mapped blocks with a given coordinate
+ *******************************************************************/
+int append_clock_rr_graph(DeviceContext& device_ctx,
+                          const ClockNetwork& clk_ntwk) {
+  VTR_LOG("Adding clock nodes to routing resource graph...");
+
+  VTR_LOG("Done\n");
+}
+
+} /* end namespace openfpga */

openfpga/src/annotation/append_clock_rr_graph.h

@@ -0,0 +1,22 @@
+#ifndef APPEND_CLOCK_RR_GRAPH_H
+#define APPEND_CLOCK_RR_GRAPH_H
+
+/********************************************************************
+ * Include header files that are required by function declaration
+ *******************************************************************/
+#include "vpr_context.h"
+#include "clock_network.h"
+
+/********************************************************************
+ * Function declaration
+ *******************************************************************/
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+int append_clock_rr_graph(DeviceContext& device_ctx,
+                          const ClockNetwork& clk_ntwk);
+
+} /* end namespace openfpga */
+
+#endif

openfpga/src/base/openfpga_link_arch_template.h

@@ -26,6 +26,7 @@
 #include "vtr_assert.h"
 #include "vtr_log.h"
 #include "vtr_time.h"
+#include "append_clock_rr_graph.h"
 
 /* begin namespace openfpga */
 namespace openfpga {
@@ -186,7 +187,7 @@ int link_arch_template(T& openfpga_ctx, const Command& cmd,
  * Top-level function to append a clock network to VPR's routing resource graph, including:
  * - Routing tracks dedicated to clock network
  * - Programmable switches to enable reconfigurability of clock network
- * - 
+ * - Adding virtual sources for clock signals 
  *******************************************************************/
 template <class T>
 int append_clock_rr_graph_template(T& openfpga_ctx, const Command& cmd,
@@ -196,9 +197,7 @@ int append_clock_rr_graph_template(T& openfpga_ctx, const Command& cmd,
 
   CommandOptionId opt_verbose = cmd.option("verbose");
 
-  /* TODO */
-
-  return CMD_EXEC_SUCCESS;
+  return append_clock_rr_graph(g_vpr_ctx.mutable_device(), openfpga_ctx.clock_arch());
 }