tangxifan
|
1bcb0d0868
|
[core] code format
|
2024-08-14 18:09:44 -07:00 |
|
tangxifan
|
4554c5781a
|
[core] fixed a bug where some clock spine was wrongly marked unused
|
2024-08-14 18:08:01 -07:00 |
|
tangxifan
|
c2d9696489
|
[core] fixed a bug where some spines are not disabled
|
2024-08-13 15:19:47 -07:00 |
|
tangxifan
|
ad13058a0b
|
[core] fixed a bug where unused last-level of clock spines are not disabled
|
2024-08-13 15:04:13 -07:00 |
Lin
|
755959a890
|
add cb cx write function
|
2024-08-08 02:54:02 -07:00 |
|
Lin
|
e45619b22d
|
write sb
|
2024-08-08 01:00:35 -07:00 |
|
Lin
|
9c67950a75
|
preload functions
|
2024-08-07 03:20:45 -07:00 |
|
Lin
|
72a90a4d8f
|
add preload function
|
2024-08-05 19:42:21 -07:00 |
|
Lin
|
c726744154
|
add sb unique modules
|
2024-08-05 02:23:47 -07:00 |
|
tangxifan
|
2e6b311d04
|
[core] add more details to debug messages
|
2024-08-02 18:33:43 -07:00 |
|
tangxifan
|
eeaa3373c6
|
[core] code format
|
2024-08-02 17:48:47 -07:00 |
|
tangxifan
|
82cf7bbb8c
|
[core] Add verbose mode on find_node() for clock rr graph
|
2024-08-02 17:47:41 -07:00 |
|
tangxifan
|
ef6b6f8e40
|
[core] remove warnings
|
2024-07-30 18:50:49 -07:00 |
|
tangxifan
|
853883cd36
|
[core] code format
|
2024-07-30 12:56:03 -07:00 |
|
tangxifan
|
234eee19ae
|
[core] revert
|
2024-07-30 12:29:32 -07:00 |
|
tangxifan
|
1513ea749b
|
[core] supporting clk spine on the same direction
|
2024-07-16 22:12:51 -07:00 |
|
tangxifan
|
c1f46c448a
|
[core] fixed a critical bug where clock network entry is on a CHANY
|
2024-07-16 17:04:44 -07:00 |
|
tangxifan
|
f607987386
|
[core] patch the out-of-range in clock rr nodes
|
2024-07-16 16:45:55 -07:00 |
|
tangxifan
|
c96f899c53
|
[core] code format
|
2024-07-10 15:07:26 -07:00 |
|
tangxifan
|
a4538fb25b
|
[core] now supports to_pin in building clock network for internal driver
|
2024-07-10 15:01:18 -07:00 |
|
tangxifan
|
213914e4ac
|
[core] code format
|
2024-07-10 12:23:57 -07:00 |
|
tangxifan
|
c6dd33a965
|
[core] fixed a bug when annotating global nets on OPIN
|
2024-07-10 11:59:25 -07:00 |
|
tangxifan
|
96bdcc8b35
|
[core] code format
|
2024-07-09 22:54:55 -07:00 |
|
tangxifan
|
27e29f949c
|
[core] fixed a bug where the pin idx of global net on rr graph is not well annotated
|
2024-07-09 22:53:12 -07:00 |
|
tangxifan
|
fe06c2f2b1
|
[core] code format
|
2024-07-08 16:18:58 -07:00 |
|
tangxifan
|
db459b0e87
|
[core] add verbose outputs
|
2024-07-08 16:18:32 -07:00 |
|
tangxifan
|
6dde383a7f
|
[core] debugging
|
2024-07-08 16:00:18 -07:00 |
|
tangxifan
|
8bca3d79be
|
[core] fixed a bug where tap points of clock network cannot reach perimeter cb
|
2024-07-08 15:17:24 -07:00 |
|
tangxifan
|
5c9c4d93c5
|
[core] typo
|
2024-07-08 10:46:47 -07:00 |
|
tangxifan
|
cdd477ad80
|
[core] remove restrictions on cb clock nodes
|
2024-07-08 10:14:39 -07:00 |
|
tangxifan
|
8449da0143
|
[core] typo
|
2024-07-07 23:36:13 -07:00 |
|
tangxifan
|
7996de3fe6
|
[core] now support perimeter cb in programmable clock network arch
|
2024-07-07 14:57:05 -07:00 |
|
tangxifan
|
703cbddc9e
|
[core] code format
|
2024-07-06 12:14:57 -07:00 |
|
tangxifan
|
283aa3a1c9
|
[core] debug
|
2024-07-05 12:21:17 -07:00 |
|
tangxifan
|
46e3b4b071
|
[core] debug
|
2024-07-05 11:50:41 -07:00 |
|
tangxifan
|
fdbc427f70
|
[core] debug
|
2024-07-05 11:17:05 -07:00 |
|
tangxifan
|
f6adca1545
|
[core] fixed a bug
|
2024-07-05 11:02:01 -07:00 |
|
tangxifan
|
1dc602a849
|
[core] syntax
|
2024-07-05 10:38:26 -07:00 |
|
tangxifan
|
266c2686d4
|
[core] adapt new gsb coordinate system
|
2024-07-05 10:32:33 -07:00 |
|
tangxifan
|
550ce0c390
|
[core] fixed the bug on build gsb when cbs are on perimeters
|
2024-07-04 10:58:44 -07:00 |
|
tangxifan
|
bc94e08c77
|
[lib] update vtr and fixing some bugs in annotate gsb when perimeter_cb is enabled
|
2024-07-03 22:28:22 -07:00 |
|
tangxifan
|
a27325d987
|
[core] code format
|
2024-07-03 17:05:27 -07:00 |
|
tangxifan
|
f681c6a903
|
[core] update API call due to vtr upgrade
|
2024-07-03 17:04:06 -07:00 |
|
tangxifan
|
3afb92d6a5
|
[core] code format
|
2024-06-30 22:48:15 -07:00 |
|
tangxifan
|
4f787a5cfc
|
[core] add more debugging message
|
2024-06-29 10:54:08 -07:00 |
|
tangxifan
|
5fa674be24
|
[core] fixed the bug on matching global net from pcf
|
2024-06-29 10:51:45 -07:00 |
|
tangxifan
|
8bc37080fa
|
[core] debuggging
|
2024-06-28 23:06:21 -07:00 |
|
tangxifan
|
1c69365938
|
[core] debugging
|
2024-06-28 18:17:38 -07:00 |
|
tangxifan
|
0de3ff3eb8
|
[core] debugging
|
2024-06-28 17:16:33 -07:00 |
|
tangxifan
|
e0b9f7860b
|
[core] fixed a bug where counter for gnets are not activated
|
2024-06-28 14:10:14 -07:00 |
|
tangxifan
|
5cfd23747b
|
[core] code format
|
2024-06-28 13:47:03 -07:00 |
|
tangxifan
|
f5b6774eb0
|
[core] add code comments and fixed some bugs
|
2024-06-28 12:21:33 -07:00 |
|
tangxifan
|
53ba2f0c29
|
[core] fixed a critical bug where some switching points are missing
|
2024-06-27 15:53:17 -07:00 |
|
tangxifan
|
5a7f618f29
|
[core] debugging
|
2024-06-27 15:44:17 -07:00 |
|
tangxifan
|
f4f487099d
|
[core] syntax
|
2024-06-27 15:07:48 -07:00 |
|
tangxifan
|
4185235a69
|
[core] now clock routing is based on tree expansion. Unused part can be disconnected
|
2024-06-27 15:02:20 -07:00 |
|
tangxifan
|
e75fd57af2
|
[core] refactor codes
|
2024-06-27 12:39:18 -07:00 |
|
tangxifan
|
7892c2340c
|
[core] add a new option 'disable_unused_trees' to route clock rr graph
|
2024-06-27 12:01:54 -07:00 |
|
tangxifan
|
6fceb81110
|
[core] code format
|
2024-06-27 10:19:40 -07:00 |
|
tangxifan
|
64a7a4ce26
|
[core] syntax
|
2024-06-27 10:19:14 -07:00 |
|
tangxifan
|
9ce552495a
|
[core] now internal drivers can be routed in dedicated clock network
|
2024-06-27 10:17:08 -07:00 |
|
tangxifan
|
ac1ad52795
|
[core] code format
|
2024-06-26 22:47:29 -07:00 |
|
tangxifan
|
5d0b0b9a8c
|
[core] now global nets mapping are applied to clock routing
|
2024-06-26 22:46:12 -07:00 |
|
tangxifan
|
d5d9531eec
|
[core] comment out buggy codes where global net mapping is not annotated in OpenFPGA
|
2024-06-26 21:52:45 -07:00 |
|
tangxifan
|
59be95b227
|
[core] code format
|
2024-06-26 17:58:26 -07:00 |
|
tangxifan
|
59404e5487
|
[core] add verbose output
|
2024-06-26 17:55:23 -07:00 |
|
tangxifan
|
576a861b8d
|
[core] now skip routing any unused clock tree. Only connect to desired clock pin at programmable blocks
|
2024-06-26 17:54:31 -07:00 |
|
tangxifan
|
3efa97b84e
|
[core] support coordinate on clock taps
|
2024-06-26 17:40:11 -07:00 |
|
tangxifan
|
fbece49047
|
[core] fixed a bug where unexpected OPINs are added as internal drivers
|
2024-06-25 12:07:19 -07:00 |
|
tangxifan
|
7bcbd8a88b
|
[core] code format
|
2024-06-25 11:44:50 -07:00 |
|
tangxifan
|
3b2c13402a
|
[core] syntax
|
2024-06-25 11:44:25 -07:00 |
|
tangxifan
|
31d4b4c402
|
[core] now support add internal drivers to clock tree
|
2024-06-25 11:27:22 -07:00 |
|
tangxifan
|
d2053db21c
|
[core] removing the restrictions on only 1 clock tree is supported in programmable clock network
|
2024-06-21 19:00:01 -07:00 |
|
tangxifan
|
3f08b83b3a
|
[core] remove restrictions on 1 clock tree definition
|
2024-06-21 17:12:10 -07:00 |
|
tangxifan
|
ecd31955b1
|
[core] code format
|
2024-06-21 17:11:32 -07:00 |
|
tangxifan
|
486cd01c15
|
[core] now clock graph builder supports two types of switches
|
2024-06-21 16:54:22 -07:00 |
|
tangxifan
|
74e94b855e
|
[core] fixed a bug where gsb OPIN name does not match the switch block module
|
2024-05-29 10:27:10 -07:00 |
|
tangxifan
|
ca6e2f9831
|
[core] code format
|
2024-05-20 13:41:35 -07:00 |
|
tangxifan
|
4a791249bf
|
[core] fixed a bug on requirement wire model for direction connection which is part of a cb
|
2024-05-20 12:52:07 -07:00 |
|
tangxifan
|
918bf79ca3
|
[core] update vtr and developing caches for OPIN lists just for connection blocks
|
2024-05-19 14:10:00 -07:00 |
|
tangxifan
|
717906ea17
|
[core] code format
|
2023-08-25 15:13:39 -07:00 |
|
tangxifan
|
89b392a51f
|
[core] adapt changes in is_sb_exist()
|
2023-08-25 15:13:00 -07:00 |
|
tangxifan
|
55e5f738ce
|
[core] code format
|
2023-08-25 11:58:15 -07:00 |
|
tangxifan
|
92f92658c9
|
[core] remove useless errors
|
2023-08-25 11:53:49 -07:00 |
|
tangxifan
|
399f087c50
|
[core] code format
|
2023-08-17 13:54:31 -07:00 |
|
tangxifan
|
414f7379c6
|
[core] fixed some bugs in debugging messages
|
2023-08-17 13:52:21 -07:00 |
|
tangxifan
|
788e3c17a9
|
[core] format
|
2023-08-08 23:02:20 -07:00 |
|
tangxifan
|
1c8c4fedbb
|
[core] fix memory leak
|
2023-08-08 23:01:52 -07:00 |
|
tangxifan
|
ff6fa1e90c
|
[core] fix memory leak
|
2023-08-08 22:41:43 -07:00 |
|
tangxifan
|
94d80a9b7c
|
[core] code format
|
2023-08-08 16:28:56 -07:00 |
|
tangxifan
|
867da98d3f
|
[core] update to use latest api from vpr upstream
|
2023-08-08 16:28:19 -07:00 |
|
tangxifan
|
beaa687a20
|
[core] fixed bugs on supporting heterogeneous blocks in tile modules
|
2023-07-27 20:29:18 -07:00 |
|
tangxifan
|
c2066cc63c
|
[core] fixed a bug where pb/cb/sb instance name is not assigned correctly in bitstream manager under tile modules
|
2023-07-27 13:33:23 -07:00 |
|
tangxifan
|
156cb800aa
|
[core] fixed a critical bug which causes wrong connections in tile modules
|
2023-07-27 12:22:16 -07:00 |
|
tangxifan
|
97219fd825
|
[core] add more verbose to help debug failed test cases
|
2023-07-26 23:26:11 -07:00 |
|
tangxifan
|
f5e8f175fb
|
[core] fixed a bug which causes flow failures when group_tile is not enabled
|
2023-07-25 21:27:58 -07:00 |
|
tangxifan
|
da36b735c6
|
[core] syntax
|
2023-07-24 12:13:45 -07:00 |
|
tangxifan
|
93c5a68592
|
[core] developing top-level nets for tiles
|
2023-07-21 23:21:53 -07:00 |
|
tangxifan
|
6b92299e39
|
[core] start working on the net build-up for tile instances under the top-level module
|
2023-07-20 17:38:13 -07:00 |
|
tangxifan
|
a06b9a0f48
|
[core] now start to develop the tile instances under the top module
|
2023-07-19 22:22:07 -07:00 |