[lib] add default seg/switch to clock arch. Fixed syntax
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ee0459d729
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7f07a9d031
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@ -21,6 +21,7 @@ set_target_properties(libclkarchopenfpga PROPERTIES PREFIX "") #Avoid extra 'lib
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target_link_libraries(libclkarchopenfpga
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libopenfpgautil
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libarchopenfpga
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librrgraph
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libvtrutil
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libpugiutil)
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@ -1,4 +1,4 @@
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<clock_networks>
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<clock_networks default_segment="seg_len1" default_switch="fast_switch">
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<clock_network name="example_network" width="8">
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<spine name="spine_lvl3" start_x="0" start_y="2" end_x="2" end_y="2">
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<switch_point tap="spine_lvl2_upper" x="2" y="2"/>
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@ -19,6 +19,8 @@ ClockNetwork::ClockNetwork() { is_dirty_ = true; }
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/************************************************************************
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* Public Accessors : aggregates
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***********************************************************************/
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size_t ClockNetwork::num_trees() const { return trees().size(); }
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ClockNetwork::clock_tree_range ClockNetwork::trees() const {
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return vtr::make_range(tree_ids_.begin(), tree_ids_.end());
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}
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@ -26,6 +28,14 @@ ClockNetwork::clock_tree_range ClockNetwork::trees() const {
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/************************************************************************
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* Public Accessors : Basic data query
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***********************************************************************/
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std::string ClockNetwork::default_segment_name() const {
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return default_segment_name_;
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}
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std::string ClockNetwork::default_switch_name() const {
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return default_switch_name_;
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}
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std::string ClockNetwork::tree_name(const ClockTreeId& tree_id) const {
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VTR_ASSERT(valid_tree_id(tree_id));
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return tree_names_[tree_id];
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@ -134,6 +144,14 @@ void ClockNetwork::reserve_trees(const size_t& num_trees) {
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tree_top_spines_.reserve(num_trees);
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}
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void ClockNetwork::set_default_segment_name(const std::string& name) {
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default_segment_name_ = name;
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}
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void ClockNetwork::set_default_switch_name(const std::string& name) {
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default_switch_name_ = name;
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}
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ClockTreeId ClockNetwork::create_tree(const std::string& name, size_t width) {
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/* Create a new id */
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ClockTreeId tree_id = ClockTreeId(tree_ids_.size());
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@ -14,7 +14,7 @@
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/* Headers from openfpgautil library */
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#include "clock_network_fwd.h"
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#include "openfpga_port.h"
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#include "rr_graph_fwd.h"
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namespace openfpga { // Begin namespace openfpga
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@ -46,11 +46,14 @@ class ClockNetwork {
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ClockNetwork();
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public: /* Accessors: aggregates */
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size_t num_trees() const;
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clock_tree_range trees() const;
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/* Return a list of spine id under a clock tree */
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std::vector<ClockSpineId> spines(const ClockTreeId& tree_id) const;
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public: /* Public Accessors: Basic data query */
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std::string default_segment_name() const;
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std::string default_switch_name() const;
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std::string tree_name(const ClockTreeId& tree_id) const;
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size_t tree_width(const ClockTreeId& tree_id) const;
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size_t tree_depth(const ClockTreeId& tree_id) const;
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@ -78,6 +81,8 @@ class ClockNetwork {
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void reserve_spines(const size_t& num_spines);
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/* Reserve a number of trees to be memory efficent */
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void reserve_trees(const size_t& num_trees);
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void set_default_segment_name(const std::string& name);
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void set_default_switch_name(const std::string& name);
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/* Create a new tree, by default the tree can accomodate only 1 clock signal;
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* use width to adjust the size */
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ClockTreeId create_tree(const std::string& name, size_t width = 1);
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@ -142,6 +147,14 @@ class ClockNetwork {
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vtr::vector<ClockSpineId, std::vector<ClockSpineId>> spine_children_;
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vtr::vector<ClockSpineId, ClockTreeId> spine_parent_trees_;
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/* Default routing resource */
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std::string default_segment_name_; /* The routing segment representing the
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clock wires */
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RRSegmentId default_segment_id_;
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std::string
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default_switch_name_; /* The routing switch interconnecting clock wire */
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RRSwitchId default_switch_id_;
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/* Fast lookup */
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std::map<std::string, ClockTreeId> tree_name2id_map_;
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std::map<std::string, ClockSpineId> spine_name2id_map_;
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@ -4,6 +4,10 @@
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/* Constants required by XML parser */
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constexpr const char* XML_CLOCK_NETWORK_ROOT_NAME = "clock_networks";
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constexpr const char* XML_CLOCK_NETWORK_ATTRIBUTE_DEFAULT_SEGMENT =
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"default_segment";
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constexpr const char* XML_CLOCK_NETWORK_ATTRIBUTE_DEFAULT_SWITCH =
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"default_switch";
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constexpr const char* XML_CLOCK_TREE_NODE_NAME = "clock_network";
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constexpr const char* XML_CLOCK_TREE_ATTRIBUTE_NAME = "name";
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constexpr const char* XML_CLOCK_TREE_ATTRIBUTE_WIDTH = "width";
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@ -167,6 +167,18 @@ ClockNetwork read_xml_clock_network(const char* fname) {
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pugi::xml_node xml_root =
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get_single_child(doc, XML_CLOCK_NETWORK_ROOT_NAME, loc_data);
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std::string default_segment_name =
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get_attribute(xml_root, XML_CLOCK_NETWORK_ATTRIBUTE_DEFAULT_SEGMENT,
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loc_data)
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.as_string();
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clk_ntwk.set_default_segment_name(default_segment_name);
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std::string default_switch_name =
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get_attribute(xml_root, XML_CLOCK_NETWORK_ATTRIBUTE_DEFAULT_SWITCH,
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loc_data)
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.as_string();
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clk_ntwk.set_default_switch_name(default_switch_name);
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size_t num_trees =
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std::distance(xml_root.children().begin(), xml_root.children().end());
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@ -135,7 +135,12 @@ int write_xml_clock_network(const char* fname, const ClockNetwork& clk_ntwk) {
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openfpga::check_file_stream(fname, fp);
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/* Write the root node */
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fp << "<" << XML_CLOCK_NETWORK_ROOT_NAME << ">"
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fp << "<" << XML_CLOCK_NETWORK_ROOT_NAME;
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write_xml_attribute(fp, XML_CLOCK_NETWORK_ATTRIBUTE_DEFAULT_SEGMENT,
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clk_ntwk.default_segment_name().c_str());
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write_xml_attribute(fp, XML_CLOCK_NETWORK_ATTRIBUTE_DEFAULT_SWITCH,
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clk_ntwk.default_switch_name().c_str());
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fp << ">"
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<< "\n";
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int err_code = 0;
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@ -1,8 +1,10 @@
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#include "annotate_clock_rr_graph.h"
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#include "append_clock_rr_graph.h"
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#include "command_exit_codes.h"
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#include "vtr_assert.h"
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#include "vtr_geometry.h"
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#include "vtr_log.h"
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#include "command_exit_codes.h"
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#include "vtr_time.h"
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/* begin namespace openfpga */
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namespace openfpga {
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@ -13,47 +15,26 @@ namespace openfpga {
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* get mapped blocks with a given coordinate
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*******************************************************************/
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int append_clock_rr_graph(DeviceContext& vpr_device_ctx,
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const ClockNetwork& clk_ntwk,
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const bool& verbose) {
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vtr::ScopedStartFinishTimer timer("Adding clock nodes to routing resource graph");
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const ClockNetwork& clk_ntwk, const bool& verbose) {
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vtr::ScopedStartFinishTimer timer(
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"Appending programmable clock network to routing resource graph");
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/* Skip if there is no clock tree */
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if (clk_ntwk.num_trees()) {
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VTR_LOG("Skip due to 0 clock trees.\nDouble check your clock architecture definition if this is unexpected\n");
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VTR_LOG(
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"Skip due to 0 clock trees.\nDouble check your clock architecture "
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"definition if this is unexpected\n");
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return CMD_EXEC_SUCCESS;
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}
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/* Walk through the GSB array and add clock nodes to each GSB.
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* Note that the GSB array is smaller than the grids by 1 column and 1 row!!!
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*/
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vtr::Point<size_t> gsb_range(vpr_device_ctx.grid.width() - 1,
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vpr_device_ctx.grid.height() - 1);
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size_t num_clock_nodes = 0;
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size_t num_clock_edges = 0;
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size_t gsb_cnt = 0;
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/* For each switch block, determine the size of array */
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for (size_t ix = 0; ix < gsb_range.x(); ++ix) {
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for (size_t iy = 0; iy < gsb_range.y(); ++iy) {
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/* Here we give the builder the fringe coordinates so that it can handle
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* the GSBs at the borderside correctly sort drive_rr_nodes should be
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* called if required by users
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*/
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const RRGSB& rr_gsb =
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build_rr_gsb(vpr_device_ctx,
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vtr::Point<size_t>(vpr_device_ctx.grid.width() - 2,
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vpr_device_ctx.grid.height() - 2),
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vtr::Point<size_t>(ix, iy));
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/* Add clock nodes to device_rr_gsb */
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vtr::Point<size_t> gsb_coordinate = rr_gsb.get_sb_coordinate();
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gsb_cnt++; /* Update counter */
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/* Print info */
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VTR_LOGV(verbose, "[%lu%] Added clock nodes to GSB[%lu][%lu]\r",
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100 * gsb_cnt / (gsb_range.x() * gsb_range.y()), ix, iy);
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}
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}
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/* Report number of added clock nodes and edges */
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VTR_LOGV(verbose, "Appended clock nodes to %d General Switch Blocks (GSBs).\n",
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gsb_range.x() * gsb_range.y());
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VTR_LOGV(
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verbose,
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"Appended %lu clock nodes and %lu clock edges to routing resource graph.\n",
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num_clock_nodes, num_clock_edges);
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return CMD_EXEC_SUCCESS;
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}
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@ -4,8 +4,8 @@
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/********************************************************************
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* Include header files that are required by function declaration
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*******************************************************************/
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#include "vpr_context.h"
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#include "clock_network.h"
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#include "vpr_context.h"
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/********************************************************************
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* Function declaration
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namespace openfpga {
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int append_clock_rr_graph(DeviceContext& vpr_device_ctx,
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const ClockNetwork& clk_ntwk,
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const bool& verbose);
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const ClockNetwork& clk_ntwk, const bool& verbose);
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} /* end namespace openfpga */
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@ -12,6 +12,7 @@
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#include "annotate_placement.h"
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#include "annotate_rr_graph.h"
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#include "annotate_simulation_setting.h"
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#include "append_clock_rr_graph.h"
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#include "build_tile_direct.h"
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#include "command.h"
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#include "command_context.h"
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#include "vtr_assert.h"
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#include "vtr_log.h"
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#include "vtr_time.h"
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#include "append_clock_rr_graph.h"
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/* begin namespace openfpga */
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namespace openfpga {
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@ -184,10 +184,11 @@ int link_arch_template(T& openfpga_ctx, const Command& cmd,
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}
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/********************************************************************
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* Top-level function to append a clock network to VPR's routing resource graph, including:
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* Top-level function to append a clock network to VPR's routing resource graph,
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*including:
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* - Routing tracks dedicated to clock network
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* - Programmable switches to enable reconfigurability of clock network
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* - Adding virtual sources for clock signals
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* - Adding virtual sources for clock signals
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*******************************************************************/
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template <class T>
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int append_clock_rr_graph_template(T& openfpga_ctx, const Command& cmd,
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@ -197,10 +198,11 @@ int append_clock_rr_graph_template(T& openfpga_ctx, const Command& cmd,
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CommandOptionId opt_verbose = cmd.option("verbose");
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return append_clock_rr_graph(g_vpr_ctx.mutable_device(), openfpga_ctx.clock_arch(), cmd_context.option_enable(cmd, opt_verbose));
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return append_clock_rr_graph(g_vpr_ctx.mutable_device(),
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openfpga_ctx.clock_arch(),
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cmd_context.option_enable(cmd, opt_verbose));
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}
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} /* end namespace openfpga */
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#endif
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@ -645,10 +645,10 @@ ShellCommandId add_append_clock_rr_graph_command_template(
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/* Add command 'pb_pin_fixup' to the Shell */
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ShellCommandId shell_cmd_id = shell.add_command(
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shell_cmd,
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"Append clock network to the routing resource graph built by VPR.",
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hidden);
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"Append clock network to the routing resource graph built by VPR.", hidden);
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shell.set_command_class(shell_cmd_id, cmd_class_id);
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shell.set_command_execute_function(shell_cmd_id, append_clock_rr_graph_template<T>);
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shell.set_command_execute_function(shell_cmd_id,
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append_clock_rr_graph_template<T>);
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/* Add command dependency to the Shell */
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shell.set_command_dependency(shell_cmd_id, dependent_cmds);
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/* The 'append_clock_rr_graph' command should NOT be executed before
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* 'read_openfpga_clock_arch' */
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std::vector<ShellCommandId> append_clock_rr_graph_dependent_cmds;
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append_clock_rr_graph_dependent_cmds.push_back(read_openfpga_clock_arch_cmd_id);
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add_append_clock_rr_graph_command_template<T>(shell, openfpga_setup_cmd_class,
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append_clock_rr_graph_dependent_cmds, hidden);
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append_clock_rr_graph_dependent_cmds.push_back(
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read_openfpga_clock_arch_cmd_id);
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add_append_clock_rr_graph_command_template<T>(
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shell, openfpga_setup_cmd_class, append_clock_rr_graph_dependent_cmds,
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hidden);
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/********************************
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* Command 'write_gsb'
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