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[core] fixed a bug where clock tracks do not pass through at higher level

This commit is contained in:
tangxifan 2023-03-07 15:05:56 -08:00
parent 50e201feeb
commit 11f09db556
1 changed files with 2 additions and 2 deletions
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4
openfpga/src/annotation/append_clock_rr_graph.cpp
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@ -515,8 +515,8 @@ static void add_rr_graph_block_clock_edges(
size_t(itree), size_t(ilvl), size_t(ipin),
DIRECTION_STRING[size_t(node_dir)]);
VTR_ASSERT(rr_graph_view.valid_node(src_node));
if (!clk_ntwk.is_last_level(itree, ilvl)) {
/* find the fan-out clock node through lookup */
/* find the fan-out clock node through lookup */
{
size_t curr_edge_count = edge_count;
for (RRNodeId des_node : find_clock_track2track_node(
rr_graph_view, clk_ntwk, clk_rr_lookup, chan_type,