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[core] code format

This commit is contained in:
tangxifan 2023-02-27 23:00:15 -08:00
parent 2735b708d3
commit 8d5c21b14d
7 changed files with 137 additions and 103 deletions
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30
libs/libclkarchopenfpga/src/base/clock_network.cpp
View File

@ -2,10 +2,10 @@
#include <algorithm>
#include "openfpga_port_parser.h"
#include "openfpga_tokenizer.h"
#include "vtr_assert.h"
#include "vtr_log.h"
#include "openfpga_tokenizer.h"
#include "openfpga_port_parser.h"
namespace openfpga { // Begin namespace openfpga
@ -232,19 +232,22 @@ vtr::Point<int> ClockNetwork::spine_switch_point(
return spine_switch_coords_[spine_id][size_t(switch_point_id)];
}
std::vector<std::string> ClockNetwork::tree_taps(const ClockTreeId& tree_id) const {
std::vector<std::string> ClockNetwork::tree_taps(
const ClockTreeId& tree_id) const {
VTR_ASSERT(valid_tree_id(tree_id));
return tree_taps_[tree_id];
}
std::vector<std::string> ClockNetwork::tree_flatten_taps(const ClockTreeId& tree_id, const ClockTreePinId& clk_pin_id) const {
std::vector<std::string> ClockNetwork::tree_flatten_taps(
const ClockTreeId& tree_id, const ClockTreePinId& clk_pin_id) const {
VTR_ASSERT(valid_tree_id(tree_id));
std::vector<std::string> flatten_taps;
for (const std::string& tap_name : tree_taps_[tree_id]) {
StringToken tokenizer(tap_name);
std::vector<std::string> pin_tokens = tokenizer.split(".");
if (pin_tokens.size() != 2) {
VTR_LOG_ERROR("Invalid pin name '%s'. Expect <tile>.<port>\n", tap_name.c_str());
VTR_LOG_ERROR("Invalid pin name '%s'. Expect <tile>.<port>\n",
tap_name.c_str());
exit(1);
}
PortParser tile_parser(pin_tokens[0]);
@ -252,23 +255,27 @@ std::vector<std::string> ClockNetwork::tree_flatten_taps(const ClockTreeId& tree
PortParser pin_parser(pin_tokens[1]);
BasicPort pin_info = pin_parser.port();
if (!tile_info.is_valid()) {
VTR_LOG_ERROR("Invalid pin name '%s' whose subtile index is not valid\n", tap_name.c_str());
VTR_LOG_ERROR("Invalid pin name '%s' whose subtile index is not valid\n",
tap_name.c_str());
exit(1);
}
if (!pin_info.is_valid()) {
VTR_LOG_ERROR("Invalid pin name '%s' whose pin index is not valid\n", tap_name.c_str());
VTR_LOG_ERROR("Invalid pin name '%s' whose pin index is not valid\n",
tap_name.c_str());
exit(1);
}
for (size_t& tile_idx : tile_info.pins()) {
std::string flatten_tile_str = tile_info.get_name() + "[" + std::to_string(tile_idx) + "]";
std::string flatten_tile_str =
tile_info.get_name() + "[" + std::to_string(tile_idx) + "]";
for (size_t& pin_idx : pin_info.pins()) {
if (pin_idx != size_t(clk_pin_id)) {
continue;
}
std::string flatten_pin_str = pin_info.get_name() + "[" + std::to_string(pin_idx) + "]";
std::string flatten_pin_str =
pin_info.get_name() + "[" + std::to_string(pin_idx) + "]";
flatten_taps.push_back(flatten_tile_str + "." + flatten_pin_str);
}
}
}
}
return flatten_taps;
}
@ -433,7 +440,8 @@ void ClockNetwork::add_spine_switch_point(const ClockSpineId& spine_id,
spine_children_[spine_id].push_back(drive_spine_id);
}
void ClockNetwork::add_tree_tap(const ClockTreeId& tree_id, const std::string& pin_name) {
void ClockNetwork::add_tree_tap(const ClockTreeId& tree_id,
const std::string& pin_name) {
VTR_ASSERT(valid_tree_id(tree_id));
tree_taps_[tree_id].push_back(pin_name);
}

15
libs/libclkarchopenfpga/src/base/clock_network.h
View File

@ -104,14 +104,15 @@ class ClockNetwork {
vtr::Point<int> spine_switch_point(
const ClockSpineId& spine_id,
const ClockSwitchPointId& switch_point_id) const;
/* Return the original list of tap pins that is in storage; useful for parsers */
std::vector<std::string> tree_taps(const ClockTreeId& tree_id) const;
/* Return the list of flatten tap pins. For example: clb[0:1].clk[2:2] is flatten to
* { clb[0].clk[2], clb[1].clk[2] }
* Useful to build clock routing resource graph
* Note that the clk_pin_id limits only 1 clock to be accessed
/* Return the original list of tap pins that is in storage; useful for parsers
*/
std::vector<std::string> tree_flatten_taps(const ClockTreeId& tree_id, const ClockTreePinId& clk_pin_id) const;
std::vector<std::string> tree_taps(const ClockTreeId& tree_id) const;
/* Return the list of flatten tap pins. For example: clb[0:1].clk[2:2] is
* flatten to { clb[0].clk[2], clb[1].clk[2] } Useful to build clock routing
* resource graph Note that the clk_pin_id limits only 1 clock to be accessed
*/
std::vector<std::string> tree_flatten_taps(
const ClockTreeId& tree_id, const ClockTreePinId& clk_pin_id) const;
/* Find a spine with a given name, if not found, return an valid id, otherwise
* return an invalid one */
ClockSpineId find_spine(const std::string& name) const;

33
libs/libclkarchopenfpga/src/io/read_xml_clock_network.cpp
View File

@ -27,34 +27,31 @@ namespace openfpga { // Begin namespace openfpga
/********************************************************************
* Parse XML codes of a <tap> to an object of ClockNetwork
*******************************************************************/
static void read_xml_clock_tree_tap(
pugi::xml_node& xml_tap, const pugiutil::loc_data& loc_data,
ClockNetwork& clk_ntwk, const ClockTreeId& tree_id) {
static void read_xml_clock_tree_tap(pugi::xml_node& xml_tap,
const pugiutil::loc_data& loc_data,
ClockNetwork& clk_ntwk,
const ClockTreeId& tree_id) {
if (!clk_ntwk.valid_tree_id(tree_id)) {
archfpga_throw(loc_data.filename_c_str(), loc_data.line(xml_tap),
"Invalid id of a clock tree!\n");
}
std::string tile_pin_name =
get_attribute(xml_tap, XML_CLOCK_TREE_TAP_ATTRIBUTE_TILE_PIN,
loc_data)
get_attribute(xml_tap, XML_CLOCK_TREE_TAP_ATTRIBUTE_TILE_PIN, loc_data)
.as_string();
clk_ntwk.add_tree_tap(tree_id, tile_pin_name);
}
static void read_xml_clock_tree_taps(
pugi::xml_node& xml_taps, const pugiutil::loc_data& loc_data,
ClockNetwork& clk_ntwk, const ClockTreeId& tree_id) {
static void read_xml_clock_tree_taps(pugi::xml_node& xml_taps,
const pugiutil::loc_data& loc_data,
ClockNetwork& clk_ntwk,
const ClockTreeId& tree_id) {
for (pugi::xml_node xml_tap : xml_taps.children()) {
/* Error out if the XML child has an invalid name! */
if (xml_tap.name() ==
std::string(XML_CLOCK_TREE_TAP_NODE_NAME)) {
read_xml_clock_tree_tap(xml_tap, loc_data, clk_ntwk,
tree_id);
if (xml_tap.name() == std::string(XML_CLOCK_TREE_TAP_NODE_NAME)) {
read_xml_clock_tree_tap(xml_tap, loc_data, clk_ntwk, tree_id);
} else {
bad_tag(xml_taps, loc_data, xml_tap,
{XML_CLOCK_TREE_TAP_NODE_NAME});
bad_tag(xml_taps, loc_data, xml_tap, {XML_CLOCK_TREE_TAP_NODE_NAME});
}
}
}
@ -180,11 +177,11 @@ static void read_xml_clock_tree(pugi::xml_node& xml_clk_tree,
/* Error out if the XML child has an invalid name! */
if (xml_spine.name() == std::string(XML_CLOCK_SPINE_NODE_NAME)) {
read_xml_clock_spine(xml_spine, loc_data, clk_ntwk, tree_id);
} else if (xml_spine.name() ==
std::string(XML_CLOCK_TREE_TAPS_NODE_NAME)) {
} else if (xml_spine.name() == std::string(XML_CLOCK_TREE_TAPS_NODE_NAME)) {
read_xml_clock_tree_taps(xml_spine, loc_data, clk_ntwk, tree_id);
} else {
bad_tag(xml_spine, loc_data, xml_clk_tree, {XML_CLOCK_SPINE_NODE_NAME, XML_CLOCK_TREE_TAPS_NODE_NAME});
bad_tag(xml_spine, loc_data, xml_clk_tree,
{XML_CLOCK_SPINE_NODE_NAME, XML_CLOCK_TREE_TAPS_NODE_NAME});
}
}
}

10
libs/libclkarchopenfpga/src/io/write_xml_clock_network.cpp
View File

@ -23,17 +23,17 @@
namespace openfpga { // Begin namespace openfpga
static int write_xml_clock_tree_taps(
std::fstream& fp, const ClockNetwork& clk_ntwk, const ClockTreeId& tree_id) {
static int write_xml_clock_tree_taps(std::fstream& fp,
const ClockNetwork& clk_ntwk,
const ClockTreeId& tree_id) {
openfpga::write_tab_to_file(fp, 3);
fp << "<" << XML_CLOCK_TREE_TAPS_NODE_NAME << ">\n";
for (const std::string& tile_pin_name : clk_ntwk.tree_taps(tree_id)) {
openfpga::write_tab_to_file(fp, 4);
fp << "<" << XML_CLOCK_TREE_TAP_NODE_NAME << "";
write_xml_attribute(
fp, XML_CLOCK_TREE_TAP_ATTRIBUTE_TILE_PIN,
tile_pin_name.c_str());
write_xml_attribute(fp, XML_CLOCK_TREE_TAP_ATTRIBUTE_TILE_PIN,
tile_pin_name.c_str());
fp << "/>"
<< "\n";
}

96
openfpga/src/annotation/append_clock_rr_graph.cpp
View File

@ -1,13 +1,13 @@
#include "append_clock_rr_graph.h"
#include "command_exit_codes.h"
#include "openfpga_physical_tile_utils.h"
#include "rr_graph_builder_utils.h"
#include "rr_graph_cost.h"
#include "vtr_assert.h"
#include "vtr_geometry.h"
#include "vtr_log.h"
#include "vtr_time.h"
#include "openfpga_physical_tile_utils.h"
/* begin namespace openfpga */
namespace openfpga {
@ -166,8 +166,8 @@ static void add_rr_graph_clock_nodes(RRGraphBuilder& rr_graph_builder,
}
/********************************************************************
* Find the destination CHANX|CHANY nodes for a driver clock node in a given connection
*block There are two types of destination nodes:
* Find the destination CHANX|CHANY nodes for a driver clock node in a given
*connection block There are two types of destination nodes:
* - Straight connection where the driver clock node connects to another clock
*node in the same direction and at the same level as well as clock index For
*example
@ -350,26 +350,25 @@ static std::vector<RRNodeId> find_clock_track2track_node(
/********************************************************************
* Try to find an IPIN of a grid which satisfy the requirement of clock pins
* that has been defined in clock network. If the IPIN does exist in a
* that has been defined in clock network. If the IPIN does exist in a
* routing resource graph, add it to the node list
*******************************************************************/
static
void try_find_and_add_clock_track2ipin_node(std::vector<RRNodeId>& des_nodes,
const DeviceGrid& grids,
const RRGraphView& rr_graph_view,
const vtr::Point<size_t>& grid_coord,
const e_side& pin_side,
const ClockNetwork& clk_ntwk,
const ClockTreeId& clk_tree,
const ClockTreePinId& clk_pin) {
t_physical_tile_type_ptr grid_type = grids[grid_coord.x()][grid_coord.y()].type;
for (std::string tap_pin_name : clk_ntwk.tree_flatten_taps(clk_tree, clk_pin)) {
static void try_find_and_add_clock_track2ipin_node(
std::vector<RRNodeId>& des_nodes, const DeviceGrid& grids,
const RRGraphView& rr_graph_view, const vtr::Point<size_t>& grid_coord,
const e_side& pin_side, const ClockNetwork& clk_ntwk,
const ClockTreeId& clk_tree, const ClockTreePinId& clk_pin) {
t_physical_tile_type_ptr grid_type =
grids[grid_coord.x()][grid_coord.y()].type;
for (std::string tap_pin_name :
clk_ntwk.tree_flatten_taps(clk_tree, clk_pin)) {
/* tap pin name could be 'io[5:5].a2f[0]' */
int grid_pin_idx = find_physical_tile_pin_index(grid_type, tap_pin_name);
if (grid_pin_idx == grid_type->num_pins) {
continue;
}
RRNodeId des_node = rr_graph_view.node_lookup().find_node(grid_coord.x(), grid_coord.y(), IPIN, grid_pin_idx, pin_side);
RRNodeId des_node = rr_graph_view.node_lookup().find_node(
grid_coord.x(), grid_coord.y(), IPIN, grid_pin_idx, pin_side);
if (rr_graph_view.valid_node(des_node)) {
des_nodes.push_back(des_node);
}
@ -378,11 +377,10 @@ void try_find_and_add_clock_track2ipin_node(std::vector<RRNodeId>& des_nodes,
/********************************************************************
* Find the destination IPIN nodes for a driver clock node in a given connection
*block.
* For CHANX, the IPIN nodes are typically on the BOTTOM and TOP sides of adjacent grids
* For CHANY, the IPIN nodes are typically on the LEFT and RIGHT sides of adjacent grids
* For example
* Grid[1][2]
*block.
* For CHANX, the IPIN nodes are typically on the BOTTOM and TOP sides of
*adjacent grids For CHANY, the IPIN nodes are typically on the LEFT and RIGHT
*sides of adjacent grids For example Grid[1][2]
* ^
* |
* clk0_lvl2_chanx[1][1] -->---------+
@ -403,32 +401,38 @@ void try_find_and_add_clock_track2ipin_node(std::vector<RRNodeId>& des_nodes,
* | [x][y] | [x][y] | [x+1][y] |
* +----------+----------+------------+
*******************************************************************/
static std::vector<RRNodeId> find_clock_track2ipin_node(const DeviceGrid& grids,
const RRGraphView& rr_graph_view,
const t_rr_type& chan_type,
const vtr::Point<size_t>& chan_coord,
const ClockNetwork& clk_ntwk,
const ClockTreeId& clk_tree,
const ClockTreePinId& clk_pin) {
static std::vector<RRNodeId> find_clock_track2ipin_node(
const DeviceGrid& grids, const RRGraphView& rr_graph_view,
const t_rr_type& chan_type, const vtr::Point<size_t>& chan_coord,
const ClockNetwork& clk_ntwk, const ClockTreeId& clk_tree,
const ClockTreePinId& clk_pin) {
std::vector<RRNodeId> des_nodes;
if (chan_type == CHANX) {
/* Get the clock IPINs at the BOTTOM side of adjacent grids [x][y+1] */
vtr::Point<size_t> bot_grid_coord(chan_coord.x(), chan_coord.y() + 1);
try_find_and_add_clock_track2ipin_node(des_nodes, grids, rr_graph_view, bot_grid_coord, BOTTOM, clk_ntwk, clk_tree, clk_pin);
try_find_and_add_clock_track2ipin_node(des_nodes, grids, rr_graph_view,
bot_grid_coord, BOTTOM, clk_ntwk,
clk_tree, clk_pin);
/* Get the clock IPINs at the TOP side of adjacent grids [x][y] */
vtr::Point<size_t> top_grid_coord(chan_coord.x(), chan_coord.y());
try_find_and_add_clock_track2ipin_node(des_nodes, grids, rr_graph_view, top_grid_coord, TOP, clk_ntwk, clk_tree, clk_pin);
try_find_and_add_clock_track2ipin_node(des_nodes, grids, rr_graph_view,
top_grid_coord, TOP, clk_ntwk,
clk_tree, clk_pin);
} else {
VTR_ASSERT(chan_type == CHANY);
/* Get the clock IPINs at the LEFT side of adjacent grids [x][y+1] */
vtr::Point<size_t> left_grid_coord(chan_coord.x() + 1, chan_coord.y());
try_find_and_add_clock_track2ipin_node(des_nodes, grids, rr_graph_view, left_grid_coord, LEFT, clk_ntwk, clk_tree, clk_pin);
try_find_and_add_clock_track2ipin_node(des_nodes, grids, rr_graph_view,
left_grid_coord, LEFT, clk_ntwk,
clk_tree, clk_pin);
/* Get the clock IPINs at the RIGHT side of adjacent grids [x][y] */
vtr::Point<size_t> right_grid_coord(chan_coord.x(), chan_coord.y());
try_find_and_add_clock_track2ipin_node(des_nodes, grids, rr_graph_view, right_grid_coord, RIGHT, clk_ntwk, clk_tree, clk_pin);
try_find_and_add_clock_track2ipin_node(des_nodes, grids, rr_graph_view,
right_grid_coord, RIGHT, clk_ntwk,
clk_tree, clk_pin);
}
return des_nodes;
@ -437,14 +441,11 @@ static std::vector<RRNodeId> find_clock_track2ipin_node(const DeviceGrid& grids,
/********************************************************************
* Add edges for the clock nodes in a given connection block
*******************************************************************/
static void add_rr_graph_block_clock_edges(RRGraphBuilder& rr_graph_builder,
size_t& num_edges_to_create,
const RRClockSpatialLookup& clk_rr_lookup,
const RRGraphView& rr_graph_view,
const DeviceGrid& grids,
const ClockNetwork& clk_ntwk,
const vtr::Point<size_t> chan_coord,
const t_rr_type& chan_type) {
static void add_rr_graph_block_clock_edges(
RRGraphBuilder& rr_graph_builder, size_t& num_edges_to_create,
const RRClockSpatialLookup& clk_rr_lookup, const RRGraphView& rr_graph_view,
const DeviceGrid& grids, const ClockNetwork& clk_ntwk,
const vtr::Point<size_t> chan_coord, const t_rr_type& chan_type) {
size_t edge_count = 0;
for (auto itree : clk_ntwk.trees()) {
for (auto ilvl : clk_ntwk.levels(itree)) {
@ -457,8 +458,8 @@ static void add_rr_graph_block_clock_edges(RRGraphBuilder& rr_graph_builder,
if (!clk_ntwk.is_last_level(itree, ilvl)) {
/* find the fan-out clock node through lookup */
for (RRNodeId des_node : find_clock_track2track_node(
rr_graph_view, clk_ntwk, clk_rr_lookup, chan_type, chan_coord,
itree, ilvl, ipin, node_dir)) {
rr_graph_view, clk_ntwk, clk_rr_lookup, chan_type,
chan_coord, itree, ilvl, ipin, node_dir)) {
/* Create edges */
VTR_ASSERT(rr_graph_view.valid_node(des_node));
rr_graph_builder.create_edge(src_node, des_node,
@ -470,7 +471,8 @@ static void add_rr_graph_block_clock_edges(RRGraphBuilder& rr_graph_builder,
* should drive some grid IPINs which are clocks */
if (clk_ntwk.is_last_level(itree, ilvl)) {
for (RRNodeId des_node : find_clock_track2ipin_node(
grids, rr_graph_view, chan_type, chan_coord, clk_ntwk, itree, ipin)) {
grids, rr_graph_view, chan_type, chan_coord, clk_ntwk, itree,
ipin)) {
/* Create edges */
VTR_ASSERT(rr_graph_view.valid_node(des_node));
rr_graph_builder.create_edge(src_node, des_node,
@ -526,8 +528,8 @@ static void add_rr_graph_clock_edges(RRGraphBuilder& rr_graph_builder,
continue;
}
add_rr_graph_block_clock_edges(rr_graph_builder, num_edges_to_create,
clk_rr_lookup, rr_graph_view, grids, clk_ntwk,
chanx_coord, CHANX);
clk_rr_lookup, rr_graph_view, grids,
clk_ntwk, chanx_coord, CHANX);
}
}
@ -542,8 +544,8 @@ static void add_rr_graph_clock_edges(RRGraphBuilder& rr_graph_builder,
continue;
}
add_rr_graph_block_clock_edges(rr_graph_builder, num_edges_to_create,
clk_rr_lookup, rr_graph_view, grids, clk_ntwk,
chany_coord, CHANY);
clk_rr_lookup, rr_graph_view, grids,
clk_ntwk, chany_coord, CHANY);
}
}
}

53
openfpga/src/utils/openfpga_physical_tile_utils.cpp
View File

@ -11,9 +11,9 @@
/* Headers from openfpgautil library */
#include "openfpga_device_grid_utils.h"
#include "openfpga_physical_tile_utils.h"
#include "openfpga_port_parser.h"
#include "openfpga_side_manager.h"
#include "openfpga_tokenizer.h"
#include "openfpga_port_parser.h"
/* begin namespace openfpga */
namespace openfpga {
@ -122,16 +122,19 @@ std::set<e_side> find_physical_io_tile_located_sides(
* Find the pin index of a physical tile which matches the given name.
* For example,
* io[5:5].a2f[1]
* which corresponds to the pin 'a2f[1]' of the 5th subtile 'io' in the physical tile
* which corresponds to the pin 'a2f[1]' of the 5th subtile 'io' in the physical
*tile
*******************************************************************/
int find_physical_tile_pin_index(t_physical_tile_type_ptr physical_tile, std::string pin_name) {
int find_physical_tile_pin_index(t_physical_tile_type_ptr physical_tile,
std::string pin_name) {
/* Deposit an invalid value */
int pin_idx = physical_tile->num_pins;
/* precheck: return unfound pin if the tile name does not match */
StringToken tokenizer(pin_name);
std::vector<std::string> pin_tokens = tokenizer.split(".");
if (pin_tokens.size() != 2) {
VTR_LOG_ERROR("Invalid pin name '%s'. Expect <tile>.<port>\n", pin_name.c_str());
VTR_LOG_ERROR("Invalid pin name '%s'. Expect <tile>.<port>\n",
pin_name.c_str());
exit(1);
}
PortParser tile_parser(pin_tokens[0]);
@ -140,16 +143,26 @@ int find_physical_tile_pin_index(t_physical_tile_type_ptr physical_tile, std::st
return pin_idx;
}
if (!tile_info.is_valid()) {
VTR_LOG_ERROR("Invalid pin name '%s' whose subtile index is not valid, expect [0, %lu]\n", pin_name.c_str(), physical_tile->capacity - 1);
VTR_LOG_ERROR(
"Invalid pin name '%s' whose subtile index is not valid, expect [0, "
"%lu]\n",
pin_name.c_str(), physical_tile->capacity - 1);
exit(1);
}
/* precheck: return unfound pin if the subtile index does not match */
if (tile_info.get_width() != 1) {
VTR_LOG_ERROR("Invalid pin name '%s' whose subtile index range should be 1. For example, clb[1:1]\n", pin_name.c_str());
VTR_LOG_ERROR(
"Invalid pin name '%s' whose subtile index range should be 1. For "
"example, clb[1:1]\n",
pin_name.c_str());
exit(1);
}
if (tile_info.get_lsb() < 0 || tile_info.get_msb() > physical_tile->capacity - 1) {
VTR_LOG_ERROR("Invalid pin name '%s' whose subtile index is out of range, expect [0, %lu]\n", pin_name.c_str(), physical_tile->capacity - 1);
if (tile_info.get_lsb() < 0 ||
tile_info.get_msb() > physical_tile->capacity - 1) {
VTR_LOG_ERROR(
"Invalid pin name '%s' whose subtile index is out of range, expect [0, "
"%lu]\n",
pin_name.c_str(), physical_tile->capacity - 1);
exit(1);
}
/* precheck: return unfound pin if the pin index does not match */
@ -157,7 +170,10 @@ int find_physical_tile_pin_index(t_physical_tile_type_ptr physical_tile, std::st
BasicPort pin_info = pin_parser.port();
/* precheck: return unfound pin if the subtile index does not match */
if (pin_info.get_width() != 1) {
VTR_LOG_ERROR("Invalid pin name '%s' whose pin index range should be 1. For example, clb[1:1].I[2:2]\n", pin_name.c_str());
VTR_LOG_ERROR(
"Invalid pin name '%s' whose pin index range should be 1. For example, "
"clb[1:1].I[2:2]\n",
pin_name.c_str());
exit(1);
}
@ -171,15 +187,25 @@ int find_physical_tile_pin_index(t_physical_tile_type_ptr physical_tile, std::st
continue;
}
if (!pin_info.is_valid()) {
VTR_LOG_ERROR("Invalid pin name '%s' whose pin index is not valid, expect [0, %lu]\n", pin_name.c_str(), sub_tile_port.num_pins - 1);
VTR_LOG_ERROR(
"Invalid pin name '%s' whose pin index is not valid, expect [0, "
"%lu]\n",
pin_name.c_str(), sub_tile_port.num_pins - 1);
exit(1);
}
if (pin_info.get_lsb() < 0 || pin_info.get_msb() > sub_tile_port.num_pins - 1) {
VTR_LOG_ERROR("Invalid pin name '%s' whose pin index is out of range, expect [0, %lu]\n", pin_name.c_str(), sub_tile_port.num_pins - 1);
if (pin_info.get_lsb() < 0 ||
pin_info.get_msb() > sub_tile_port.num_pins - 1) {
VTR_LOG_ERROR(
"Invalid pin name '%s' whose pin index is out of range, expect [0, "
"%lu]\n",
pin_name.c_str(), sub_tile_port.num_pins - 1);
exit(1);
}
/* Reach here, we get the port we want, return the accumulated index */
size_t accumulated_pin_idx = sub_tile_port.absolute_first_pin_index + sub_tile.num_phy_pins * (tile_info.get_lsb() - sub_tile.capacity.low) + pin_info.get_lsb();
size_t accumulated_pin_idx =
sub_tile_port.absolute_first_pin_index +
sub_tile.num_phy_pins * (tile_info.get_lsb() - sub_tile.capacity.low) +
pin_info.get_lsb();
return accumulated_pin_idx;
}
}
@ -187,5 +213,4 @@ int find_physical_tile_pin_index(t_physical_tile_type_ptr physical_tile, std::st
return pin_idx;
}
} /* end namespace openfpga */

3
openfpga/src/utils/openfpga_physical_tile_utils.h
View File

@ -27,7 +27,8 @@ float find_physical_tile_pin_Fc(t_physical_tile_type_ptr type, const int& pin);
std::set<e_side> find_physical_io_tile_located_sides(
const DeviceGrid& grids, t_physical_tile_type_ptr physical_tile);
int find_physical_tile_pin_index(t_physical_tile_type_ptr physical_tile, std::string pin_name);
int find_physical_tile_pin_index(t_physical_tile_type_ptr physical_tile,
std::string pin_name);
} /* end namespace openfpga */