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[core] code format

This commit is contained in:
tangxifan 2023-02-27 15:12:59 -08:00
parent 9ec4d690db
commit b3dec93eb9
5 changed files with 69 additions and 67 deletions
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12
libs/libclkarchopenfpga/src/base/clock_network.cpp
View File

@ -155,9 +155,7 @@ std::string ClockNetwork::default_switch_name() const {
return default_switch_name_;
}
RRSwitchId ClockNetwork::default_switch() const {
return default_switch_id_;
}
RRSwitchId ClockNetwork::default_switch() const { return default_switch_id_; }
std::string ClockNetwork::tree_name(const ClockTreeId& tree_id) const {
VTR_ASSERT(valid_tree_id(tree_id));
@ -279,7 +277,6 @@ void ClockNetwork::set_default_switch(const RRSwitchId& switch_id) {
default_switch_id_ = switch_id;
}
void ClockNetwork::set_default_segment_name(const std::string& name) {
default_segment_name_ = name;
}
@ -506,12 +503,11 @@ bool ClockNetwork::valid_tree_id(const ClockTreeId& tree_id) const {
(tree_id == tree_ids_[tree_id]);
}
bool ClockNetwork::valid_level_id(const ClockTreeId& tree_id, const ClockLevelId& lvl_id) const {
return valid_tree_id(tree_id) &&
(size_t(lvl_id) < tree_depth(tree_id));
bool ClockNetwork::valid_level_id(const ClockTreeId& tree_id,
const ClockLevelId& lvl_id) const {
return valid_tree_id(tree_id) && (size_t(lvl_id) < tree_depth(tree_id));
}
bool ClockNetwork::valid_spine_id(const ClockSpineId& spine_id) const {
return (size_t(spine_id) < spine_ids_.size()) &&
(spine_id == spine_ids_[spine_id]);

10
libs/libclkarchopenfpga/src/base/clock_network.h
View File

@ -110,9 +110,10 @@ class ClockNetwork {
/* Check if there are clock tree */
bool empty() const;
bool is_valid() const;
/* Get the level id which is next to the current level
* Note that this follows the same rule in computing levels in update_tree_depth()
* If the rule has been changed, this API should be changed as well
/* Get the level id which is next to the current level
* Note that this follows the same rule in computing levels in
* update_tree_depth() If the rule has been changed, this API should be
* changed as well
*/
ClockLevelId next_level(const ClockLevelId& lvl) const;
@ -154,7 +155,8 @@ class ClockNetwork {
/* Show if the tree id is a valid for data queries */
bool valid_tree_id(const ClockTreeId& tree_id) const;
/* Show if the level id is a valid for a given tree */
bool valid_level_id(const ClockTreeId& tree_id, const ClockLevelId& lvl_id) const;
bool valid_level_id(const ClockTreeId& tree_id,
const ClockLevelId& lvl_id) const;
/* Show if the tree id is a valid for data queries */
bool valid_spine_id(const ClockSpineId& spine_id) const;
bool valid_spine_switch_point_id(

13
libs/libclkarchopenfpga/src/utils/clock_network_utils.cpp
View File

@ -10,9 +10,8 @@ namespace openfpga { // Begin namespace openfpga
* Link all the segments that are defined in a routing resource graph to a given
*clock network
*******************************************************************/
static
int link_clock_network_rr_segments(ClockNetwork& clk_ntwk,
const RRGraphView& rr_graph) {
static int link_clock_network_rr_segments(ClockNetwork& clk_ntwk,
const RRGraphView& rr_graph) {
/* default segment id */
std::string default_segment_name = clk_ntwk.default_segment_name();
for (size_t rr_seg_id = 0; rr_seg_id < rr_graph.num_rr_segments();
@ -31,9 +30,8 @@ int link_clock_network_rr_segments(ClockNetwork& clk_ntwk,
* Link all the switches that are defined in a routing resource graph to a given
*clock network
*******************************************************************/
static
int link_clock_network_rr_switches(ClockNetwork& clk_ntwk,
const RRGraphView& rr_graph) {
static int link_clock_network_rr_switches(ClockNetwork& clk_ntwk,
const RRGraphView& rr_graph) {
/* default switch id */
std::string default_switch_name = clk_ntwk.default_switch_name();
for (size_t rr_switch_id = 0; rr_switch_id < rr_graph.num_rr_switches();
@ -61,8 +59,7 @@ int link_clock_network_rr_graph(ClockNetwork& clk_ntwk,
return status;
}
return status;
return status;
}
} // End of namespace openfpga

99
openfpga/src/annotation/append_clock_rr_graph.cpp
View File

@ -165,16 +165,16 @@ static void add_rr_graph_clock_nodes(RRGraphBuilder& rr_graph_builder,
}
/********************************************************************
* Find the destination nodes for a driver clock node in a given connection block
* There are two types of destination nodes:
* - Straight connection where the driver clock node connects to another clock node
* in the same direction and at the same level as well as clock index
* For example
* Find the destination nodes for a driver clock node in a given connection
*block There are two types of destination nodes:
* - Straight connection where the driver clock node connects to another clock
*node in the same direction and at the same level as well as clock index For
*example
*
* clk0_lvl0_chanx[1][1] -->------------->---> clk0_lvl0_chanx[2][1]
*
* - Turning connections where the driver clock node makes turns to connect other clock nodes
* at 1-level up and in the same clock index
* - Turning connections where the driver clock node makes turns to connect
*other clock nodes at 1-level up and in the same clock index
*
*
* clk0_lvl1_chany[1][2]
@ -186,7 +186,7 @@ static void add_rr_graph_clock_nodes(RRGraphBuilder& rr_graph_builder,
* clk0_lvl1_chany[1][1]
*
* Coordindate system:
*
*
* +----------+----------+------------+
* | Grid | CBy | Grid |
* | [x][y+1] | [x][y+1] | [x+1][y+1] |
@ -197,29 +197,25 @@ static void add_rr_graph_clock_nodes(RRGraphBuilder& rr_graph_builder,
* | Grid | CBy | Grid |
* | [x][y] | [x][y] | [x+1][y] |
* +----------+----------+------------+
*
*
*******************************************************************/
static
std::vector<RRNodeId> find_clock_track2track_node(const RRGraphView& rr_graph_view,
const ClockNetwork& clk_ntwk,
const RRClockSpatialLookup& clk_rr_lookup,
const t_rr_type& chan_type,
const vtr::Point<size_t>& chan_coord,
const ClockTreeId& clk_tree,
const ClockLevelId& clk_lvl,
const ClockTreePinId& clk_pin,
const Direction& direction) {
static std::vector<RRNodeId> find_clock_track2track_node(
const RRGraphView& rr_graph_view, const ClockNetwork& clk_ntwk,
const RRClockSpatialLookup& clk_rr_lookup, const t_rr_type& chan_type,
const vtr::Point<size_t>& chan_coord, const ClockTreeId& clk_tree,
const ClockLevelId& clk_lvl, const ClockTreePinId& clk_pin,
const Direction& direction) {
std::vector<RRNodeId> des_nodes;
/* Straight connection */
vtr::Point<size_t> straight_des_coord = chan_coord;
vtr::Point<size_t> straight_des_coord = chan_coord;
if (chan_type == CHANX) {
if (direction == Direction::INC) {
straight_des_coord.set_x(straight_des_coord.x() + 1);
} else {
VTR_ASSERT(direction == Direction::DEC);
straight_des_coord.set_x(straight_des_coord.x() - 1);
}
}
} else {
VTR_ASSERT(chan_type == CHANY);
if (direction == Direction::INC) {
@ -227,22 +223,25 @@ std::vector<RRNodeId> find_clock_track2track_node(const RRGraphView& rr_graph_vi
} else {
VTR_ASSERT(direction == Direction::DEC);
straight_des_coord.set_y(straight_des_coord.y() - 1);
}
}
}
RRNodeId straight_des_node = clk_rr_lookup.find_node(straight_des_coord.x(), straight_des_coord.y(), clk_tree, clk_lvl, clk_pin, direction);
RRNodeId straight_des_node =
clk_rr_lookup.find_node(straight_des_coord.x(), straight_des_coord.y(),
clk_tree, clk_lvl, clk_pin, direction);
if (rr_graph_view.valid_node(straight_des_node)) {
VTR_ASSERT(chan_type == rr_graph_view.node_type(straight_des_node));
des_nodes.push_back(straight_des_node);
}
/* Check the next level if this is the last level, there are no turns available */
/* Check the next level if this is the last level, there are no turns
* available */
ClockLevelId next_clk_lvl = clk_ntwk.next_level(clk_lvl);
if (!clk_ntwk.valid_level_id(clk_tree, next_clk_lvl)) {
return des_nodes;
}
/* left turn connection */
vtr::Point<size_t> left_des_coord = chan_coord;
vtr::Point<size_t> left_des_coord = chan_coord;
Direction left_direction = direction;
t_rr_type left_des_chan_type = chan_type;
if (chan_type == CHANX) {
@ -262,7 +261,7 @@ std::vector<RRNodeId> find_clock_track2track_node(const RRGraphView& rr_graph_vi
*/
VTR_ASSERT(direction == Direction::DEC);
left_des_coord.set_x(left_des_coord.x() - 1);
}
}
} else {
VTR_ASSERT(chan_type == CHANY);
left_des_chan_type = CHANX;
@ -283,16 +282,18 @@ std::vector<RRNodeId> find_clock_track2track_node(const RRGraphView& rr_graph_vi
left_direction = Direction::INC;
left_des_coord.set_x(left_des_coord.x() + 1);
left_des_coord.set_y(left_des_coord.y() - 1);
}
}
}
RRNodeId left_des_node = clk_rr_lookup.find_node(left_des_coord.x(), left_des_coord.y(), clk_tree, next_clk_lvl, clk_pin, left_direction);
RRNodeId left_des_node =
clk_rr_lookup.find_node(left_des_coord.x(), left_des_coord.y(), clk_tree,
next_clk_lvl, clk_pin, left_direction);
if (rr_graph_view.valid_node(left_des_node)) {
VTR_ASSERT(left_des_chan_type == rr_graph_view.node_type(left_des_node));
des_nodes.push_back(left_des_node);
}
/* right turn connection */
vtr::Point<size_t> right_des_coord = chan_coord;
vtr::Point<size_t> right_des_coord = chan_coord;
Direction right_direction = direction;
t_rr_type right_des_chan_type = chan_type;
if (chan_type == CHANX) {
@ -314,7 +315,7 @@ std::vector<RRNodeId> find_clock_track2track_node(const RRGraphView& rr_graph_vi
right_direction = Direction::INC;
right_des_coord.set_x(right_des_coord.x() - 1);
right_des_coord.set_y(right_des_coord.y() + 1);
}
}
} else {
VTR_ASSERT(chan_type == CHANY);
right_des_chan_type = CHANX;
@ -333,9 +334,11 @@ std::vector<RRNodeId> find_clock_track2track_node(const RRGraphView& rr_graph_vi
* <--+
*/
right_des_coord.set_y(right_des_coord.y() - 1);
}
}
}
RRNodeId right_des_node = clk_rr_lookup.find_node(right_des_coord.x(), right_des_coord.y(), clk_tree, next_clk_lvl, clk_pin, right_direction);
RRNodeId right_des_node =
clk_rr_lookup.find_node(right_des_coord.x(), right_des_coord.y(), clk_tree,
next_clk_lvl, clk_pin, right_direction);
if (rr_graph_view.valid_node(right_des_node)) {
VTR_ASSERT(right_des_chan_type == rr_graph_view.node_type(right_des_node));
des_nodes.push_back(right_des_node);
@ -348,9 +351,10 @@ std::vector<RRNodeId> find_clock_track2track_node(const RRGraphView& rr_graph_vi
* Add edges for the clock nodes in a given connection block
*******************************************************************/
static void add_rr_graph_block_clock_edges(
RRGraphBuilder& rr_graph_builder, size_t& num_edges_to_create, const RRClockSpatialLookup& clk_rr_lookup,
const RRGraphView& rr_graph_view, const ClockNetwork& clk_ntwk,
const vtr::Point<size_t> chan_coord, const t_rr_type& chan_type) {
RRGraphBuilder& rr_graph_builder, size_t& num_edges_to_create,
const RRClockSpatialLookup& clk_rr_lookup, const RRGraphView& rr_graph_view,
const ClockNetwork& clk_ntwk, const vtr::Point<size_t> chan_coord,
const t_rr_type& chan_type) {
size_t edge_count = 0;
for (auto itree : clk_ntwk.trees()) {
for (auto ilvl : clk_ntwk.levels(itree)) {
@ -361,13 +365,17 @@ static void add_rr_graph_block_clock_edges(
chan_coord.x(), chan_coord.y(), itree, ilvl, ipin, node_dir);
VTR_ASSERT(rr_graph_view.valid_node(src_node));
/* find the fan-out clock node through lookup */
for (RRNodeId des_node : find_clock_track2track_node(rr_graph_view, clk_ntwk, clk_rr_lookup, chan_type, chan_coord, itree, ilvl, ipin, node_dir)) {
for (RRNodeId des_node : find_clock_track2track_node(
rr_graph_view, clk_ntwk, clk_rr_lookup, chan_type, chan_coord,
itree, ilvl, ipin, node_dir)) {
/* Create edges */
VTR_ASSERT(rr_graph_view.valid_node(des_node));
rr_graph_builder.create_edge(src_node, des_node, clk_ntwk.default_switch());
rr_graph_builder.create_edge(src_node, des_node,
clk_ntwk.default_switch());
edge_count++;
}
/* TODO: If this is the clock node at the last level of the tree, should drive some grid IPINs which are clocks */
/* TODO: If this is the clock node at the last level of the tree,
* should drive some grid IPINs which are clocks */
}
}
}
@ -415,9 +423,9 @@ static void add_rr_graph_clock_edges(RRGraphBuilder& rr_graph_builder,
(false == is_chanx_exist(grids, chanx_coord))) {
continue;
}
add_rr_graph_block_clock_edges(rr_graph_builder, num_edges_to_create, clk_rr_lookup,
rr_graph_view, clk_ntwk, chanx_coord,
CHANX);
add_rr_graph_block_clock_edges(rr_graph_builder, num_edges_to_create,
clk_rr_lookup, rr_graph_view, clk_ntwk,
chanx_coord, CHANX);
}
}
@ -431,9 +439,9 @@ static void add_rr_graph_clock_edges(RRGraphBuilder& rr_graph_builder,
(false == is_chany_exist(grids, chany_coord))) {
continue;
}
add_rr_graph_block_clock_edges(rr_graph_builder, num_edges_to_create, clk_rr_lookup,
rr_graph_view, clk_ntwk, chany_coord,
CHANY);
add_rr_graph_block_clock_edges(rr_graph_builder, num_edges_to_create,
clk_rr_lookup, rr_graph_view, clk_ntwk,
chany_coord, CHANY);
}
}
}
@ -485,8 +493,7 @@ int append_clock_rr_graph(DeviceContext& vpr_device_ctx,
/* TODO: Add edges between clock nodes*/
size_t num_clock_edges = 0;
add_rr_graph_clock_edges(
vpr_device_ctx.rr_graph_builder,
num_clock_edges,
vpr_device_ctx.rr_graph_builder, num_clock_edges,
static_cast<const RRClockSpatialLookup&>(clk_rr_lookup),
vpr_device_ctx.rr_graph, vpr_device_ctx.grid,
vpr_device_ctx.arch->through_channel, clk_ntwk);

2
openfpga/src/base/openfpga_read_arch_template.h
View File

@ -238,7 +238,7 @@ int read_openfpga_clock_arch_template(T& openfpga_context, const Command& cmd,
/* Build internal links */
openfpga_context.mutable_clock_arch().link();
link_clock_network_rr_graph(openfpga_context.mutable_clock_arch(),
g_vpr_ctx.device().rr_graph);
g_vpr_ctx.device().rr_graph);
/* Ensure clean data */
openfpga_context.clock_arch().validate();
if (!openfpga_context.clock_arch().is_valid()) {