58708ff727
[core] syntax
2024-04-10 20:08:02 -07:00
435e83c530
[core] add port side to tile ports
2024-04-10 17:38:02 -07:00
f9f7d42d93
[core] add port side attribute and set them when buidling grid/cb/sb modules
2024-04-10 17:10:06 -07:00
d156de060e
[core] adding pin side attribute to module manager
2024-04-10 16:19:28 -07:00
b0be9fe75d
[core] developing xml writer for fabric pin phy loc
2024-04-10 15:51:26 -07:00
47baaff94c
[core] rename command name to 'write_fabric_pin_physical_location`` and start developing exec func
2024-04-10 13:30:02 -07:00
f1334645db
[core] added a new command write_pin_physical_location
2024-04-10 13:07:49 -07:00
0a7915aa77
[core] typo
2024-03-29 12:03:23 -07:00
6a5d3c7cdc
[code] syntax
2024-03-29 11:03:48 -07:00
00de794967
[core] code format
2024-03-29 10:58:48 -07:00
981828c39c
[core] add a new opton ``--dump_waveform`` to command ``write_preconfigured_fabric_wrapper``
2024-03-29 10:57:45 -07:00
4365d160ff
Support extracting data that is not affecting fabric bitstream ( #1566 )
...
* BRAM preload data - generic way to extract data from design
* Add docs and support special __layout__ case
* Add test
* Fix warning
* Change none-fabric to non-fabric
2024-03-09 17:38:31 -08:00
59deb97d5d
[core] code format
2024-01-12 14:17:10 -08:00
f1e3d53da6
[core] fixed a bug where pb pin fixup may fail when subtile capacities are not same
2024-01-12 14:16:07 -08:00
bacd845139
[core] code format
2023-12-08 13:41:41 -08:00
5e181cbe72
[core] add a new option for simulator type to verilog full testbench generator
2023-12-08 13:07:25 -08:00
0e945d6e71
[core] fix a bug in ql memory bank tb where VCS failed
2023-12-08 11:36:54 -08:00
8a24b1ba8c
Update repack_option.h
...
code clean up
2023-12-05 10:17:52 -08:00
94f7b2f4e2
Update repack.cpp
...
code clean up
2023-12-05 10:16:10 -08:00
d2379cfff6
Update repack_option.h
2023-12-05 09:34:34 -08:00
231cb0f89b
Update repack_option.cpp
2023-12-05 09:30:32 -08:00
83fdaea13d
Update repack.cpp
2023-12-05 09:28:27 -08:00
5ca928efda
Merge branch 'master' into repack_debug
2023-12-04 13:21:10 -08:00
c18f4d7f44
Issue:1466 - Fix WL ordering in bitstream generation
2023-11-29 21:55:53 -08:00
d28f024b61
minor change
2023-11-29 01:53:18 -08:00
1aac6681bc
Merge branch 'master' into repack_debug
2023-11-22 10:48:59 -08:00
e3682ac955
reformate the code
2023-11-22 01:15:55 -08:00
93d5b850f0
reset the error flag in each parsing iteration
2023-11-22 00:04:51 -08:00
8f9161b438
format the code
2023-11-21 22:28:37 -08:00
ee392f1b46
add ignore_net to repackdesign constraint
2023-11-21 21:47:03 -08:00
b780f0a552
[core] code format
2023-11-03 14:39:49 -07:00
e48de682ed
[core] fixed som ebugs
2023-11-03 14:39:28 -07:00
b2e1eb30c7
[core] code format
2023-11-03 13:50:04 -07:00
21813eb59f
[core] now full testbench uses bitstream in different sizes
2023-11-03 13:48:21 -07:00
2cd3453629
[core] fixed the bug in ccff v2 on config enable signal drivers
2023-11-03 10:25:12 -07:00
8bee65853c
[core] add missing files
2023-11-02 19:01:25 -07:00
649d44b2d8
[core] code format
2023-11-02 16:33:55 -07:00
36fa020c15
[core] syntax
2023-11-02 16:33:19 -07:00
75e9e98e5d
[core] add two new commands to output testbench parts
2023-11-02 16:06:48 -07:00
3d4f1505b6
[core] code format
2023-10-20 22:02:56 -07:00
66c3226fad
[core] now follow module unique index when naming grouped configuration memories
2023-10-20 22:01:19 -07:00
e4b204f2e4
[core] code format
2023-10-20 21:14:07 -07:00
76a4b8a82b
[core] remove the prefix of grouped memory blocks
2023-10-20 21:13:37 -07:00
5bae2bf54d
[core] code format
2023-10-19 23:05:49 -07:00
4b00651a46
[core] now name indexing is applied to netlist names
2023-10-19 23:03:48 -07:00
7ba6795fe2
[core] fixed a bug
2023-10-06 18:50:26 -07:00
83ef35b2da
[core] fixed a bug
2023-10-06 18:47:20 -07:00
3440768840
[core] code format
2023-10-06 18:37:54 -07:00
e102c9bddc
[core] fixed a bug
2023-10-06 18:37:28 -07:00
93cbbf2045
[core] code format
2023-10-06 18:20:55 -07:00
b07111497c
[core] enable options in xml writers
2023-10-06 18:20:17 -07:00
ae63c9d441
[core] code format
2023-10-06 17:28:25 -07:00
1e8bf1cece
[core] deploy options
2023-10-06 17:28:02 -07:00
f30663f708
[core] code format
2023-10-06 14:08:09 -07:00
108bbad8d4
[core] syntax
2023-10-06 14:07:44 -07:00
80856f1b70
[core] adding new options and rewrite options for bitfile writer
2023-10-06 13:54:29 -07:00
a15db83267
[core] code format
2023-09-26 11:41:11 -07:00
ea91182216
[core] check option conflicts
2023-09-26 11:40:42 -07:00
c4bce834e4
[core] code format
2023-09-25 22:34:39 -07:00
5aa206e616
[core] fixed some bugs
2023-09-25 22:27:24 -07:00
1624dc9764
[core] code format
2023-09-25 21:13:50 -07:00
76f446caec
[core] fixed a bug
2023-09-25 21:13:11 -07:00
dbd466cdec
[core] now support tile port merge
2023-09-25 18:16:24 -07:00
3adf81046a
[core] code format
2023-09-25 17:22:26 -07:00
5e269e8bc4
[core] support port merging at grid modules
2023-09-25 17:21:58 -07:00
edb0e687f1
[core] code format
2023-09-23 12:15:53 -07:00
11de8965a8
[core] fixed some bugs
2023-09-23 12:15:31 -07:00
860cfd53c6
[core] fixed critical bugs in renaming modules
2023-09-23 11:51:31 -07:00
ca3617a029
[core] code format
2023-09-20 20:37:27 -07:00
1ef38b6a64
[core] now name the port of tiles using the relative index of the subblocks in each tile, rather than the unique index of subblocks across a complete fabric. This avoids all the conflicts in naming
2023-09-20 20:34:21 -07:00
c105b56bf0
[core] code format
2023-09-18 23:31:27 -07:00
43fd08a3fe
[core] fixed a bug
2023-09-18 23:31:09 -07:00
4d11f73471
[core] fixed a bug
2023-09-18 20:43:15 -07:00
a1e609c901
[core] fixed some bugs
2023-09-18 16:39:07 -07:00
1daabb990e
[core] code format
2023-09-18 15:35:13 -07:00
110301a2e4
[core] now tile port naming can follow index
2023-09-18 15:34:40 -07:00
e46e58527a
[core] code format
2023-09-17 23:16:38 -07:00
eeb1bd6662
[core] fixed some bugs
2023-09-17 23:16:15 -07:00
c6175aa514
[core] code format
2023-09-17 22:37:48 -07:00
ef97127c63
[core] fixed some bugs in testbenches when renaming top modules
2023-09-17 22:34:00 -07:00
c14277a674
[core] fixing bugs
2023-09-17 17:57:57 -07:00
d5152dc16d
[core] fixed a bug on the hierarchy writer
2023-09-17 17:42:25 -07:00
4ccb4737be
[core] code format
2023-09-17 17:33:10 -07:00
f79da76656
[core] supporting renaming on all the verilog modules
2023-09-17 17:29:11 -07:00
72a3c05747
[core] code format
2023-09-17 13:29:30 -07:00
ccd4c1861b
[core] developing new command to write module naming rules
2023-09-16 19:37:06 -07:00
32df673d72
[core] code format
2023-09-16 18:35:33 -07:00
200ecad74a
[core] fixed bugs in bitgen
2023-09-16 18:34:55 -07:00
058bb1ef51
[core] code format
2023-09-16 18:24:38 -07:00
6fc2924438
[core] syntax
2023-09-16 18:16:30 -07:00
d61d88f12e
[core] fixed some bugs in verilog writer due to renaming
2023-09-16 18:13:22 -07:00
37573abc22
[core] code format
2023-09-15 23:32:40 -07:00
c85c64eb5a
[core] syntax
2023-09-15 23:30:34 -07:00
bc407e5d69
[core] code complete for rename modules
2023-09-15 23:22:31 -07:00
2a45b49890
[core] developing renaming commands. options and functions
2023-09-15 19:15:18 -07:00
af67b02cca
[lib] rename lib to namemanager as a unified library to provide naming support on FPGA modules
2023-09-15 13:51:14 -07:00
eaadff3448
[core] fixed some bugs
2023-09-06 22:49:56 -07:00
bcb82d43af
[core] code format
2023-09-06 22:40:59 -07:00
2fee56548b
[core] fixed some bugs
2023-09-06 22:39:59 -07:00
f544953085
[core] code format
2023-09-06 22:29:30 -07:00
tangxifan
chungshien
Yitian4Debug
chungshien
ubuntu