riscv
/
OpenFPGA
mirror of https://github.com/lnis-uofu/OpenFPGA.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

[core] fixed a bug

This commit is contained in:
tangxifan 2023-10-06 18:47:20 -07:00
parent c6f33bcd7f
commit 83ef35b2da
2 changed files with 4 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
openfpga/src/fpga_bitstream/bitstream_writer_options.cpp
View File

@ -141,11 +141,11 @@ bool BitstreamWriterOption::validate(bool show_err_msg) const {
"specified, please define one of them\n");
return false;
}
if (!filter_value_.empty() && (filter_value_ != std::to_string(0) ||
if (!filter_value_.empty() && (filter_value_ != std::to_string(0) &&
filter_value_ != std::to_string(1))) {
VTR_LOGV_ERROR(show_err_msg,
"Invalid value '%s' for filter values. Expect [0|1]!\n",
filter_value_);
filter_value_.c_str());
return false;
}
}

4
openfpga/src/fpga_bitstream/write_xml_fabric_bitstream.cpp
View File

@ -118,9 +118,9 @@ static int write_fabric_config_bit_to_xml_file(
hie_path += std::to_string(bit_idx_in_parent_block);
hie_path += std::string("]");
fp << " path=\"" << hie_path;
fp << " path=\"" << hie_path << "\"";
}
fp << "\">\n";
fp << ">\n";
switch (config_type) {
case CONFIG_MEM_STANDALONE: