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[core] code format

This commit is contained in:
tangxifan 2024-03-29 10:58:48 -07:00
parent 981828c39c
commit 00de794967
5 changed files with 14 additions and 14 deletions
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3
openfpga/src/base/openfpga_verilog_template.h
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@ -185,8 +185,7 @@ int write_preconfigured_fabric_wrapper_template(
options.set_verbose_output(cmd_context.option_enable(cmd, opt_verbose));
options.set_include_signal_init(
cmd_context.option_enable(cmd, opt_include_signal_init));
options.set_dump_waveform(
cmd_context.option_enable(cmd, opt_dump_waveform));
options.set_dump_waveform(cmd_context.option_enable(cmd, opt_dump_waveform));
options.set_print_formal_verification_top_netlist(true);
if (true == cmd_context.option_enable(cmd, opt_dut_module)) {

3
openfpga/src/fpga_verilog/verilog_preconfig_top_module.cpp
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@ -492,7 +492,8 @@ int print_verilog_preconfig_top_module(
/* Add waveform output command, support both fsdb and vcd */
if (true == options.dump_waveform()) {
print_verilog_testbench_dump_waveform(fp, circuit_name, std::string(FORMAL_VERIFICATION_TOP_MODULE_UUT_NAME));
print_verilog_testbench_dump_waveform(
fp, circuit_name, std::string(FORMAL_VERIFICATION_TOP_MODULE_UUT_NAME));
}
/* Testbench ends*/

4
openfpga/src/fpga_verilog/verilog_testbench_options.cpp
View File

@ -88,9 +88,7 @@ bool VerilogTestbenchOption::include_signal_init() const {
return include_signal_init_;
}
bool VerilogTestbenchOption::dump_waveform() const {
return dump_waveform_;
}
bool VerilogTestbenchOption::dump_waveform() const { return dump_waveform_; }
bool VerilogTestbenchOption::no_self_checking() const {
return reference_benchmark_file_path_.empty();

12
openfpga/src/fpga_verilog/verilog_testbench_utils.cpp
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@ -1347,14 +1347,15 @@ void print_verilog_testbench_signal_initialization(
/********************************************************************
* Print waveform output commands: support both VCD and FSDB
*******************************************************************/
void print_verilog_testbench_dump_waveform(
std::fstream& fp, const std::string& circuit_name,
const std::string& uut_name) {
void print_verilog_testbench_dump_waveform(std::fstream& fp,
const std::string& circuit_name,
const std::string& uut_name) {
/* Validate the file stream */
valid_file_stream(fp);
print_verilog_comment(
fp, std::string("------ Use " + std::string(VERILOG_FSDB_PREPROC_FLAG) + " to enable FSDB waveform output -----"));
fp, std::string("------ Use " + std::string(VERILOG_FSDB_PREPROC_FLAG) +
" to enable FSDB waveform output -----"));
print_verilog_preprocessing_flag(fp, std::string(VERILOG_FSDB_PREPROC_FLAG));
fp << "\tinital begin\n";
fp << "\t\t$fsdbDumpfile(\"" << circuit_name << ".fsdb\");\n";
@ -1363,7 +1364,8 @@ void print_verilog_testbench_dump_waveform(
print_verilog_endif(fp);
print_verilog_comment(
fp, std::string("------ Use " + std::string(VERILOG_VCD_PREPROC_FLAG) + " to enable VCD waveform output -----"));
fp, std::string("------ Use " + std::string(VERILOG_VCD_PREPROC_FLAG) +
" to enable VCD waveform output -----"));
print_verilog_preprocessing_flag(fp, std::string(VERILOG_VCD_PREPROC_FLAG));
fp << "\tinital begin\n";
fp << "\t\t$dumpfile(\"" << circuit_name << ".vcd\");\n";

6
openfpga/src/fpga_verilog/verilog_testbench_utils.h
View File

@ -135,9 +135,9 @@ void print_verilog_testbench_signal_initialization(
const CircuitLibrary& circuit_lib, const ModuleManager& module_manager,
const ModuleId& top_module, const bool& deposit_random_values);
void print_verilog_testbench_dump_waveform(
std::fstream& fp, const std::string& circuit_name,
const std::string& uut_name);
void print_verilog_testbench_dump_waveform(std::fstream& fp,
const std::string& circuit_name,
const std::string& uut_name);
} /* end namespace openfpga */