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[core] fix a bug in ql memory bank tb where VCS failed

This commit is contained in:
tangxifan 2023-12-08 11:36:54 -08:00
parent 8fe9811326
commit 0e945d6e71
1 changed files with 5 additions and 4 deletions
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9
openfpga/src/fpga_verilog/verilog_top_testbench_memory_bank.cpp
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@ -345,10 +345,11 @@ print_verilog_full_testbench_ql_memory_bank_shift_register_virtual_clock_generat
fp << "end";
fp << std::endl;
fp << "\t";
fp << generate_verilog_port_constant_values(
sr_clock_port, std::vector<size_t>(sr_clock_port.get_width(), 0), true);
fp << ";" << std::endl;
// The following code does not work when using Synopsys VCS. Comment them out. See if iverilog is fine or not
//fp << "\t";
//fp << generate_verilog_port_constant_values(
// sr_clock_port, std::vector<size_t>(sr_clock_port.get_width(), 0), true);
//fp << ";" << std::endl;
fp << "end";
fp << std::endl;