From 0e945d6e71e98be1fe9123f8c0b57f8292eeb5ed Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 8 Dec 2023 11:36:54 -0800 Subject: [PATCH] [core] fix a bug in ql memory bank tb where VCS failed --- .../fpga_verilog/verilog_top_testbench_memory_bank.cpp | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/openfpga/src/fpga_verilog/verilog_top_testbench_memory_bank.cpp b/openfpga/src/fpga_verilog/verilog_top_testbench_memory_bank.cpp index d4a211e89..64c22ca0b 100644 --- a/openfpga/src/fpga_verilog/verilog_top_testbench_memory_bank.cpp +++ b/openfpga/src/fpga_verilog/verilog_top_testbench_memory_bank.cpp @@ -345,10 +345,11 @@ print_verilog_full_testbench_ql_memory_bank_shift_register_virtual_clock_generat fp << "end"; fp << std::endl; - fp << "\t"; - fp << generate_verilog_port_constant_values( - sr_clock_port, std::vector(sr_clock_port.get_width(), 0), true); - fp << ";" << std::endl; + // The following code does not work when using Synopsys VCS. Comment them out. See if iverilog is fine or not + //fp << "\t"; + //fp << generate_verilog_port_constant_values( + // sr_clock_port, std::vector(sr_clock_port.get_width(), 0), true); + //fp << ";" << std::endl; fp << "end"; fp << std::endl;