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[core] syntax

This commit is contained in:
tangxifan 2023-11-02 16:33:19 -07:00
parent 75e9e98e5d
commit 36fa020c15
6 changed files with 71 additions and 51 deletions
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20
openfpga/src/base/openfpga_verilog_template.h
View File

@ -244,6 +244,11 @@ int write_testbench_template_template(
options.set_time_stamp(!cmd_context.option_enable(cmd, opt_no_time_stamp));
options.set_verbose_output(cmd_context.option_enable(cmd, opt_verbose));
if (true == cmd_context.option_enable(cmd, opt_default_net_type)) {
options.set_default_net_type(
cmd_context.option_value(cmd, opt_default_net_type));
}
if (true == cmd_context.option_enable(cmd, opt_dut_module)) {
options.set_dut_module(cmd_context.option_value(cmd, opt_dut_module));
}
@ -253,12 +258,8 @@ int write_testbench_template_template(
}
return fpga_verilog_template_testbench(
openfpga_ctx.module_graph(), openfpga_ctx.bitstream_manager(),
g_vpr_ctx.atom(), g_vpr_ctx.placement(), pin_constraints, bus_group,
openfpga_ctx.io_location_map(), openfpga_ctx.io_name_map(),
openfpga_ctx.module_name_map(), openfpga_ctx.fabric_global_port_info(),
openfpga_ctx.vpr_netlist_annotation(), openfpga_ctx.arch().circuit_lib,
openfpga_ctx.arch().config_protocol, options);
openfpga_ctx.module_graph(), openfpga_ctx.io_name_map(),
openfpga_ctx.module_name_map(), options);
}
/********************************************************************
@ -303,12 +304,11 @@ int write_testbench_io_connection_template(
}
return fpga_verilog_testbench_io_connection(
openfpga_ctx.module_graph(), openfpga_ctx.bitstream_manager(),
openfpga_ctx.module_graph(),
g_vpr_ctx.atom(), g_vpr_ctx.placement(), pin_constraints, bus_group,
openfpga_ctx.io_location_map(), openfpga_ctx.io_name_map(),
openfpga_ctx.io_location_map(),
openfpga_ctx.module_name_map(), openfpga_ctx.fabric_global_port_info(),
openfpga_ctx.vpr_netlist_annotation(), openfpga_ctx.arch().circuit_lib,
openfpga_ctx.arch().config_protocol, options);
openfpga_ctx.vpr_netlist_annotation(), options);
}
/********************************************************************

51
openfpga/src/fpga_verilog/verilog_api.cpp
View File

@ -21,6 +21,7 @@
#include "verilog_mock_fpga_wrapper.h"
#include "verilog_preconfig_top_module.h"
#include "verilog_template_testbench.h"
#include "verilog_testbench_io_connection.h"
#include "verilog_routing.h"
#include "verilog_simulation_info_writer.h"
#include "verilog_submodule.h"
@ -265,18 +266,45 @@ int fpga_verilog_preconfigured_fabric_wrapper(
********************************************************************/
int fpga_verilog_template_testbench(
const ModuleManager &module_manager,
const BitstreamManager &bitstream_manager, const AtomContext &atom_ctx,
const PlacementContext &place_ctx, const PinConstraints &pin_constraints,
const BusGroup &bus_group, const IoLocationMap &io_location_map,
const IoNameMap &io_name_map, const ModuleNameMap &module_name_map,
const FabricGlobalPortInfo &fabric_global_port_info,
const VprNetlistAnnotation &netlist_annotation,
const CircuitLibrary &circuit_lib, const ConfigProtocol &config_protocol,
const VerilogTestbenchOption &options) {
vtr::ScopedStartFinishTimer timer(
"Write a template testbench for a preconfigured FPGA fabric\n");
std::string src_dir_path = format_dir_path(options.output_directory());
std::string src_dir_path = format_dir_path(find_path_dir_name(options.output_directory()));
std::string testbench_file_path = options.output_directory();
int status = CMD_EXEC_SUCCESS;
/* Create directories */
create_directory(src_dir_path);
/* Generate wrapper module for FPGA fabric (mapped by the input benchmark and
* pre-configured testbench for verification */
status = print_verilog_template_testbench(
module_manager, io_name_map, module_name_map,
testbench_file_path, options);
return status;
}
/********************************************************************
* A top-level function of FPGA-Verilog which focuses on generating I/O connection part of testbenches
********************************************************************/
int fpga_verilog_testbench_io_connection(
const ModuleManager &module_manager,
const AtomContext &atom_ctx,
const PlacementContext &place_ctx, const PinConstraints &pin_constraints,
const BusGroup &bus_group, const IoLocationMap &io_location_map,
const ModuleNameMap &module_name_map,
const FabricGlobalPortInfo &fabric_global_port_info,
const VprNetlistAnnotation &netlist_annotation,
const VerilogTestbenchOption &options) {
vtr::ScopedStartFinishTimer timer(
"Write a template testbench for a preconfigured FPGA fabric\n");
std::string src_dir_path = format_dir_path(find_path_dir_name(options.output_directory()));
std::string testbench_file_path = options.output_directory();
std::string netlist_name = atom_ctx.nlist.netlist_name();
@ -287,13 +315,10 @@ int fpga_verilog_template_testbench(
/* Generate wrapper module for FPGA fabric (mapped by the input benchmark and
* pre-configured testbench for verification */
std::string testbench_file_path =
src_dir_path + options.top_module_name() +
std::string(VERILOG_NETLIST_FILE_POSTFIX);
status = print_verilog_template_testbench(
module_manager, bitstream_manager, config_protocol, circuit_lib,
status = print_verilog_testbench_io_connection(
module_manager,
fabric_global_port_info, atom_ctx, place_ctx, pin_constraints, bus_group,
io_location_map, io_name_map, module_name_map, netlist_annotation,
io_location_map, module_name_map, netlist_annotation,
netlist_name, testbench_file_path, options);
return status;

16
openfpga/src/fpga_verilog/verilog_api.h
View File

@ -74,6 +74,22 @@ int fpga_verilog_preconfigured_fabric_wrapper(
const CircuitLibrary& circuit_lib, const ConfigProtocol& config_protocol,
const VerilogTestbenchOption& options);
int fpga_verilog_template_testbench(
const ModuleManager &module_manager,
const IoNameMap &io_name_map, const ModuleNameMap &module_name_map,
const VerilogTestbenchOption &options);
int fpga_verilog_testbench_io_connection(
const ModuleManager &module_manager,
const AtomContext &atom_ctx,
const PlacementContext &place_ctx, const PinConstraints &pin_constraints,
const BusGroup &bus_group, const IoLocationMap &io_location_map,
const ModuleNameMap &module_name_map,
const FabricGlobalPortInfo &fabric_global_port_info,
const VprNetlistAnnotation &netlist_annotation,
const VerilogTestbenchOption &options);
int fpga_verilog_mock_fpga_wrapper(
const ModuleManager& module_manager, const AtomContext& atom_ctx,
const PlacementContext& place_ctx, const PinConstraints& pin_constraints,

2
openfpga/src/fpga_verilog/verilog_preconfig_top_module.h
View File

@ -29,7 +29,7 @@
namespace openfpga {
int print_verilog_testbench_io_connection(
int print_verilog_preconfig_top_module(
const ModuleManager& module_manager,
const BitstreamManager& bitstream_manager,
const ConfigProtocol& config_protocol, const CircuitLibrary& circuit_lib,

10
openfpga/src/fpga_verilog/verilog_template_testbench.cpp
View File

@ -52,14 +52,8 @@ namespace openfpga {
*******************************************************************/
int print_verilog_template_testbench(
const ModuleManager &module_manager,
const BitstreamManager &bitstream_manager,
const ConfigProtocol &config_protocol, const CircuitLibrary &circuit_lib,
const FabricGlobalPortInfo &global_ports, const AtomContext &atom_ctx,
const PlacementContext &place_ctx, const PinConstraints &pin_constraints,
const BusGroup &bus_group, const IoLocationMap &io_location_map,
const IoNameMap &io_name_map, const ModuleNameMap &module_name_map,
const VprNetlistAnnotation &netlist_annotation,
const std::string &circuit_name, const std::string &verilog_fname,
const std::string &verilog_fname,
const VerilogTestbenchOption &options) {
std::string timer_message =
std::string(
@ -79,7 +73,7 @@ int print_verilog_template_testbench(
/* Generate a brief description on the Verilog file*/
std::string title =
std::string("A template Verilog testbench for pre-configured FPGA fabric")
std::string("A template Verilog testbench for pre-configured FPGA fabric");
print_verilog_file_header(fp, title, options.time_stamp());
print_verilog_comment(fp, std::string("Require an adaption to your needs before used for design verification!!!"));

23
openfpga/src/fpga_verilog/verilog_template_testbench.h
View File

@ -7,19 +7,10 @@
#include <string>
#include <vector>
#include "bitstream_manager.h"
#include "bus_group.h"
#include "circuit_library.h"
#include "config_protocol.h"
#include "fabric_global_port_info.h"
#include "io_location_map.h"
#include "io_name_map.h"
#include "module_manager.h"
#include "module_name_map.h"
#include "pin_constraints.h"
#include "verilog_testbench_options.h"
#include "vpr_context.h"
#include "vpr_netlist_annotation.h"
/********************************************************************
* Function declaration
@ -29,16 +20,10 @@
namespace openfpga {
int print_verilog_template_testbench(
const ModuleManager& module_manager,
const BitstreamManager& bitstream_manager,
const ConfigProtocol& config_protocol, const CircuitLibrary& circuit_lib,
const FabricGlobalPortInfo& global_ports, const AtomContext& atom_ctx,
const PlacementContext& place_ctx, const PinConstraints& pin_constraints,
const BusGroup& bus_group, const IoLocationMap& io_location_map,
const IoNameMap& io_name_map, const ModuleNameMap& module_name_map,
const VprNetlistAnnotation& netlist_annotation,
const std::string& circuit_name, const std::string& verilog_fname,
const VerilogTestbenchOption& options);
const ModuleManager &module_manager,
const IoNameMap &io_name_map, const ModuleNameMap &module_name_map,
const std::string &verilog_fname,
const VerilogTestbenchOption &options);
} /* end namespace openfpga */