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[core] code format

This commit is contained in:
tangxifan 2023-11-03 14:39:49 -07:00
parent e48de682ed
commit b780f0a552
1 changed files with 2 additions and 1 deletions
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3
openfpga/src/fpga_verilog/verilog_top_testbench.cpp
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@ -1702,7 +1702,8 @@ static void print_verilog_full_testbench_configuration_chain_bitstream(
find_fabric_regional_bitstream_max_size(fabric_bitstream,
curr_clk_ctrl_regions);
fp << "\t";
fp << TOP_TB_BITSTREAM_INDEX_REG_NAME << iclk << " <= " << regional_bitstream_max_size - curr_regional_bitstream_max_size;
fp << TOP_TB_BITSTREAM_INDEX_REG_NAME << iclk << " <= "
<< regional_bitstream_max_size - curr_regional_bitstream_max_size;
fp << ";";
fp << std::endl;
}