Baudouin Chauviere
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6f7023658e
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Revert "Correction on the cb vs sb corrdinator. Does not fix the problem though"
This reverts commit 95596bb4f8.
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2019-10-03 14:59:04 -06:00 |
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Baudouin Chauviere
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95596bb4f8
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Correction on the cb vs sb corrdinator. Does not fix the problem though
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2019-10-03 13:50:01 -06:00 |
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Baudouin Chauviere
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01ff484158
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Explicit verilog passing all tests
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2019-10-02 10:22:28 -06:00 |
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Baudouin Chauviere
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6b3e1fd410
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Get backup verilog_routing.c
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2019-10-02 08:54:56 -06:00 |
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Baudouin Chauviere
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33e50bbc8c
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fix
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2019-10-01 16:54:16 -06:00 |
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Baudouin Chauviere
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7c3ab38410
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Hot fix
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2019-10-01 16:40:16 -06:00 |
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Baudouin Chauviere
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633a12ee08
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Buggy version but need help on debugging
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2019-10-01 14:49:42 -06:00 |
tangxifan
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b082e60c10
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start refactoring instanciation of memory modules
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2019-09-29 18:20:56 -06:00 |
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tangxifan
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3726e691f4
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simplify the local wire generation for ccffs
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2019-09-28 21:36:56 -06:00 |
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tangxifan
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1983e56557
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make local configuration bus generation more general
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2019-09-28 21:02:14 -06:00 |
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tangxifan
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433fc73460
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refactored local encoder support for Verilog MUX generation
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2019-09-27 23:10:43 -06:00 |
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tangxifan
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4da5035627
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Connect CCFFs in a chain in a Verilog module
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2019-09-27 20:50:12 -06:00 |
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tangxifan
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f0949fea2f
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Merge branch 'dev' into refactoring
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2019-09-27 18:09:58 -06:00 |
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tangxifan
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1e187f3d15
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start adding memory circuit to Switch blocks
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2019-09-27 18:08:37 -06:00 |
AurelienUoU
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640922accd
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Merge remote-tracking branch 'origin/dev' into heterogeneous
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2019-09-27 16:54:13 -06:00 |
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AurelienUoU
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a93d7e57f7
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Scan chain support in directlist
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2019-09-27 16:53:00 -06:00 |
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tangxifan
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167778cf57
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refactoring MUX Verilog instanciation in Switch block
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2019-09-27 16:05:47 -06:00 |
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tangxifan
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dbe1625267
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Refactored Verilog wiring for formal verification ports in Switch Blocks
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2019-09-27 13:51:22 -06:00 |
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tangxifan
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ead014e7d8
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refactoring the configuration bus Verilog generation for MUXes
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2019-09-27 11:47:34 -06:00 |
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tangxifan
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091bbd4d9c
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start refactoring the num_config_bits for circuit model
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2019-09-26 22:53:07 -06:00 |
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tangxifan
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8ccf681749
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Merge branch 'dev' into refactoring
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2019-09-26 21:00:19 -06:00 |
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tangxifan
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f0589cc2cf
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refactoring mux Verilog generation for switch blocks
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2019-09-26 20:59:19 -06:00 |
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tangxifan
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05eaa412b1
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refactored short-connection of switch block
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2019-09-26 14:31:05 -06:00 |
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AurelienUoU
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3b13c959f3
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Finish renaming SCFF to CCFF
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2019-09-26 14:04:40 -06:00 |
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AurelienUoU
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c4449b667f
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Merge remote-tracking branch 'origin/dev' into heterogeneous
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2019-09-26 11:34:59 -06:00 |
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AurelienUoU
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056219f180
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Rename SCFF to CCFF, configuration chain flip flop
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2019-09-26 11:32:57 -06:00 |
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tangxifan
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ea0da49e04
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Merge branch 'dev' into refactoring
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2019-09-25 21:06:06 -06:00 |
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tangxifan
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5bb40e7f74
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refactored local wire generation for Switch block
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2019-09-25 21:05:02 -06:00 |
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AurelienUoU
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e5faeb1400
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Merge remote-tracking branch 'origin/dev' into heterogeneous
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2019-09-25 16:50:53 -06:00 |
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AurelienUoU
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a35e2936b2
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Fix verilog generation for direct connexion from directlist
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2019-09-25 16:44:00 -06:00 |
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tangxifan
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2b0e2615fa
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refactored sram port addition to module manager
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2019-09-25 16:09:58 -06:00 |
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tangxifan
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c911f15a67
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add formal verification port to SB Verilog generation
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2019-09-23 21:15:45 -06:00 |
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tangxifan
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e1742b68ef
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add pre-processing flag support for module manager
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2019-09-23 20:25:53 -06:00 |
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tangxifan
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d2ddbc19a3
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refactoring the reserved sram port generation
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2019-09-22 16:38:16 -06:00 |
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tangxifan
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2c4372c506
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add reserved BLB/WL port naming
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2019-09-22 12:16:43 -06:00 |
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tangxifan
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1e4177067d
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remove port size in the module definition
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2019-09-22 11:21:43 -06:00 |
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tangxifan
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0ff0c8cf06
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bug fix for IO=1
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2019-09-19 15:43:25 -06:00 |
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tangxifan
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0f0d06aad7
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add non-LUT intermediate buffer to test and apply minor bug fix
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2019-09-18 15:04:51 -06:00 |
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tangxifan
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d7ac7d3649
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start refactoring the switch block verilog generation
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2019-09-17 20:40:26 -06:00 |
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tangxifan
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2294aecef2
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remove old codes and compact new codes
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2019-09-16 20:19:14 -06:00 |
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tangxifan
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c5ee81541a
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remove dead codes in routing module generation
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2019-09-16 18:47:01 -06:00 |
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tangxifan
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0963852091
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remove useless global ports for routing channel modules
Need to rework the top-netlist generator before the new module generator can be plugged-in
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2019-09-16 18:38:37 -06:00 |
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tangxifan
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d83cad7c2e
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refactoring Verilog generation for routing channels
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2019-09-16 17:35:51 -06:00 |
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Baudouin Chauviere
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d5ebe66ad9
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Bug fix
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2019-09-16 10:57:52 -06:00 |
Ganesh Gore
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ec3854a648
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Merge remote-tracking branch 'origin/ganesh_dev' into dev
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2019-09-14 00:14:17 -06:00 |
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tangxifan
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f69ce708ca
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rework on the order of top-level functions
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2019-09-13 21:59:52 -06:00 |
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tangxifan
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29e80d157c
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Start developing BitstreamContext
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2019-09-13 21:27:47 -06:00 |
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tangxifan
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e64cfc5852
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start refactoring memory decoders
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2019-09-13 20:58:55 -06:00 |
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Baudouin Chauviere
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737cfb1086
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Correction to the explicit Verilog for FPGAs above 2x2
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2019-09-13 16:02:06 -06:00 |
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Baudouin Chauviere
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63e6ed21b5
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Fully functional
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2019-09-13 16:02:06 -06:00 |
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tangxifan
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d6fc9c1c71
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Find out the mem circuit is so correlated to the new MUX Verilog. Plug-in later
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2019-09-13 15:36:35 -06:00 |
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tangxifan
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009c0d63b5
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refactored the memory bank. Ready to plug-in the test
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2019-09-13 15:05:31 -06:00 |
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tangxifan
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99c30fa7dd
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keep refactoring the memory Verilog generation
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2019-09-13 14:02:04 -06:00 |
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tangxifan
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56f40cf46c
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light modification on Verilog Mux generation and start refactoring memory Verilog generation
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2019-09-13 12:22:57 -06:00 |
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tangxifan
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d8b9349066
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remove legacy codes
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2019-09-13 11:48:25 -06:00 |
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tangxifan
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b920f0fc38
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refactored user template Verilog generation
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2019-09-13 11:41:54 -06:00 |
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tangxifan
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0e6c88dd52
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delete legacy codes for wire Verilog generation
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2019-09-12 21:06:53 -06:00 |
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tangxifan
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c20e182484
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plugged in the refactored wire Verilog generation
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2019-09-12 20:56:30 -06:00 |
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tangxifan
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2b829238b5
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refactored wire Verilog generation
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2019-09-12 20:49:02 -06:00 |
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tangxifan
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79fa858f36
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remove unused ports for Verilog modules
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2019-09-11 19:39:59 -06:00 |
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tangxifan
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2bed51bf29
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minor bug fix for echo
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2019-09-11 17:41:45 -06:00 |
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tangxifan
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0399319212
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refactored LUT Verilog generation
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2019-09-11 17:04:43 -06:00 |
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tangxifan
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6a5b50facf
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refactored RRAM MUX verilog generation
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2019-09-10 20:45:44 -06:00 |
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tangxifan
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0711aa1bd6
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minor bug fixing
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2019-09-10 16:56:14 -06:00 |
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tangxifan
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82683d49cf
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remove legacy codes of local encoders
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2019-09-10 15:34:20 -06:00 |
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tangxifan
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5f561ef5e3
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pass regression test when plug in refactored local encoders
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2019-09-10 15:26:47 -06:00 |
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tangxifan
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62853c092f
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refactoring local encoders. Ready to plug in
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2019-09-10 15:16:29 -06:00 |
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Ganesh Gore
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d64bb18346
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Separated Modelsim tcl script generation
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2019-09-07 12:36:22 -04:00 |
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tangxifan
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59edd49862
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refactored CMOS MUX buffering
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2019-09-06 16:39:34 -06:00 |
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tangxifan
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bc9d95408e
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bug fixed and refactored intermediate buffer addition
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2019-09-05 16:09:28 -06:00 |
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tangxifan
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e623c19055
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implementing mux Verilog generation. Bugs detected, fixing ongoing
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2019-09-04 23:54:53 -06:00 |
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tangxifan
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fde9c8b4ec
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add frac_lut outputs to mux_graph generation
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2019-09-03 23:19:24 -06:00 |
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tangxifan
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b6bb433edc
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bug fixing for datapath mux size in Verilog generation
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2019-09-03 18:09:21 -06:00 |
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tangxifan
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4d183a3fe4
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start developing mux Verilog module generation
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2019-09-03 16:59:03 -06:00 |
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tangxifan
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a8c803f08f
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try to fix bugs in explicit port mapping
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2019-09-02 16:37:43 -06:00 |
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tangxifan
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d2d750a15c
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debugged rram mux branch Verilog generation
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2019-09-02 16:21:29 -06:00 |
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tangxifan
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395bf4fbdf
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refactored rram mux generation
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2019-09-02 14:30:18 -06:00 |
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tangxifan
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f04565386f
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refactored behavioral mux branch verilog generation
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2019-08-27 18:39:25 -06:00 |
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tangxifan
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ab6f1a5461
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add mux output ids for mux_graph
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2019-08-26 21:21:50 -06:00 |
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tangxifan
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b6617a5adf
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fix bugs in verilog comment lines
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2019-08-25 16:37:46 -06:00 |
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tangxifan
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14db2bf1a9
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minor fixing on comment
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2019-08-25 16:35:49 -06:00 |
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tangxifan
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706b7f3427
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Merge branch 'refactoring' of https://github.com/LNIS-Projects/OpenFPGA into refactoring
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2019-08-25 15:52:04 -06:00 |
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tangxifan
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1cfc117b32
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developed verilog instance writer. refactoring on mux ongoing
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2019-08-25 15:47:57 -06:00 |
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tangxifan
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056c45321b
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plug in module manager
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2019-08-25 15:44:31 -06:00 |
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tangxifan
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8fc258cc93
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develop and plug mux_lib_builder, refactoring the mux submodule generation
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2019-08-25 15:33:37 -06:00 |
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tangxifan
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c43fabb43c
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developed verilog instance writer. refactoring on mux ongoing
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2019-08-25 10:31:45 -06:00 |
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tangxifan
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fe7dfd59c3
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Merge branch 'refactoring' of https://github.com/LNIS-Projects/OpenFPGA into refactoring
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2019-08-24 23:54:37 -06:00 |
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tangxifan
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63f40f48fa
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develop and plug mux_lib_builder, refactoring the mux submodule generation
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2019-08-24 19:23:33 -06:00 |
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tangxifan
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27b619554d
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add stats for verilog modules
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2019-08-23 20:23:42 -06:00 |
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tangxifan
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ad06e9c98c
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plug in module manager
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2019-08-23 20:23:41 -06:00 |
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tangxifan
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39853408dd
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add recursive global port searching for circuit library
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2019-08-23 20:23:41 -06:00 |
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tangxifan
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fcb31e4c24
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add stats for verilog modules
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2019-08-23 18:41:16 -06:00 |
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tangxifan
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8eebca9daa
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plug in module manager
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2019-08-23 17:39:29 -06:00 |
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tangxifan
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37a092e885
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add recursive global port searching for circuit library
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2019-08-23 16:36:30 -06:00 |
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tangxifan
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931b042750
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refactoring module manager
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2019-08-23 12:52:01 -06:00 |
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tangxifan
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732e24767f
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developing module manager
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2019-08-22 23:49:35 -06:00 |
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tangxifan
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3f45e6cc87
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remove dead codes for essential gates code generation
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2019-08-22 10:01:52 -06:00 |
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tangxifan
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43de2d7636
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some tuning on Verilog port formatting
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2019-08-21 23:47:50 -06:00 |
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tangxifan
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1be5632e92
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minor tuning on the delay assignment
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2019-08-21 23:11:54 -06:00 |
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tangxifan
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7b0c55ce15
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try to reduce precision in timing assignment of Verilog netlist (travis iverilog was not happy)
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2019-08-21 22:45:48 -06:00 |