Clifford Wolf
71c38d9de5
Add $specrule cells for $setup/$hold/$skew specify rules
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-23 21:36:59 +02:00
Clifford Wolf
e807e88b60
Rename T_{RISE,FALL}_AVG to T_{RISE,FALL}_TYP to better match verilog std nomenclature
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-23 21:36:59 +02:00
Clifford Wolf
a7e11261bd
Add $specify2 and $specify3 cells to simlib
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-23 21:36:59 +02:00
Eddie Hung
45ddd9066e
synth to take -abc9 argument
2019-02-20 11:08:49 -08:00
Clifford Wolf
da1c8d8d3d
Merge pull request #772 from whitequark/synth_lut
...
synth: add k-LUT mode
2019-01-02 15:44:57 +01:00
Clifford Wolf
00330c741a
Merge pull request #771 from whitequark/techmap_cmp2lut
...
cmp2lut: new techmap pass
2019-01-02 15:43:10 +01:00
whitequark
efa278e232
Fix typographical and grammatical errors and inconsistencies.
...
The initial list of hits was generated with the codespell command
below, and each hit was evaluated and fixed manually while taking
context into consideration.
DIRS="kernel/ frontends/ backends/ passes/ techlibs/"
DIRS="${DIRS} libs/ezsat/ libs/subcircuit"
codespell $DIRS -S *.o -L upto,iff,thru,synopsys,uint
More hits were found by looking through comments and strings manually.
2019-01-02 13:12:17 +00:00
whitequark
18174202a9
synth: add k-LUT mode.
2019-01-02 08:25:03 +00:00
whitequark
fdff32dd73
synth: improve script documentation. NFC.
2019-01-02 08:05:44 +00:00
whitequark
a91892bba4
cmp2lut: new techmap pass.
2019-01-02 07:53:31 +00:00
whitequark
9ef078848a
gate2lut: new techlib, for converting Yosys gates to FPGA LUTs.
2018-12-05 17:13:27 +00:00
whitequark
12596b5003
Fix typo.
2018-12-05 17:13:27 +00:00
Henner Zeller
3aa4484a3c
Consistent use of 'override' for virtual methods in derived classes.
...
o Not all derived methods were marked 'override', but it is a great
feature of C++11 that we should make use of.
o While at it: touched header files got a -*- c++ -*- for emacs to
provide support for that language.
o use YS_OVERRIDE for all override keywords (though we should probably
use the plain keyword going forward now that C++11 is established)
2018-07-20 23:51:06 -07:00
Clifford Wolf
7fecc3c199
Make -nordff the default in "prep"
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-05-30 13:17:09 +02:00
Clifford Wolf
27dd500d31
Add "synth -noshare"
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-03-04 17:13:45 +01:00
Clifford Wolf
eb67a7532b
Add $allconst and $allseq cell types
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-02-23 13:14:47 +01:00
Clifford Wolf
b66d50e62d
Fix minor typo in "prep" help message
2017-12-19 21:44:05 +01:00
Clifford Wolf
e7a984a4df
Add dff2ff.v techmap file
2017-05-31 11:45:58 +02:00
Clifford Wolf
05cdd58c8d
Add $_ANDNOT_ and $_ORNOT_ gates
2017-05-17 09:08:29 +02:00
Clifford Wolf
5f1d0b1024
Add $live and $fair cell types, add support for s_eventually keyword
2017-02-25 10:36:39 +01:00
Clifford Wolf
3928482a3c
Add $cover cell type and SVA cover() support
2017-02-04 14:14:26 +01:00
Clifford Wolf
bdc316db50
Added $anyseq cell type
2016-10-14 15:24:03 +02:00
Clifford Wolf
53655d173b
Added $global_clock verilog syntax support for creating $ff cells
2016-10-14 12:33:56 +02:00
Clifford Wolf
8ebba8a35f
Added $ff and $_FF_ cell types
2016-10-12 01:18:39 +02:00
Clifford Wolf
76352c99c9
Added "prep -nokeepdc"
2016-09-30 17:02:52 +02:00
Clifford Wolf
2ee9bf10d0
Added "prep -nomem"
2016-08-30 23:57:24 +02:00
Clifford Wolf
6f41e5277d
Removed $aconst cell type
2016-08-30 19:09:56 +02:00
Clifford Wolf
eae390ae17
Removed $predict again
2016-08-28 21:35:33 +02:00
Clifford Wolf
d77a914683
Added "wreduce -memx"
2016-08-20 12:52:50 +02:00
Clifford Wolf
15ef608453
Added memory_memx pass, "memory -memx", and "prep -memx"
2016-08-19 19:48:26 +02:00
Clifford Wolf
4056312987
Added $anyconst and $aconst
2016-07-27 15:41:22 +02:00
Clifford Wolf
5c166e76e5
Added $initstate cell type and vlog function
2016-07-21 14:23:22 +02:00
Clifford Wolf
d7763634b6
After reading the SV spec, using non-standard predict() instead of expect()
2016-07-21 13:34:33 +02:00
Clifford Wolf
721f1f5ecf
Added basic support for $expect cells
2016-07-13 16:56:17 +02:00
Clifford Wolf
cdb58f68ab
Added "prep -auto-top" and "synth -auto-top"
2016-07-11 11:40:55 +02:00
Clifford Wolf
95757efb25
Improved support for $sop cells
2016-06-17 16:31:16 +02:00
Clifford Wolf
52bb1b968d
Added $sop cell type and "abc -sop"
2016-06-17 13:50:09 +02:00
Clifford Wolf
52b0b4e31e
Do not run "wreduce" in "prep -ifx"
2016-06-08 12:14:32 +02:00
Clifford Wolf
2032e6d8e4
Added "proc_mux -ifx"
2016-06-06 17:15:50 +02:00
Clifford Wolf
09ffebb995
Added "prep -flatten" and "synth -flatten"
2016-04-24 00:48:33 +02:00
Clifford Wolf
77aa2031e7
Converted "prep" to ScriptPass
2016-04-24 00:48:06 +02:00
Clifford Wolf
0bc95f1e04
Added "yosys -D" feature
2016-04-21 23:28:37 +02:00
Clifford Wolf
2553319081
Added ScriptPass helper class for script-like passes
2016-03-31 11:16:34 +02:00
Clifford Wolf
1d0f0d668a
Renamed opt_const to opt_expr
2016-03-31 08:46:56 +02:00
Clifford Wolf
19c20235b5
Added more cell help messages
2016-03-29 15:14:43 +02:00
Clifford Wolf
bd10927f45
Progress in cell library documentation
2016-02-01 13:58:10 +01:00
Clifford Wolf
f1b959dc69
Run opt_const before check in default scripts
2015-12-22 11:15:05 +01:00
Clifford Wolf
bbcbf739e6
Progress on cell help messages
2015-10-20 16:49:11 +02:00
Clifford Wolf
5d1c0ce7c0
Progress on cell help messages
2015-10-17 02:35:19 +02:00
Clifford Wolf
25c1f6e605
Added "prep" command
2015-10-14 22:46:41 +02:00
Clifford Wolf
87adb523aa
Added more cell descriptions
2015-10-14 20:30:59 +02:00
Clifford Wolf
7d3a3a3173
Added first help messages for cell types
2015-10-14 16:27:42 +02:00
Clifford Wolf
924d9d6e86
Added read-enable to memory model
2015-09-25 12:23:11 +02:00
Clifford Wolf
d5b1a90b33
Added $tribuf and $_TBUF_ sim models
2015-08-16 13:05:32 +02:00
Clifford Wolf
ff50bc2ac3
Added $tribuf and $_TBUF_ cell types
2015-08-16 12:54:52 +02:00
Larry Doolittle
6c00704a5e
Another block of spelling fixes
...
Smaller this time
2015-08-14 23:27:05 +02:00
Clifford Wolf
e4ef000b70
Adjust makefiles to work with out-of-tree builds
...
This is based on work done by Larry Doolittle
2015-08-12 15:04:44 +02:00
Clifford Wolf
8d6d5c30d9
Added WORDS parameter to $meminit
2015-07-31 10:40:09 +02:00
Clifford Wolf
f0c9a099d2
Added "synth -nofsm"
2015-07-02 15:25:38 +02:00
Clifford Wolf
6c84341f22
Fixed trailing whitespaces
2015-07-02 11:14:30 +02:00
Clifford Wolf
ed128b82d7
Added "synth -nordff -noalumacc"
2015-06-15 17:07:40 +02:00
Clifford Wolf
794d22969d
Added simplemap $lut support
2015-04-27 10:16:07 +02:00
Clifford Wolf
95944eb69e
make all vector-size related integer params in $mem sim model signed
...
this fixes iverilog crashes such as the following:
warning: verinum::as_long() truncated 32 bits to 31, returns 2147483647
draw_net_input.c:711: Error: malloc() ran out of memory.
2015-04-05 17:26:53 +02:00
Clifford Wolf
706631225e
Added $_MUX4_, $_MUX8_, and $_MUX16_ cell types
2015-04-05 09:45:14 +02:00
Clifford Wolf
b005eedf36
Added $assume cell type
2015-02-26 18:04:10 +01:00
Clifford Wolf
4d34d031f9
Added "stat" to "synth" and "synth_xilinx"
2015-02-15 13:25:15 +01:00
Clifford Wolf
881dcd8af9
Added final checks to "synth" and "synth_xilinx"
2015-02-15 13:00:00 +01:00
Clifford Wolf
ec05242c27
Smaller default parameters in $mem simlib model
2015-02-15 00:20:05 +01:00
Clifford Wolf
dcf2e24240
Added $meminit support to "memory" command
2015-02-14 12:55:03 +01:00
Clifford Wolf
910556560f
Added $meminit cell type
2015-02-14 10:23:03 +01:00
Clifford Wolf
04cb947d6a
Added "check" command
2015-02-13 14:34:51 +01:00
Clifford Wolf
d58c3eca3a
Some test related fixes
...
(incl. removal of three bad test cases)
2015-02-12 17:45:44 +01:00
Clifford Wolf
1df81f92ce
Added "make mklibyosys", some minor API changes
2015-02-01 13:38:46 +01:00
Clifford Wolf
bedd46338f
Added "fsm -encfile"
2015-01-30 22:46:53 +01:00
Clifford Wolf
e13a45ae61
Added $equiv cell type
2015-01-19 11:55:05 +01:00
Clifford Wolf
3ed4e34380
Added cells.lib
2015-01-16 15:50:42 +01:00
Clifford Wolf
1d96277f5d
Added add_share_file Makefile macro
2015-01-08 00:23:18 +01:00
Clifford Wolf
a7e43ae3d9
Progress in memory_bram
2015-01-03 10:57:01 +01:00
Clifford Wolf
90f4017703
Added proper clkpol support to memory_bram
2015-01-02 22:57:08 +01:00
Clifford Wolf
474831643c
New $mem simlib model
2015-01-02 17:11:31 +01:00
Clifford Wolf
ba43cf5807
Fixed simlib entries for $memrd and $memwr
2014-12-30 13:33:29 +01:00
Clifford Wolf
c64b1de11d
Fixed build with SMALL=1
2014-12-30 11:41:24 +01:00
Clifford Wolf
4aa9fbbf3f
Improvements in simplemap api, added $ne $nex $eq $eqx support
2014-12-24 10:49:24 +01:00
Clifford Wolf
72f500c950
Removed UTF-8 chars from techmap.v
2014-12-12 12:44:16 +01:00
Clifford Wolf
f1764b4fe9
Added $dffe cell type
2014-12-08 10:50:19 +01:00
Clifford Wolf
fad9cec47b
Added $_DFFE_??_ cell types
2014-12-08 10:43:38 +01:00
Clifford Wolf
74ef92b9c8
Added "abc" label in synth script
2014-10-31 03:46:27 +01:00
Clifford Wolf
ab28491f27
Added "opt -full" alias for all more aggressive optimizations
2014-10-31 03:36:51 +01:00
Clifford Wolf
c3e779a65f
Added $_BUF_ cell type
2014-10-03 10:12:28 +02:00
Clifford Wolf
f9a307a50b
namespace Yosys
2014-09-27 16:17:53 +02:00
Clifford Wolf
4888d61c65
Improvements in "synth" script
2014-09-18 12:57:55 +02:00
Clifford Wolf
6644e27cd4
Fixed $macc simlib model for zero-config
2014-09-16 08:19:35 +02:00
Clifford Wolf
7815f81c32
Added "synth" command
2014-09-14 16:09:06 +02:00
Clifford Wolf
923bbbeaf0
Using alumacc in techmap.v
2014-09-14 14:50:15 +02:00
Clifford Wolf
44b5bd4b63
Fixed simlib $macc model for xilinx xsim
2014-09-08 17:09:39 +02:00
Clifford Wolf
fcb46138ce
Simplified $fa undef model
2014-09-08 16:59:39 +02:00
Clifford Wolf
6dc07eb1f2
Fixes and cleanups for blackbox.v
2014-09-08 13:31:04 +02:00
Clifford Wolf
af0c8873bb
Added $lcu cell type
2014-09-08 13:31:04 +02:00
Clifford Wolf
d46bac3305
Added "$fa" cell type
2014-09-08 12:15:39 +02:00
Clifford Wolf
dd887cc025
Using maccmap for $macc and $mul techmap
2014-09-07 18:24:08 +02:00
Clifford Wolf
9329a76818
Various bug fixes (related to $macc model testing)
2014-09-06 20:30:46 +02:00
Clifford Wolf
fa64942018
Added $macc SAT model
2014-09-06 19:44:11 +02:00
Clifford Wolf
bff4706b62
Added $macc simlib model (also use as techmap rule for now)
2014-09-06 17:59:12 +02:00
Clifford Wolf
8927aa6148
Removed $bu0 cell type
2014-09-04 02:07:52 +02:00
Clifford Wolf
635b922afe
Undef-related fixes in simlib $alu model
2014-09-02 23:21:59 +02:00
Clifford Wolf
c38283dbd0
Small bug fixes in $not, $neg, and $shiftx models
2014-09-02 17:48:41 +02:00
Clifford Wolf
9923762461
Fixed "test_cell -simlib all"
2014-09-01 15:37:56 +02:00
Clifford Wolf
8649b57b6f
Added $lut support in test_cell, techmap, satgen
2014-08-31 17:43:31 +02:00
Clifford Wolf
4724d94fbc
Added $alu cell type
2014-08-30 18:59:05 +02:00
Clifford Wolf
eb571cba6a
Replaced $__alu CO/CS outputs with full-width CO output
2014-08-30 15:12:39 +02:00
Clifford Wolf
a92a68ce52
Using "via_celltype" in $mul carry-save-acc implementation
2014-08-18 14:30:20 +02:00
Clifford Wolf
6f33fc3e87
Performance fix for new $__lcu techmap rule
2014-08-18 00:27:54 +02:00
Clifford Wolf
4b3834e0cc
Replaced recursive lcu scheme with bk adder
2014-08-18 00:03:33 +02:00
Clifford Wolf
976bda7102
Multiply using a carry-save accumulator
2014-08-16 21:07:29 +02:00
Clifford Wolf
47c2637a96
Added additional gate types: $_NAND_ $_NOR_ $_XNOR_ $_AOI3_ $_OAI3_ $_AOI4_ $_OAI4_
2014-08-16 18:29:39 +02:00
Clifford Wolf
1ddf150c35
Changes in techmap $__alu interface
2014-08-16 16:01:58 +02:00
Clifford Wolf
b64b38eea2
Renamed $lut ports to follow A-Y naming scheme
2014-08-15 14:18:40 +02:00
Clifford Wolf
f092b50148
Renamed $_INV_ cell type to $_NOT_
2014-08-15 14:11:40 +02:00
Clifford Wolf
5602cbde9f
Simplified $__arraymul techmap rule
2014-08-14 20:53:21 +02:00
Clifford Wolf
13f2f36884
RIP $safe_pmux
2014-08-14 11:39:46 +02:00
Clifford Wolf
7e758d5fbb
Added techmap support for actual lookahead carry unit
2014-08-13 18:40:57 +02:00
Clifford Wolf
9a065509ac
Preparations for lookahead ALU support in techmap.v
2014-08-13 16:36:30 +02:00
Clifford Wolf
c27120fcbc
New interface for $__alu in techmap.v
2014-08-13 13:04:28 +02:00
Clifford Wolf
312ee00c9e
Added adff2dff.v (for techmap -share_map)
2014-08-07 16:14:38 +02:00
Clifford Wolf
014a41fcf3
Implemented recursive techmap
2014-08-03 12:40:43 +02:00
Clifford Wolf
1202f7aa4b
Renamed "stdcells.v" to "techmap.v"
2014-07-31 02:32:00 +02:00
Clifford Wolf
41555cde10
Reorganized stdcells.v (no actual code change, just moved and indented stuff)
2014-07-31 02:21:06 +02:00
Clifford Wolf
2541489105
Added techmap CONSTMAP feature
2014-07-30 22:04:30 +02:00
Clifford Wolf
6c05badc43
New techmap default rules for $shr $sshr $shl $sshl
2014-07-30 18:49:12 +02:00
Clifford Wolf
2145e57ef0
Bugfix in simlib.v for iverilog
2014-07-29 19:23:31 +02:00
Clifford Wolf
397b00252d
Added $shift and $shiftx cell types (needed for correct part select behavior)
2014-07-29 16:35:13 +02:00
Clifford Wolf
b17d6531c8
Added "make PRETTY=1"
2014-07-24 17:15:01 +02:00
Clifford Wolf
f1ca93a0a3
Fixed simlib.v model for $mem
2014-07-17 16:48:36 +02:00
Clifford Wolf
dcdd5c11b4
Updated simlib to new $mem/$memwr interface
2014-07-16 11:46:40 +02:00
Clifford Wolf
7370ae01e9
Added SIMLIB_NOLUT to simlib.v
2014-04-02 21:28:33 +02:00
Clifford Wolf
e24797add0
Added SIMLIB_NOSR to simlib.v
2014-04-02 21:06:55 +02:00
Clifford Wolf
d4a1b0af5b
Added support for dlatchsr cells
2014-03-31 14:14:40 +02:00
Clifford Wolf
7aa2d746b7
Merged addition of SED makefile variable from github.com/Siesh1oo/yosys
...
(see https://github.com/cliffordwolf/yosys/pull/28 )
2014-03-11 14:42:58 +01:00
Clifford Wolf
973507d85b
Fixes for improved techmap of shifts with large B inputs
2014-03-06 13:33:12 +01:00
Clifford Wolf
8406e7f7b6
Strictly zero-extend unsigned A-inputs of shift operations in techmap
2014-03-06 12:15:44 +01:00
Clifford Wolf
d7f29bb23f
Improved techmap of shift with wide B inputs
2014-03-06 12:14:20 +01:00
Clifford Wolf
fc3b3c4ec3
Added $slice and $concat cell types
2014-02-07 17:44:57 +01:00
Clifford Wolf
a6750b3753
Added TRANSPARENT parameter to $memrd (and RD_TRANSPARENT to $mem)
2014-02-03 13:01:45 +01:00
Clifford Wolf
ed8ad99960
More changes to techlibs/common/simlib.v for LEC
2014-01-31 11:21:29 +01:00
Clifford Wolf
a86f33653d
Major rewrite of techlibs/common/simlib.v for LEC (cadance conformal)
2014-01-29 00:36:03 +01:00
Clifford Wolf
1e67099b77
Added $assert cell
2014-01-19 14:03:40 +01:00
Clifford Wolf
3d7a1491aa
Fixed $lut simlib model for a wider range of tools
2014-01-18 19:31:40 +01:00
Clifford Wolf
2fbaaaca7a
More changes to simlib to make it friendlier to a wider range of tools
2014-01-18 19:13:43 +01:00
Clifford Wolf
4a9e133fab
Fixed a type in $mem model in simlib.v
2014-01-18 18:54:50 +01:00
Clifford Wolf
bef17eeb10
Removed cases of trailing comma in stdcells.v
2014-01-18 15:36:17 +01:00
Clifford Wolf
5b96675696
Added $bu0 cell to simlib.v
2014-01-18 15:35:15 +01:00
Clifford Wolf
db9cf544b8
Added techlibs/common/pmux2mux.v
2014-01-17 20:06:15 +01:00
Clifford Wolf
b3b00f1bf4
Various small cleanups in stdcells.v techmap code
2013-12-31 15:41:40 +01:00
Clifford Wolf
c69c416d28
Added $bu0 cell (for easy correct $eq/$ne mapping)
2013-12-28 12:02:14 +01:00
Clifford Wolf
369bf81a70
Added support for non-const === and !== (for miter circuits)
2013-12-27 14:20:15 +01:00
Clifford Wolf
76f7c10cfc
Using simplemap mappers from techmap
2013-11-24 23:31:14 +01:00
Clifford Wolf
1afe6589df
Renamed stdcells_sim.v to simcells.v and fixed blackbox.v
2013-11-24 20:44:00 +01:00
Clifford Wolf
0c91f890c9
Install simlib in datdir
2013-11-19 23:05:46 +01:00
Clifford Wolf
e5b974fa2a
Cleanups and bugfixes in response to new internal cell checker
2013-11-11 00:39:45 +01:00
Clifford Wolf
404b46674b
Fixed techmap of $reduce_xnor with multi-bit outputs
2013-11-07 00:58:06 +01:00
Clifford Wolf
b41740060b
Fixed techmap of $gt and $ge with multi-bit outputs
2013-11-06 22:59:45 +01:00
Clifford Wolf
6fcbc79b5c
Improved width extension with regard to undef propagation
2013-11-06 21:05:11 +01:00
Clifford Wolf
0836a1f2ba
Bugfix in dffsr techmap rules
2013-10-18 13:24:44 +02:00
Clifford Wolf
8197169f8d
Added techmap rules for $sr, $dffsr and $dlatch
2013-10-18 12:29:21 +02:00
Clifford Wolf
e0f693cbb0
Added $_SR_[PN][PN]_, $_DFFSR_[PN][PN][PN]_, $_DLATCH_[PN]_
2013-10-18 12:13:34 +02:00
Clifford Wolf
5998c101a4
Added $sr, $dffsr and $dlatch cell types
2013-10-18 11:56:16 +02:00
Clifford Wolf
288ba9618a
Moved common techlib files to techlibs/common
2013-09-15 11:52:57 +02:00