Clifford Wolf
023086bd46
Add $_NMUX_, add "abc -g cmos", add proper cmos cell costs
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-08-06 04:47:55 +02:00
Eddie Hung
105aaeaf59
Trim Y_WIDTH
2019-08-01 14:33:16 -07:00
Eddie Hung
65de9aaaa9
Add DSP_SIGNEDONLY back
2019-08-01 14:29:00 -07:00
Eddie Hung
915f4e34bf
DSP_MINWIDTH -> DSP_{A,B,Y}_MINWIDTH
2019-08-01 13:20:34 -07:00
Eddie Hung
332b86491d
Revert "Do not do sign extension in techmap; let packer do it"
...
This reverts commit 595a8f032f
.
2019-08-01 12:17:14 -07:00
Eddie Hung
7e86c8bcfb
Fix B_WIDTH > DSP_B_MAXWIDTH case
2019-08-01 10:01:43 -07:00
Eddie Hung
d2c33863d0
Do not compute sign bit if result is zero
2019-07-31 16:04:19 -07:00
Eddie Hung
60c4887d15
For signed multipliers, compute sign bit separately...
2019-07-31 15:45:41 -07:00
Eddie Hung
2f71c2c219
Fix spacing
2019-07-26 15:30:51 -07:00
Eddie Hung
c39ccc65e9
Add copyright header, comment on cascade
2019-07-24 10:49:09 -07:00
Eddie Hung
151c5c96c0
Typo for Y_WIDTH
2019-07-23 15:05:20 -07:00
Eddie Hung
3a7aeb028d
Use minimum sized width wires
2019-07-22 13:01:26 -07:00
Eddie Hung
47fd042b9f
Indirection via $__soft_mul
2019-07-19 20:20:33 -07:00
Eddie Hung
595a8f032f
Do not do sign extension in techmap; let packer do it
2019-07-19 15:50:13 -07:00
Eddie Hung
bba72f03dd
Do not $mul -> $__mul if A and B are less than maxwidth
2019-07-19 11:54:26 -07:00
Eddie Hung
1d14cec7fd
Add a DSP_MINWIDTH macro, and soft-logic for {A_WIDTH,B_WIDTH} <= 1 too
2019-07-19 11:39:24 -07:00
Eddie Hung
7bdb3996e2
Merge branch 'xc7dsp' into ice40dsp
2019-07-19 10:28:38 -07:00
Eddie Hung
ca94c2d3c4
Fix typo in B
2019-07-19 10:27:44 -07:00
Eddie Hung
2168568f43
Use sign_headroom instead
2019-07-19 09:16:13 -07:00
Eddie Hung
0157043b97
Merge remote-tracking branch 'origin/master' into xc7dsp
2019-07-18 20:36:48 -07:00
Eddie Hung
15c2a79ab9
Do not define `DSP_SIGNEDONLY macro if no exists
2019-07-18 16:04:58 -07:00
Eddie Hung
42e40dbd0a
Merge remote-tracking branch 'origin/master' into ice40dsp
2019-07-18 15:45:25 -07:00
Eddie Hung
2339b7fc37
mul2dsp to create cells that can be interchanged with $mul
2019-07-18 15:37:35 -07:00
Eddie Hung
e22a752242
Make consistent
2019-07-18 15:21:23 -07:00
Eddie Hung
8326af5418
Fix signed multiplier decomposition
2019-07-18 13:11:26 -07:00
Eddie Hung
2024357f32
Working for unsigned
2019-07-18 10:53:18 -07:00
Eddie Hung
d5cd2c80be
Cleanup
2019-07-18 09:20:48 -07:00
David Shah
16b0ccf04c
mul2dsp: Lower partial products always have unsigned inputs
...
Signed-off-by: David Shah <dave@ds0.me>
2019-07-18 11:33:37 +01:00
Eddie Hung
8dca8d486e
Fix mul2dsp signedness
2019-07-17 12:44:52 -07:00
Eddie Hung
1b62b82e05
A_SIGNED == B_SIGNED so flip both
2019-07-17 11:34:18 -07:00
Eddie Hung
0b6d47f8bf
Add DSP_{A,B}_SIGNEDONLY macro
2019-07-16 15:55:13 -07:00
Eddie Hung
569cd66764
Merge branch 'xc7dsp' of github.com:YosysHQ/yosys into xc7dsp
2019-07-16 14:18:36 -07:00
Eddie Hung
7a58ee78dc
gen_lut to return correctly sized LUT mask
2019-07-16 12:45:29 -07:00
David Shah
8da4c1ad82
mul2dsp: Fix edge case where Y_WIDTH is less than B_WIDTH+`DSP_A_MAXWIDTH
...
Signed-off-by: David Shah <dave@ds0.me>
2019-07-16 16:44:40 +01:00
David Shah
7a75f5f3ac
mul2dsp: Fix indentation
...
Signed-off-by: David Shah <dave@ds0.me>
2019-07-16 16:19:32 +01:00
Eddie Hung
fd5b3593d8
Do not swap if equals
2019-07-15 16:52:37 -07:00
Eddie Hung
42f8e68e76
OUT port to Y in generic DSP
2019-07-15 14:45:47 -07:00
Eddie Hung
91fcf034bc
Only swap if B_WIDTH > A_WIDTH
2019-07-15 11:24:11 -07:00
Eddie Hung
1793e6018a
Tidy up
2019-07-15 11:19:54 -07:00
Eddie Hung
713337255e
Revert "Add "synth -keepdc" option"
2019-07-09 10:14:23 -07:00
Eddie Hung
dd9771cbcd
Add synth -keepdc option
2019-07-08 19:14:54 -07:00
David Shah
e78864993a
mul2dsp: Fix typo
...
Signed-off-by: David Shah <dave@ds0.me>
2019-07-08 18:42:41 +01:00
David Shah
269ff450f5
Add mul2dsp multiplier splitting rule and ECP5 mapping
...
Signed-off-by: David Shah <dave@ds0.me>
2019-07-08 18:42:09 +01:00
Eddie Hung
627a62a797
Make doc consistent
2019-06-14 10:32:46 -07:00
Eddie Hung
f7a9769c14
Merge remote-tracking branch 'origin/master' into xaig
2019-06-12 08:50:39 -07:00
Clifford Wolf
c4b8575f43
Add "wreduce -keepdc", fixes #1016
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-05-20 15:36:13 +02:00
Eddie Hung
d9c4644e88
Merge remote-tracking branch 'origin/master' into clifford/specify
2019-05-03 15:05:57 -07:00
Clifford Wolf
d2d402e625
Run "peepopt" in generic "synth" pass and "synth_ice40"
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-30 08:10:37 +02:00
Clifford Wolf
64925b4e8f
Improve $specrule interface
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-23 22:57:10 +02:00
Clifford Wolf
4575e4ad86
Improve $specrule interface
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-23 22:18:04 +02:00
Clifford Wolf
71c38d9de5
Add $specrule cells for $setup/$hold/$skew specify rules
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-23 21:36:59 +02:00
Clifford Wolf
e807e88b60
Rename T_{RISE,FALL}_AVG to T_{RISE,FALL}_TYP to better match verilog std nomenclature
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-23 21:36:59 +02:00
Clifford Wolf
a7e11261bd
Add $specify2 and $specify3 cells to simlib
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-23 21:36:59 +02:00
Eddie Hung
45ddd9066e
synth to take -abc9 argument
2019-02-20 11:08:49 -08:00
Clifford Wolf
da1c8d8d3d
Merge pull request #772 from whitequark/synth_lut
...
synth: add k-LUT mode
2019-01-02 15:44:57 +01:00
Clifford Wolf
00330c741a
Merge pull request #771 from whitequark/techmap_cmp2lut
...
cmp2lut: new techmap pass
2019-01-02 15:43:10 +01:00
whitequark
efa278e232
Fix typographical and grammatical errors and inconsistencies.
...
The initial list of hits was generated with the codespell command
below, and each hit was evaluated and fixed manually while taking
context into consideration.
DIRS="kernel/ frontends/ backends/ passes/ techlibs/"
DIRS="${DIRS} libs/ezsat/ libs/subcircuit"
codespell $DIRS -S *.o -L upto,iff,thru,synopsys,uint
More hits were found by looking through comments and strings manually.
2019-01-02 13:12:17 +00:00
whitequark
18174202a9
synth: add k-LUT mode.
2019-01-02 08:25:03 +00:00
whitequark
fdff32dd73
synth: improve script documentation. NFC.
2019-01-02 08:05:44 +00:00
whitequark
a91892bba4
cmp2lut: new techmap pass.
2019-01-02 07:53:31 +00:00
whitequark
9ef078848a
gate2lut: new techlib, for converting Yosys gates to FPGA LUTs.
2018-12-05 17:13:27 +00:00
whitequark
12596b5003
Fix typo.
2018-12-05 17:13:27 +00:00
Henner Zeller
3aa4484a3c
Consistent use of 'override' for virtual methods in derived classes.
...
o Not all derived methods were marked 'override', but it is a great
feature of C++11 that we should make use of.
o While at it: touched header files got a -*- c++ -*- for emacs to
provide support for that language.
o use YS_OVERRIDE for all override keywords (though we should probably
use the plain keyword going forward now that C++11 is established)
2018-07-20 23:51:06 -07:00
Clifford Wolf
7fecc3c199
Make -nordff the default in "prep"
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-05-30 13:17:09 +02:00
Clifford Wolf
27dd500d31
Add "synth -noshare"
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-03-04 17:13:45 +01:00
Clifford Wolf
eb67a7532b
Add $allconst and $allseq cell types
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-02-23 13:14:47 +01:00
Clifford Wolf
b66d50e62d
Fix minor typo in "prep" help message
2017-12-19 21:44:05 +01:00
Clifford Wolf
e7a984a4df
Add dff2ff.v techmap file
2017-05-31 11:45:58 +02:00
Clifford Wolf
05cdd58c8d
Add $_ANDNOT_ and $_ORNOT_ gates
2017-05-17 09:08:29 +02:00
Clifford Wolf
5f1d0b1024
Add $live and $fair cell types, add support for s_eventually keyword
2017-02-25 10:36:39 +01:00
Clifford Wolf
3928482a3c
Add $cover cell type and SVA cover() support
2017-02-04 14:14:26 +01:00
Clifford Wolf
bdc316db50
Added $anyseq cell type
2016-10-14 15:24:03 +02:00
Clifford Wolf
53655d173b
Added $global_clock verilog syntax support for creating $ff cells
2016-10-14 12:33:56 +02:00
Clifford Wolf
8ebba8a35f
Added $ff and $_FF_ cell types
2016-10-12 01:18:39 +02:00
Clifford Wolf
76352c99c9
Added "prep -nokeepdc"
2016-09-30 17:02:52 +02:00
Clifford Wolf
2ee9bf10d0
Added "prep -nomem"
2016-08-30 23:57:24 +02:00
Clifford Wolf
6f41e5277d
Removed $aconst cell type
2016-08-30 19:09:56 +02:00
Clifford Wolf
eae390ae17
Removed $predict again
2016-08-28 21:35:33 +02:00
Clifford Wolf
d77a914683
Added "wreduce -memx"
2016-08-20 12:52:50 +02:00
Clifford Wolf
15ef608453
Added memory_memx pass, "memory -memx", and "prep -memx"
2016-08-19 19:48:26 +02:00
Clifford Wolf
4056312987
Added $anyconst and $aconst
2016-07-27 15:41:22 +02:00
Clifford Wolf
5c166e76e5
Added $initstate cell type and vlog function
2016-07-21 14:23:22 +02:00
Clifford Wolf
d7763634b6
After reading the SV spec, using non-standard predict() instead of expect()
2016-07-21 13:34:33 +02:00
Clifford Wolf
721f1f5ecf
Added basic support for $expect cells
2016-07-13 16:56:17 +02:00
Clifford Wolf
cdb58f68ab
Added "prep -auto-top" and "synth -auto-top"
2016-07-11 11:40:55 +02:00
Clifford Wolf
95757efb25
Improved support for $sop cells
2016-06-17 16:31:16 +02:00
Clifford Wolf
52bb1b968d
Added $sop cell type and "abc -sop"
2016-06-17 13:50:09 +02:00
Clifford Wolf
52b0b4e31e
Do not run "wreduce" in "prep -ifx"
2016-06-08 12:14:32 +02:00
Clifford Wolf
2032e6d8e4
Added "proc_mux -ifx"
2016-06-06 17:15:50 +02:00
Clifford Wolf
09ffebb995
Added "prep -flatten" and "synth -flatten"
2016-04-24 00:48:33 +02:00
Clifford Wolf
77aa2031e7
Converted "prep" to ScriptPass
2016-04-24 00:48:06 +02:00
Clifford Wolf
0bc95f1e04
Added "yosys -D" feature
2016-04-21 23:28:37 +02:00
Clifford Wolf
2553319081
Added ScriptPass helper class for script-like passes
2016-03-31 11:16:34 +02:00
Clifford Wolf
1d0f0d668a
Renamed opt_const to opt_expr
2016-03-31 08:46:56 +02:00
Clifford Wolf
19c20235b5
Added more cell help messages
2016-03-29 15:14:43 +02:00
Clifford Wolf
bd10927f45
Progress in cell library documentation
2016-02-01 13:58:10 +01:00
Clifford Wolf
f1b959dc69
Run opt_const before check in default scripts
2015-12-22 11:15:05 +01:00
Clifford Wolf
bbcbf739e6
Progress on cell help messages
2015-10-20 16:49:11 +02:00
Clifford Wolf
5d1c0ce7c0
Progress on cell help messages
2015-10-17 02:35:19 +02:00
Clifford Wolf
25c1f6e605
Added "prep" command
2015-10-14 22:46:41 +02:00
Clifford Wolf
87adb523aa
Added more cell descriptions
2015-10-14 20:30:59 +02:00
Clifford Wolf
7d3a3a3173
Added first help messages for cell types
2015-10-14 16:27:42 +02:00
Clifford Wolf
924d9d6e86
Added read-enable to memory model
2015-09-25 12:23:11 +02:00
Clifford Wolf
d5b1a90b33
Added $tribuf and $_TBUF_ sim models
2015-08-16 13:05:32 +02:00
Clifford Wolf
ff50bc2ac3
Added $tribuf and $_TBUF_ cell types
2015-08-16 12:54:52 +02:00
Larry Doolittle
6c00704a5e
Another block of spelling fixes
...
Smaller this time
2015-08-14 23:27:05 +02:00
Clifford Wolf
e4ef000b70
Adjust makefiles to work with out-of-tree builds
...
This is based on work done by Larry Doolittle
2015-08-12 15:04:44 +02:00
Clifford Wolf
8d6d5c30d9
Added WORDS parameter to $meminit
2015-07-31 10:40:09 +02:00
Clifford Wolf
f0c9a099d2
Added "synth -nofsm"
2015-07-02 15:25:38 +02:00
Clifford Wolf
6c84341f22
Fixed trailing whitespaces
2015-07-02 11:14:30 +02:00
Clifford Wolf
ed128b82d7
Added "synth -nordff -noalumacc"
2015-06-15 17:07:40 +02:00
Clifford Wolf
794d22969d
Added simplemap $lut support
2015-04-27 10:16:07 +02:00
Clifford Wolf
95944eb69e
make all vector-size related integer params in $mem sim model signed
...
this fixes iverilog crashes such as the following:
warning: verinum::as_long() truncated 32 bits to 31, returns 2147483647
draw_net_input.c:711: Error: malloc() ran out of memory.
2015-04-05 17:26:53 +02:00
Clifford Wolf
706631225e
Added $_MUX4_, $_MUX8_, and $_MUX16_ cell types
2015-04-05 09:45:14 +02:00
Clifford Wolf
b005eedf36
Added $assume cell type
2015-02-26 18:04:10 +01:00
Clifford Wolf
4d34d031f9
Added "stat" to "synth" and "synth_xilinx"
2015-02-15 13:25:15 +01:00
Clifford Wolf
881dcd8af9
Added final checks to "synth" and "synth_xilinx"
2015-02-15 13:00:00 +01:00
Clifford Wolf
ec05242c27
Smaller default parameters in $mem simlib model
2015-02-15 00:20:05 +01:00
Clifford Wolf
dcf2e24240
Added $meminit support to "memory" command
2015-02-14 12:55:03 +01:00
Clifford Wolf
910556560f
Added $meminit cell type
2015-02-14 10:23:03 +01:00
Clifford Wolf
04cb947d6a
Added "check" command
2015-02-13 14:34:51 +01:00
Clifford Wolf
d58c3eca3a
Some test related fixes
...
(incl. removal of three bad test cases)
2015-02-12 17:45:44 +01:00
Clifford Wolf
1df81f92ce
Added "make mklibyosys", some minor API changes
2015-02-01 13:38:46 +01:00
Clifford Wolf
bedd46338f
Added "fsm -encfile"
2015-01-30 22:46:53 +01:00
Clifford Wolf
e13a45ae61
Added $equiv cell type
2015-01-19 11:55:05 +01:00
Clifford Wolf
3ed4e34380
Added cells.lib
2015-01-16 15:50:42 +01:00
Clifford Wolf
1d96277f5d
Added add_share_file Makefile macro
2015-01-08 00:23:18 +01:00
Clifford Wolf
a7e43ae3d9
Progress in memory_bram
2015-01-03 10:57:01 +01:00
Clifford Wolf
90f4017703
Added proper clkpol support to memory_bram
2015-01-02 22:57:08 +01:00
Clifford Wolf
474831643c
New $mem simlib model
2015-01-02 17:11:31 +01:00
Clifford Wolf
ba43cf5807
Fixed simlib entries for $memrd and $memwr
2014-12-30 13:33:29 +01:00
Clifford Wolf
c64b1de11d
Fixed build with SMALL=1
2014-12-30 11:41:24 +01:00
Clifford Wolf
4aa9fbbf3f
Improvements in simplemap api, added $ne $nex $eq $eqx support
2014-12-24 10:49:24 +01:00
Clifford Wolf
72f500c950
Removed UTF-8 chars from techmap.v
2014-12-12 12:44:16 +01:00
Clifford Wolf
f1764b4fe9
Added $dffe cell type
2014-12-08 10:50:19 +01:00
Clifford Wolf
fad9cec47b
Added $_DFFE_??_ cell types
2014-12-08 10:43:38 +01:00
Clifford Wolf
74ef92b9c8
Added "abc" label in synth script
2014-10-31 03:46:27 +01:00
Clifford Wolf
ab28491f27
Added "opt -full" alias for all more aggressive optimizations
2014-10-31 03:36:51 +01:00
Clifford Wolf
c3e779a65f
Added $_BUF_ cell type
2014-10-03 10:12:28 +02:00
Clifford Wolf
f9a307a50b
namespace Yosys
2014-09-27 16:17:53 +02:00
Clifford Wolf
4888d61c65
Improvements in "synth" script
2014-09-18 12:57:55 +02:00
Clifford Wolf
6644e27cd4
Fixed $macc simlib model for zero-config
2014-09-16 08:19:35 +02:00
Clifford Wolf
7815f81c32
Added "synth" command
2014-09-14 16:09:06 +02:00
Clifford Wolf
923bbbeaf0
Using alumacc in techmap.v
2014-09-14 14:50:15 +02:00
Clifford Wolf
44b5bd4b63
Fixed simlib $macc model for xilinx xsim
2014-09-08 17:09:39 +02:00
Clifford Wolf
fcb46138ce
Simplified $fa undef model
2014-09-08 16:59:39 +02:00
Clifford Wolf
6dc07eb1f2
Fixes and cleanups for blackbox.v
2014-09-08 13:31:04 +02:00
Clifford Wolf
af0c8873bb
Added $lcu cell type
2014-09-08 13:31:04 +02:00
Clifford Wolf
d46bac3305
Added "$fa" cell type
2014-09-08 12:15:39 +02:00
Clifford Wolf
dd887cc025
Using maccmap for $macc and $mul techmap
2014-09-07 18:24:08 +02:00