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2257 Commits

Author SHA1 Message Date
whitequark 2de7e92bb8 opt_lut: make less chatty. 2019-07-13 16:49:56 +00:00
Eddie Hung 9b91d815b5 If ConstEval fails do not log_abort() but return gracefully 2019-07-13 04:13:57 -07:00
Eddie Hung ab3917d079 Error out if enable > dbits 2019-07-13 03:39:23 -07:00
Eddie Hung fb062c3426 Add comment 2019-07-13 00:52:21 -07:00
Eddie Hung e9bdc86c0e duplicate -> clone 2019-07-12 19:33:02 -07:00
Eddie Hung be0cb7f4b8 More cleanup 2019-07-12 19:30:18 -07:00
Eddie Hung 7d583f9e57 Cleanup 2019-07-12 19:30:18 -07:00
Eddie Hung 83f23a24a8 Cleanup 2019-07-12 19:30:18 -07:00
Eddie Hung 1adbfb5533 Cleanup 2019-07-12 19:30:18 -07:00
Eddie Hung 39a7c7c54c More cleanup 2019-07-12 19:30:18 -07:00
Eddie Hung 91c07be196 Cleanup 2019-07-12 19:30:18 -07:00
Eddie Hung 399e1ec870 Cleanup 2019-07-12 19:30:18 -07:00
Eddie Hung 58dbb28fd3 Cleanup 2019-07-12 19:30:18 -07:00
Eddie Hung 7dc15bdd2d Do not double count cells in abc 2019-07-12 08:22:26 -07:00
Eddie Hung 237d8651a5 Error out if abc9 not called with -lut or -luts 2019-07-11 09:58:00 -07:00
Eddie Hung 0c3ed73dad Count $_NOT_ cells turned into $luts 2019-07-11 09:55:14 -07:00
Eddie Hung 33862d0445 WIP for fixing partitioning, temporarily do not partition 2019-07-11 09:22:52 -07:00
Eddie Hung c0abd18799 Enable &mfs for abc9, even if it only currently works for ice40 2019-07-11 08:49:06 -07:00
Clifford Wolf fd3d5cefad
Merge pull request #1179 from whitequark/attrmap-proc 
attrmap: also consider process, switch and case attributes
 2019-07-11 07:23:28 +02:00
Eddie Hung 9f608d6be3 write_verilog with *.v extension 2019-07-10 20:25:59 -07:00
Eddie Hung 71acd3ddcf Remove -retime from abc9, revert to abc behav with separate clock/en domains 2019-07-10 18:57:44 -07:00
Eddie Hung 052060f109 Merge remote-tracking branch 'origin/master' into xaig_dff 2019-07-10 16:05:41 -07:00
whitequark ea447220da attrmap: also consider process, switch and case attributes. 2019-07-10 12:30:53 +00:00
Clifford Wolf c66b4b9131
Merge pull request #1177 from YosysHQ/clifford/async 
Fix clk2fflogic adff reset semantic to negative hold time on reset
 2019-07-10 08:48:20 +02:00
Clifford Wolf cae26bf330
Merge pull request #1174 from YosysHQ/eddie/fix1173 
Increment _TECHMAP_BITS_CONNMAP_ by one since counting from zero
 2019-07-09 22:59:51 +02:00
Clifford Wolf 9546ccdbd3 Fix tests/various/async FFL test 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-07-09 22:44:39 +02:00
Eddie Hung c2db70f41e Increment _TECHMAP_BITS_CONNMAP_ by one since counting from zero 2019-07-09 12:14:00 -07:00
Eddie Hung 713337255e
Revert "Add "synth -keepdc" option" 2019-07-09 10:14:23 -07:00
Clifford Wolf e95ce1f7af
Merge pull request #1168 from whitequark/bugpoint-processes 
Add support for processes in bugpoint
 2019-07-09 16:59:43 +02:00
Clifford Wolf a0787c12f0
Merge pull request #1169 from whitequark/more-proc-cleanups 
A new proc_prune pass
 2019-07-09 16:59:18 +02:00
Clifford Wolf 38e942507e
Merge pull request #1163 from whitequark/more-case-attrs 
More support for case rule attributes
 2019-07-09 16:57:16 +02:00
whitequark 44bcb7a187 proc_prune: promote assigns to module connections when legal. 
This can pave the way for further transformations by exposing
identities that were previously hidden in a process to any pass that
uses SigMap. Indeed, this commit removes some ad-hoc logic from
proc_init that appears to have been tailored to the output of
genrtlil in favor of using `SigMap.apply()`. (This removal is not
optional, as the ad-hoc logic cannot cope with the result of running
proc_prune; a similar issue was fixed in proc_arst.)
 2019-07-09 09:30:58 +00:00
whitequark 5fe0ffe30f proc_prune: new pass. 
The proc_prune pass is similar in nature to proc_rmdead pass: while
proc_rmdead removes branches that never become active because another
branch preempts it, proc_prune removes assignments that never become
active because another assignment preempts them.

Genrtlil contains logic similar to the proc_prune pass, but their
purpose is different: genrtlil has to prune assignments to adapt
the semantics of blocking assignments in HDLs (latest assignment
wins) to semantics of assignments in RTLIL processes (assignment in
the most specific case wins). On the other hand proc_prune is
a general purpose RTLIL simplification that benefits all frontends,
even those not using the Yosys AST library.

The proc_prune pass is added to the proc script after proc_rmdead,
since it gives better results with fewer branches.
 2019-07-09 09:30:58 +00:00
whitequark f2fb958d44 bugpoint: add -assigns and -updates options. 2019-07-09 09:27:43 +00:00
whitequark f7a14a5678 proc_clean: add -quiet option. 
This is useful for other passes that call it often, like bugpoint.
 2019-07-09 09:27:43 +00:00
Eddie Hung 37b58f4324 Clarify 'wreduce -keepdc' doc 2019-07-08 19:15:07 -07:00
Eddie Hung b5072256f2 Update muxcover doc as per @ZirconiumX 2019-07-08 12:50:59 -07:00
Eddie Hung 3681162c8d atoi -> stoi 2019-07-08 11:00:06 -07:00
Eddie Hung a34c5612e7 Add muxcover -mux2=cost option 2019-07-08 10:59:12 -07:00
whitequark 48655dfb8b proc_mux: consider \src attribute on CaseRule. 2019-07-08 13:18:18 +00:00
Eddie Hung 35fd9b0473 Merge remote-tracking branch 'origin/master' into xaig_dff 2019-07-02 12:35:45 -07:00
David Shah d45936fe5f memory_dff: Fix checking of feedback mux input when more than one mux 
Signed-off-by: David Shah <dave@ds0.me>
 2019-07-02 13:35:50 +01:00
Eddie Hung ef757002db Also remove $__ABC_FF_ 2019-07-01 10:55:24 -07:00
Eddie Hung 699d8e3939 Merge remote-tracking branch 'origin/master' into xaig_dff 2019-07-01 10:44:42 -07:00
Gabriel L. Somlo 8cb3655ecd Make abc9 pass aware of optional ABCEXTERNAL override 
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
 2019-06-28 14:56:16 -04:00
Eddie Hung 4a2a93aa06 Fix spacing 2019-06-28 11:10:36 -07:00
Eddie Hung da5f830395
Merge pull request #1098 from YosysHQ/xaig 
"abc9" pass for timing-aware techmapping (experimental, FPGA only, no FFs)
 2019-06-28 10:59:03 -07:00
Clifford Wolf 1c7ce251f3
Merge pull request #1046 from bogdanvuk/master 
Optimizing DFFs whose initial value prevents their value from changing
 2019-06-28 08:30:18 +02:00
Eddie Hung a625854ac5 Do not use Module::remove() iterator version 2019-06-27 15:29:20 -07:00
Eddie Hung 137c91d9a9 Remove &retime when abc9 -fast 2019-06-27 15:17:39 -07:00
Eddie Hung 6bf73e3546 Cleanup abc9.cc 2019-06-27 15:15:56 -07:00
Bogdan Vukobratovic 3225bfb984 Add help for "-sat" option inside opt_rmdff. "opt" can pass "-sat" too 2019-06-27 22:06:23 +02:00
Bogdan Vukobratovic 35fa7b3057 Fix memory leak when one of multiple DFF cells is removed in opt_rmdff 
When there are multiple DFFs and one of them is removed, its reference lingers
inside bit2driver dict. While invoking handle_dff() function for other DFFs,
this broken reference is used isnside sat_import_cell() function.
 2019-06-27 22:02:12 +02:00
Eddie Hung 440f173aef Merge remote-tracking branch 'origin/master' into xaig 2019-06-27 11:54:34 -07:00
Eddie Hung 6c210e5813
Merge pull request #1143 from YosysHQ/clifford/fix1135 
Add "pmux2shiftx -norange"
 2019-06-27 11:48:48 -07:00
Eddie Hung 6c256b8cda Merge origin/master 2019-06-27 11:20:15 -07:00
Bogdan Vukobratovic 0f32cb4e0a Merge remote-tracking branch 'upstream/master' 2019-06-27 12:11:47 +02:00
Clifford Wolf 7c14678ec0 Add "pmux2shiftx -norange", fixes #1135 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-06-27 10:59:12 +02:00
Clifford Wolf 69d810e4a8 Fix handling of partial covers in muxcover, fixes #1132 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-06-27 09:42:58 +02:00
Eddie Hung c226af3f56 Fix spacing 2019-06-26 20:03:34 -07:00
Eddie Hung 26efd6f0a9 Support more than one port in the abc_scc_break attr 2019-06-26 19:57:54 -07:00
Clifford Wolf 0b7d648c6a Improve opt_clean handling of unused public wires 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-06-26 17:54:17 +02:00
Clifford Wolf 8e9ef891fe Do not clean up buffer cells with "keep" attribute, closes #1128 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-06-26 11:01:03 +02:00
Eddie Hung 5db96b8aec Missing muxpack.o in Makefile 2019-06-25 10:38:42 -07:00
Eddie Hung 6f36ec8ecf Merge remote-tracking branch 'origin/master' into xaig 2019-06-25 09:33:11 -07:00
Clifford Wolf add2d415fc
Merge pull request #1130 from YosysHQ/eddie/fix710 
memory_dff: walk through more than one mux for computing read enable
 2019-06-25 17:34:44 +02:00
Eddie Hung 42720ef6fe Fix spacing 2019-06-25 08:33:17 -07:00
Eddie Hung c4e4902098 Move only one consumer check outside of while loop 2019-06-25 08:29:55 -07:00
Eddie Hung d2fed0a7f1 nullptr check 2019-06-25 06:06:32 -07:00
Eddie Hung a19226c174 Fix for abc_scc_break is bus 2019-06-24 22:16:56 -07:00
Eddie Hung 5605002d8a More meaningful error message 2019-06-24 22:12:55 -07:00
Eddie Hung babadf5938 Do not use log_id as it strips \\, also fix scc for |wire| > 1 2019-06-24 22:04:22 -07:00
Eddie Hung 49a762ba46 Fix abc9's scc breaker, also break on abc_scc_break attr 2019-06-24 21:53:18 -07:00
Eddie Hung b7deaceadd Walk through as many muxes as exist for rd_en 2019-06-24 18:33:06 -07:00
Eddie Hung 4ddc0354c1 Merge remote-tracking branch 'origin/master' into eddie/muxpack 2019-06-22 14:40:55 -07:00
Eddie Hung 1abe93e48d Merge remote-tracking branch 'origin/master' into xaig 2019-06-21 17:43:29 -07:00
Eddie Hung ad296d77ab Do not rename non LUT cells in abc9 2019-06-21 17:18:04 -07:00
Eddie Hung e01bab6c64
Merge pull request #1108 from YosysHQ/clifford/fix1091 
Add support for partial matches to muxcover
 2019-06-21 17:13:41 -07:00
Eddie Hung 545cfbbe0d Cope with $reduce_or common in case 2019-06-21 12:31:14 -07:00
Eddie Hung 15535112b7 Fix spacing 2019-06-21 11:52:51 -07:00
Eddie Hung d89d663c92 Add doc 2019-06-21 11:52:28 -07:00
Eddie Hung 641b86d25f Fix up ExclusiveDatabase with @cliffordwolf's help 2019-06-21 11:45:31 -07:00
Eddie Hung 63eb5cace9 Merge branch 'master' into eddie/muxpack 2019-06-21 11:17:19 -07:00
Clifford Wolf ec979475e7 Replace "muxcover -freedecode" with "muxcover -dmux=cost" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-06-21 19:24:41 +02:00
Eddie Hung 6d74cf0d2b
Merge pull request #1085 from YosysHQ/eddie/shregmap_improve 
Improve shregmap to handle case where first flop is common to two chains
 2019-06-21 08:56:56 -07:00
Clifford Wolf c9949dba99
Merge pull request #1117 from bwidawsk/more-home 
Add a few more filename rewrites
 2019-06-21 10:13:51 +02:00
Clifford Wolf 9286b6f013 Add "muxcover -freedecode" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-06-21 10:02:10 +02:00
Eddie Hung 54f3237720 Fix gcc warning of potentially uninitialised 2019-06-20 22:10:43 -07:00
Clifford Wolf 891ea6512e Improvements in muxcover 
- Slightly under-estimate cost of decoder muxes
- Prefer larger muxes at tree root at same cost
- Don't double-count input cost for partial muxes
- Add debug log output
 2019-06-20 19:47:59 -07:00
Clifford Wolf 40188457d1 Add support for partial matches to muxcover, fixes #1091 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-06-20 19:47:59 -07:00
Eddie Hung 0e97e6a00d Fix simple_abc9/generate test with 1'bx at MSB 2019-06-20 19:41:27 -07:00
Eddie Hung e612dade12 Merge remote-tracking branch 'origin/master' into xaig 2019-06-20 19:00:36 -07:00
Eddie Hung 3f34779d64 Do not call "setundef -zero" in abc9 2019-06-20 17:38:04 -07:00
Eddie Hung e63324f5ef Actually, there might not be any harm in updating sigmap... 2019-06-20 17:03:05 -07:00
Eddie Hung 9c61fb0e0c Add comment as per @cliffordwolf 2019-06-20 16:57:54 -07:00
Ben Widawsky 8767ec3fbd Add a few more filename rewrites 
This now allows a full pipeline to work, something such as:
yosys -p "synth_ecp5 -json ~/work/fpga/prjtrellis/examples/ecp5_evn/blinky.v"

Otherwise, you will get something along the lines of:
ERROR: Can't open output file `~/work/fpga/prjtrellis/examples/ecp5_evn/blinky.v' for writing: No such file or directory

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
 2019-06-20 10:27:59 -07:00
Clifford Wolf 477e566e8d Fix typo, fixes #1095 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-06-20 15:34:52 +02:00
Clifford Wolf 06eb87bcb7 Improve shregmap help message, fixes #1113 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-06-20 15:23:55 +02:00
Clifford Wolf 2454ad99bf Refactor "opt_rmdff -sat" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-06-20 13:44:21 +02:00
Clifford Wolf 73bd1d59a7 Merge branch 'master' of https://github.com/bogdanvuk/yosys into clifford/ext1046 2019-06-20 13:04:04 +02:00
Clifford Wolf 11ec7b2aec Fix typo 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-06-20 12:23:07 +02:00
acw1251 0d888ee7ed Fixed the help summary line for a few commands 2019-06-19 15:27:04 -04:00
Eddie Hung 96ade54993 Fix bug in #1078, add entry to CHANGELOG 2019-06-19 09:51:11 -07:00
Clifford Wolf 3da5288ce0 Use input default values in hierarchy pass 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-06-19 11:49:20 +02:00
Eddie Hung d80678e581 Cleanup 2019-06-17 15:10:33 -07:00
Eddie Hung 3ebba74461 Merge branch 'xaig' into xaig_dff 2019-06-17 13:51:53 -07:00
Eddie Hung 4d6d593fe3 &scorr before &sweep, remove &retime as recommended 2019-06-17 13:32:08 -07:00
Eddie Hung a474fe937b Merge branch 'xaig' into xaig_dff 2019-06-17 13:20:19 -07:00
Eddie Hung 63fc879a5f Copy not move parameters/attributes 2019-06-17 13:19:45 -07:00
Eddie Hung 7dd3a7f161 Merge branch 'xaig' into xaig_dff 2019-06-17 12:58:41 -07:00
Eddie Hung b45d06d7a3 Fix leak removing cells during ABC integration; also preserve attr 2019-06-17 12:54:24 -07:00
Eddie Hung 5ce672d1c5 Merge remote-tracking branch 'origin/xaig' into xaig_dff 2019-06-17 12:14:55 -07:00
Eddie Hung 7250c57c5a Re-enable &dc2 2019-06-17 10:28:51 -07:00
Eddie Hung fb90d8c18c Cleanup 2019-06-16 09:34:26 -07:00
Eddie Hung 3ed95dae8d Cleanup 2019-06-15 22:48:16 -07:00
Eddie Hung 416312b9ed abc9 to recover_init by default 2019-06-15 22:44:45 -07:00
Eddie Hung 2309459605 Do not treat $__ABC_FF_ as a user cell 2019-06-15 19:36:55 -07:00
Eddie Hung cdfb634977 Cleanup 2019-06-15 18:18:56 -07:00
Eddie Hung c2f3f116d0 Use $__ABC_FF_ instead of $_FF_ 2019-06-15 18:16:14 -07:00
Eddie Hung a76c8a7ffd Fix initialisation of flops 2019-06-15 09:46:35 -07:00
Eddie Hung ac18a76beb Map to $_FF_ instead of $_DFF_P_ to prevent recursion issues 2019-06-15 09:34:48 -07:00
Eddie Hung da487c4f31 For now, short $_DFF_[NP]_ from ff_map.v at re-integration 2019-06-15 09:08:18 -07:00
Eddie Hung 2d85725604 Get rid of compiler warnings 2019-06-14 13:07:56 -07:00
Eddie Hung a632799d5b Update abc9 -D doc 2019-06-14 12:29:46 -07:00
Eddie Hung e391fc8e7b Enable "abc9 -D <num>" for timing-driven synthesis 2019-06-14 12:28:01 -07:00
Eddie Hung a48b5bfaa5 Further cleanup based on @daveshah1 2019-06-14 12:25:06 -07:00
Eddie Hung 751e640c1d Merge branch 'xaig' of github.com:YosysHQ/yosys into xaig 2019-06-14 10:29:16 -07:00
Eddie Hung a5425a2f7e Remove extra semicolon 2019-06-14 10:11:34 -07:00
David Shah 9566573054 ecp5: Add abc9 option 
Signed-off-by: David Shah <dave@ds0.me>
 2019-06-14 17:15:02 +01:00
Bogdan Vukobratovic 8451cbea89 Move netlist helper module to passes/opt for the time being 2019-06-14 12:14:02 +02:00
Bogdan Vukobratovic fe651922cb Merge remote-tracking branch 'upstream/master' 2019-06-14 12:06:57 +02:00
Bogdan Vukobratovic 53695e6729 Prepare for situation when port of the signal cannot be found 2019-06-14 11:39:24 +02:00
Bogdan Vukobratovic 291b36afeb Some cleanup, revert sat.cc 2019-06-14 11:35:45 +02:00
Bogdan Vukobratovic 8665f48879 Implement disconnection of constant register bits 2019-06-13 19:35:37 +02:00
Eddie Hung 2c40b66785 Rip out all non FPGA stuff from abc9 2019-06-12 16:53:12 -07:00
Eddie Hung f81a189fb8 Fix spelling 2019-06-12 16:52:09 -07:00
Eddie Hung 90dc4d82de Revert "For 'stat' do not count modules with abc_box_id" 
This reverts commit b89bb74452.
 2019-06-12 16:51:37 -07:00
Eddie Hung b3faf0246d Be more precise when connecting during ABC9 re-integration 2019-06-12 16:04:33 -07:00
Eddie Hung 2e7e73f483 Remove hacky wideports_split from abc9 2019-06-12 15:52:49 -07:00
Eddie Hung d9974b85e7 Fix compile errors when #if 1 for debug 2019-06-12 15:47:39 -07:00
Bogdan Vukobratovic d69989b8d2 Rename satgen_algo.h -> algo.h, code cleanup and refactoring 2019-06-12 19:35:05 +02:00
Eddie Hung 8bb67fa67c Do not call abc9 if no outputs 2019-06-12 10:18:44 -07:00
Eddie Hung 14e870d4c4 More write_xaiger cleanup 2019-06-12 10:00:57 -07:00
Eddie Hung b21d29598a Consistency 2019-06-12 09:40:51 -07:00
Eddie Hung b2c72f74f0 Merge branch 'xc7mux' into xaig 2019-06-12 09:14:27 -07:00
Eddie Hung afd620fd5f Typo: wire delay is -W argument 2019-06-12 09:13:53 -07:00
Eddie Hung 2cbcd6224c Revert "Merge remote-tracking branch 'origin/eddie/shregmap_improve' into xc7mux" 
This reverts commit a138381ac3, reversing
changes made to b77c5da769.
 2019-06-12 09:05:02 -07:00
Eddie Hung 882a83c383 Revert "Merge remote-tracking branch 'origin/eddie/muxpack' into xc7mux" 
This reverts commit eaee250a6e, reversing
changes made to 935df3569b.
 2019-06-12 09:04:31 -07:00
Eddie Hung 86efe9a616 Revert "Merge remote-tracking branch 'origin/eddie/muxpack' into xc7mux" 
This reverts commit 2223ca91b0, reversing
changes made to eaee250a6e.
 2019-06-12 09:01:15 -07:00
Eddie Hung 1e838a8913 Retry "Add "-W' wire delay arg to abc9, use from synth_xilinx" 2019-06-12 08:49:15 -07:00
Eddie Hung 4c9fde87d1 Revert "Add "-W' wire delay arg to abc9, use from synth_xilinx" 
This reverts commit 2dffa4685b.
 2019-06-12 08:48:45 -07:00
Eddie Hung 2dffa4685b Add "-W' wire delay arg to abc9, use from synth_xilinx 2019-06-11 17:10:47 -07:00
Eddie Hung 6cdea93724 Revert "Try way that doesn't involve creating a new wire" 
This reverts commit 2f427acc9e.
 2019-06-11 16:05:42 -07:00
Eddie Hung d26646051c Revert "Merge remote-tracking branch 'origin/eddie/shregmap_improve' into xc7mux" 
This reverts commit 5174082208, reversing
changes made to 54379f9872.
 2019-06-11 16:05:27 -07:00
Eddie Hung 5174082208 Merge remote-tracking branch 'origin/eddie/shregmap_improve' into xc7mux 2019-06-11 15:48:41 -07:00
Eddie Hung 2f427acc9e Try way that doesn't involve creating a new wire 2019-06-11 15:48:20 -07:00
Bogdan Vukobratovic 9892df17ef Generate satgen instance instead of calling sat pass 2019-06-11 11:47:13 +02:00
Eddie Hung a138381ac3 Merge remote-tracking branch 'origin/eddie/shregmap_improve' into xc7mux 2019-06-10 16:21:43 -07:00
Eddie Hung f19aa8d989 If d_bit already in sigbit_chain_next, create extra wire 2019-06-10 16:16:40 -07:00
Eddie Hung a1d4ae78a0 Revert "Rename shregmap -tech xilinx -> xilinx_dynamic" 
This reverts commit 94a5f4e609.
 2019-06-10 14:34:43 -07:00
Eddie Hung 7d27e1e431 Revert "shregmap -tech xilinx_dynamic to work -params and -enpol" 
This reverts commit 45d1bdf83a.
 2019-06-10 14:34:16 -07:00
Eddie Hung 3579d68193 Revert "Refactor to ShregmapTechXilinx7Static" 
This reverts commit e1e37db860.
 2019-06-10 14:34:15 -07:00
Eddie Hung b6a39351f4 Revert "Add -tech xilinx_static" 
This reverts commit dfe9d95579.
 2019-06-10 14:34:14 -07:00
Eddie Hung e1dbeb3004 Revert "Continue support for ShregmapTechXilinx7Static" 
This reverts commit 72eda94a66.
 2019-06-10 14:34:14 -07:00
Eddie Hung 9d8563178e Revert "shregmap -tech xilinx_static to handle INIT" 
This reverts commit 935df3569b.
 2019-06-10 14:34:12 -07:00
Eddie Hung 5b999ae68d Elaborate muxpack doc 2019-06-10 10:32:19 -07:00
Eddie Hung 1dd7e23a20 Merge remote-tracking branch 'origin/master' into eddie/muxpack 2019-06-10 10:28:40 -07:00
Eddie Hung 5a46a0b385 Fine tune aigerparse 2019-06-07 16:57:32 -07:00
Eddie Hung f705f6a0b5 Comment O(N) -> O(N^2) 2019-06-07 15:39:12 -07:00
Eddie Hung ba52d9b471 Extend ExclusiveDatabase to query SigSpec-s (for $pmux) 2019-06-07 15:34:16 -07:00
Eddie Hung 9b408838f1 Add ExclusiveDatabase to check exclusive $eq/$logic_not cell results 2019-06-07 14:18:17 -07:00
Eddie Hung 887df8914c Resolve @cliffordwolf comment on redundant check 2019-06-07 11:37:52 -07:00
Eddie Hung 5ab59cd59e Resolve @cliffordwolf comment on sigmap 2019-06-07 11:36:19 -07:00
Eddie Hung 30abdaf3b2 Allow muxcover costs to be changed 2019-06-07 08:34:11 -07:00
Eddie Hung fe4394fb9a Allow muxcover costs to be changed 2019-06-07 08:30:39 -07:00
Eddie Hung 2223ca91b0 Merge remote-tracking branch 'origin/eddie/muxpack' into xc7mux 2019-06-06 14:22:10 -07:00
Eddie Hung 5c277c6325 Fix and test for balanced case 2019-06-06 14:21:34 -07:00
Eddie Hung eaee250a6e Merge remote-tracking branch 'origin/eddie/muxpack' into xc7mux 2019-06-06 14:06:59 -07:00
Eddie Hung ccdf989025 Support cascading $pmux.A with $mux.A and $mux.B 2019-06-06 13:51:22 -07:00
Eddie Hung dc7b8c4b94 More cleanup 2019-06-06 12:56:34 -07:00
Eddie Hung 978fda94f6 Fix spacing 2019-06-06 12:46:42 -07:00
Eddie Hung d2172c6846 Non chain user check using next_sig 2019-06-06 12:44:50 -07:00
Eddie Hung 83450a9489 Move muxpack from passes/techmap to passes/opt 2019-06-06 12:15:13 -07:00
Eddie Hung 3dd0682f29 Update doc 2019-06-06 12:11:59 -07:00
Eddie Hung 3e76e3a6fa Add tests, fix for != 2019-06-06 11:54:38 -07:00
Eddie Hung 543dd11c7e Missing file 2019-06-06 11:03:45 -07:00
Eddie Hung 7bd1c664a6 Initial adaptation of muxpack from shregmap 2019-06-06 10:51:02 -07:00
Clifford Wolf e4e1cd6930
Merge pull request #1071 from YosysHQ/eddie/fix_1070 
Fix typo in opt_rmdff causing register to be incorrectly removed
 2019-06-06 06:50:12 +02:00
Clifford Wolf 50e2dce5e7
Merge pull request #1072 from YosysHQ/eddie/fix_1069 
Error out if no top module given before 'sim'
 2019-06-06 06:49:07 +02:00
Eddie Hung fd8ef128bf Missing doc for -tech xilinx in shregmap 2019-06-05 14:21:44 -07:00
Eddie Hung dd134914cc Error out if no top module given before 'sim' 2019-06-05 14:16:24 -07:00
Eddie Hung feb2ddb52b Fix typo in opt_rmdff 2019-06-05 14:08:14 -07:00
Eddie Hung 935df3569b shregmap -tech xilinx_static to handle INIT 2019-06-05 12:55:59 -07:00
Eddie Hung 72eda94a66 Continue support for ShregmapTechXilinx7Static 2019-06-05 12:33:55 -07:00
Eddie Hung dfe9d95579 Add -tech xilinx_static 2019-06-05 11:14:14 -07:00
Eddie Hung e1e37db860 Refactor to ShregmapTechXilinx7Static 2019-06-05 11:08:08 -07:00
Eddie Hung 45d1bdf83a shregmap -tech xilinx_dynamic to work -params and -enpol 2019-06-05 10:21:57 -07:00
Eddie Hung a3a80b755c
Merge pull request #1067 from YosysHQ/clifford/fix1065 
Suppress driver-driver conflict warning for unknown cell types
 2019-06-05 09:59:05 -07:00
Eddie Hung bcc0a5d136 Merge remote-tracking branch 'origin/master' into xc7mux 2019-06-05 09:56:57 -07:00
Eddie Hung b5aff1de04 Merge remote-tracking branch 'origin/clifford/fix1065' into xc7mux 2019-06-05 09:56:51 -07:00
Clifford Wolf b33176dafb Major rewrite of wire selection in setundef -init 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-06-05 10:26:48 +02:00
Clifford Wolf 6cc60ffd67 Indent fix 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-06-05 09:53:06 +02:00
Clifford Wolf 00d32eb73d
Merge pull request #999 from jakobwenzel/setundefInitFix 
initialize more registers in setundef -init
 2019-06-05 09:50:15 +02:00
Clifford Wolf 4190d7c094 Fix typo in fmcombine log message, fixes #1063 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-06-05 09:26:44 +02:00
Clifford Wolf 8a6f9977f6 Suppress driver-driver conflict warning for unknown cell types, fixes #1065 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-06-05 09:14:12 +02:00
Eddie Hung 94a5f4e609 Rename shregmap -tech xilinx -> xilinx_dynamic 2019-06-04 14:34:36 -07:00
Eddie Hung f81a0ed92e Merge remote-tracking branch 'origin/master' into xc7mux 2019-06-03 23:07:08 -07:00
Eddie Hung 295bd8d0bf Remove dupe 2019-06-03 12:32:20 -07:00
Eddie Hung eb08e71bd1 Merge branch 'xaig' into xc7mux 2019-05-31 13:03:03 -07:00
Eddie Hung a379234f56 Throw out unused code inherited from abc 2019-05-31 12:50:11 -07:00
Clifford Wolf 90ec2cda42 Fix "tee" handling of log_streams 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-05-31 09:28:51 +02:00
Eddie Hung 4a6b9af227 Fix spelling 2019-05-30 15:50:47 -07:00
Eddie Hung a44fe3a632 Revert "Re-enable &dc2" 
This reverts commit 8c58c728a7.
 2019-05-30 11:41:50 -07:00
Eddie Hung 0800846e73 Do not double count LUT1s 2019-05-30 11:32:14 -07:00
Eddie Hung 8c58c728a7 Re-enable &dc2 2019-05-30 00:42:41 -07:00
Eddie Hung 2560f92f29 Reduce -W to 160 2019-05-29 23:01:46 -07:00
Eddie Hung 854557814e Erase all boxes before stitching 2019-05-29 19:17:36 -07:00
Eddie Hung b955344ecd Call &if with -W 250 2019-05-29 16:34:52 -07:00
Eddie Hung ecaa7856e9 Add some debug to abc9 2019-05-29 15:21:41 -07:00
Clifford Wolf 349c47250a
Merge pull request #1049 from YosysHQ/clifford/fix1047 
Do not use shiftmul peepopt pattern when mul result is truncated
 2019-05-28 19:02:26 +02:00
Eddie Hung cdedf51c32 From master 2019-05-28 09:37:50 -07:00
Eddie Hung 914074a07c Update from master 2019-05-28 09:35:45 -07:00
Eddie Hung ba9513b325 Merge remote-tracking branch 'origin/master' into xc7mux 2019-05-28 09:30:53 -07:00
Eddie Hung 4a76b425cc Misspell 2019-05-28 08:44:59 -07:00
Clifford Wolf cb285e4b87 Do not use shiftmul peepopt pattern when mul result is truncated, fixes #1047 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-05-28 17:17:56 +02:00
Clifford Wolf ba2185ead8 Refactor hierarchy wand/wor handling 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-05-28 16:43:25 +02:00
Bogdan Vukobratovic 29a78267d7 Fix the regression 2019-05-28 15:45:04 +02:00
Bogdan Vukobratovic 9a468f81c4 Optimizing DFFs whose initial value prevents their value from changing 
This is a proof of concept implementation that invokes SAT solver via Pass::call
method.
 2019-05-28 08:48:21 +02:00
Eddie Hung 89bd6b8504 If driver not found, use LUT2 2019-05-27 23:12:21 -07:00
Eddie Hung 4df37c77fd Disconnect all ABC boxes too 2019-05-27 19:40:27 -07:00
Eddie Hung 75bd41eaeb Parse without wideports 2019-05-27 12:22:05 -07:00
Eddie Hung bf3b8d5e45 Remove mapped_mod when done 2019-05-27 12:19:21 -07:00
Eddie Hung 234156c01a Instantiate cell type (from sym file) otherwise 'clean' warnings 2019-05-27 12:16:10 -07:00
Eddie Hung 03b289a851 Add 'cinput' and 'coutput' to symbols file for boxes 2019-05-27 11:38:52 -07:00
Stefan Biereigel 816082d5a1
Merge branch 'master' into wandwor 2019-05-27 19:07:46 +02:00
Stefan Biereigel ed625a3102 move wand/wor resolution into hierarchy pass 2019-05-27 18:00:22 +02:00
Clifford Wolf 2a9c68e2d6
Merge pull request #1026 from YosysHQ/clifford/fix1023 
Keep zero-width wires in opt_clean if and only if they are ports
 2019-05-27 13:24:19 +02:00
Eddie Hung 3981eba999 ABC9 to call &sweep 2019-05-26 11:31:35 -07:00
Eddie Hung 086b6560b4 Typo 2019-05-26 03:17:20 -07:00
Eddie Hung 823153e418 Combine ABC_COMMAND_LUT 2019-05-26 02:47:06 -07:00
Eddie Hung 32a4c10c0d Fix "a" extension 2019-05-26 02:44:36 -07:00
Eddie Hung d4fb6cac7c Revert enable check 2019-05-25 12:55:57 -07:00
Eddie Hung 822d0b7789 opt_rmdff to optimise even in presence of enable signal, even removing 2019-05-24 18:30:51 -07:00
Eddie Hung 0d66103cbb Add comments 2019-05-24 16:33:10 -07:00
Eddie Hung 357b1de6bc Resolve @cliffordwolf review, set even if !has_init 2019-05-24 16:15:22 -07:00
Eddie Hung 6ad09bfcea Add &fraig and &mfs back 2019-05-24 15:10:18 -07:00
Eddie Hung 68359bcd6f Merge remote-tracking branch 'origin/eddie/opt_rmdff' into xc7mux 2019-05-23 13:37:53 -07:00
Eddie Hung 5ac7e38d0a Fix spacing 2019-05-23 12:58:30 -07:00
Eddie Hung 50ed34a6d0 opt_rmdff to work on $dffe and $_DFFE_* 2019-05-23 11:26:18 -07:00
Clifford Wolf e3f9ccf56d Keep zero-width wires in opt_clean if and only if they are ports, fixes #1023 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-05-22 13:57:36 +02:00
Eddie Hung fb09c6219b Merge remote-tracking branch 'origin/master' into xc7mux 2019-05-21 14:21:00 -07:00
Clifford Wolf c4b8575f43 Add "wreduce -keepdc", fixes #1016 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-05-20 15:36:13 +02:00
Clifford Wolf a21a84b3b4 Improvements in opt_clean 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-05-15 16:01:28 +02:00
Clifford Wolf f67ec1b235 Do not leak file descriptors in cover.cc 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-05-15 13:51:02 +02:00
Henner Zeller 5e443a5d0d Fix two instances of integer-assignment to string. 
o In cover.cc, the int-result of mkstemps() was assigned to a string
  and silently interpreted as a single-character filename with a funny
  value. Fix with the intent: assign the filename.
o in libparse.cc, an int was assigned to a string, but depending on
  visible constructors, this is ambiguous. Explicitly cast this to
  a char.
 2019-05-14 22:01:15 -07:00
whitequark c8c1df23a0 bugpoint: check for -script option. 
Fixes #925.
 2019-05-14 10:48:06 +00:00
Clifford Wolf 8166a142dd Fix handling of glob_abort_cnt in opt_muxtree, fixes #1002 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-05-12 13:51:12 +02:00
Clifford Wolf faf00586d8
Merge pull request #1003 from makaimann/zinit-all 
Zinit option '-singleton' -> '-all'
 2019-05-11 13:56:51 +02:00
Clifford Wolf b66b657b6b Add "fmcombine -initeq -anyeq" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-05-11 09:28:55 +02:00
Clifford Wolf 04ef222cfb Add "stat -tech xilinx" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-05-11 09:24:52 +02:00
Makai Mann 2f5cfa014b Zinit option '-singleton' -> '-all' 2019-05-10 10:23:14 -07:00
Jakob Wenzel f06cb75b93 initialize more registers in setundef -init 2019-05-09 12:47:16 +02:00
Clifford Wolf 3870e7cf29
Merge pull request #991 from kristofferkoch/gcc9-warnings 
Fix all warnings that occurred when compiling with gcc9
 2019-05-08 11:25:22 +02:00
Kristoffer Ellersgaard Koch 30c762d3a1 Fix all warnings that occurred when compiling with gcc9 2019-05-08 10:27:14 +02:00
Clifford Wolf a76189e7ad More opt_clean cleanups 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-05-07 14:41:58 +02:00
Clifford Wolf 752553d8e9
Merge pull request #946 from YosysHQ/clifford/specify 
Add specify parser
 2019-05-06 20:57:15 +02:00
Clifford Wolf 1706798f4e
Merge pull request #975 from YosysHQ/clifford/fix968 
Re-enable "final loop assignment" feature and fix opt_clean warnings
 2019-05-06 20:53:38 +02:00
Clifford Wolf 7bab7b3d49
Merge pull request #871 from YosysHQ/verific_import 
Improve verific -chparam and add hierarchy -chparam
 2019-05-06 20:51:59 +02:00
Clifford Wolf d187be39d6 Merge branch 'master' of github.com:YosysHQ/yosys into clifford/fix968 2019-05-06 15:41:13 +02:00
Clifford Wolf b37c31e2cb Bugfix in peepopt_shiftmul.pmg 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-05-06 15:34:19 +02:00
Clifford Wolf c0782d8390
Merge pull request #989 from YosysHQ/dave/abc_name_improve 
ABC name recovery fixes
 2019-05-06 13:57:35 +02:00
Clifford Wolf f02e22a35a Fix bug in "expose -input" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-05-06 13:30:55 +02:00
Clifford Wolf ba6ce21a74 Cleanups in opt_clean 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-05-06 12:45:22 +02:00
Clifford Wolf c7f2e93024 Merge branch 'master' of github.com:YosysHQ/yosys into clifford/specify 2019-05-06 11:46:10 +02:00
David Shah a84256aa36 abc: Fix handling of postfixed names (e.g. for retiming) 
Signed-off-by: David Shah <dave@ds0.me>
 2019-05-04 17:23:44 +01:00
David Shah 5ce9113eda abc: Improve name recovery 
Signed-off-by: David Shah <dave@ds0.me>
 2019-05-04 16:53:25 +01:00
Clifford Wolf a01386c0e4 Improve opt_clean handling of unused wires 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-05-04 09:47:16 +02:00
Eddie Hung d9c4644e88 Merge remote-tracking branch 'origin/master' into clifford/specify 2019-05-03 15:05:57 -07:00
Clifford Wolf ec39cfd0ad Add "hierarchy -chparam" support for non-verific top modules 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-05-03 22:03:43 +02:00
Eddie Hung eb21bf3651 log_warning_noprefix -> log_warning as per review 2019-05-03 20:53:25 +02:00
Eddie Hung a27b42e975 WIP -chparam support for hierarchy when verific 2019-05-03 20:53:25 +02:00
Clifford Wolf 373b236108
Merge pull request #969 from YosysHQ/clifford/pmgenstuff 
Improve pmgen, Add "peepopt" pass with shift-mul pattern
 2019-05-03 20:39:50 +02:00
Clifford Wolf f170fb6383
Merge pull request #984 from YosysHQ/eddie/fix_982 
dffinit to do nothing when (* init *) value is 1'bx
 2019-05-03 20:34:32 +02:00
Eddie Hung e08df0c739 If init is 1'bx, do not add to dict as per @cliffordwolf 2019-05-03 08:06:16 -07:00
Eddie Hung fc349de033 Revert "dffinit -noreinit to silently continue when init value is 1'bx" 
This reverts commit aa081f83c7.
 2019-05-03 08:05:37 -07:00
Clifford Wolf 42190207b4 Improve opt_expr and opt_clean handling of (partially) undriven and/or unused wires, fixes #981 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-05-03 14:25:01 +02:00
Clifford Wolf 5c2c0b4bb2 Further improve unused-detection for opt_clean driver-driver conflict warning 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-05-03 09:22:26 +02:00
Clifford Wolf f12e1155f1 Improve unused-detection for opt_clean driver-driver conflict warning 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-05-03 09:12:10 +02:00
Clifford Wolf 2b29aa5c86 Update pmgen documentation 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-05-03 08:35:45 +02:00
Clifford Wolf e8c5afcb84 Fix typo 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-05-03 08:25:30 +02:00
Eddie Hung aa081f83c7 dffinit -noreinit to silently continue when init value is 1'bx 2019-05-02 17:40:39 -07:00
Eddie Hung 8829cba901 Merge remote-tracking branch 'origin/clifford/pmgenstuff' into xc7mux 2019-05-02 11:25:34 -07:00
Eddie Hung 5cd19b52da Merge remote-tracking branch 'origin/master' into xc7mux 2019-05-02 10:44:59 -07:00
Eddie Hung f86d153cef Merge branch 'master' of github.com:YosysHQ/yosys 2019-05-01 16:26:43 -07:00
Clifford Wolf 521663f09e Add missing enable_undef to "sat -tempinduct-def", fixes #883 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-05-02 00:03:31 +02:00
Clifford Wolf 93b7fd7744 Fix floating point exception in qwp, fixes #923 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-05-01 15:06:46 +02:00
Clifford Wolf a30b99e66e Silently resolve completely unused cell-vs-const driver-driver conflicts 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-05-01 09:29:34 +02:00
Clifford Wolf 32ff37bb5a Fix segfault in wreduce 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-30 22:20:45 +02:00
Clifford Wolf a27eeff573
Merge pull request #966 from YosysHQ/clifford/fix956 
Drive dangling wires with init attr with their init value
 2019-04-30 18:08:41 +02:00
Clifford Wolf 9d117eba9d Add handling of init attributes in "opt_expr -undriven" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-30 14:46:12 +02:00
Clifford Wolf b515fd2d25 Add peepopt_muldiv, fixes #930 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-30 11:25:15 +02:00
Clifford Wolf 4306bebe58 pmgen progress 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-30 10:51:51 +02:00
Clifford Wolf bb4f3642de Some pmgen reorg, rename peepopt.pmg to peepopt_shiftmul.pmg 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-30 08:04:22 +02:00
Clifford Wolf 58238da133 Progress in shiftmul peepopt pattern 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-30 07:59:39 +02:00
Clifford Wolf ea547bcaa3 Add "peepopt" skeleton 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-29 13:38:56 +02:00
Clifford Wolf 9f792c599d Add pmgen support for multiple patterns in one matcher 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-29 13:02:05 +02:00
Clifford Wolf 32881a989c Support multiple pmg files (right now just concatenated together) 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-29 12:09:02 +02:00
Clifford Wolf 754b1ee4b3 Drive dangling wires with init attr with their init value, fixes #956 2019-04-29 08:44:53 +02:00
Eddie Hung acafcdc94d Copy with 1'bx padding in $shiftx 2019-04-28 13:04:34 -07:00
Eddie Hung dcc8a13e48 Revert "Merge branch 'eddie/split_shiftx' into xc7mux" 
This reverts commit 3042d58330, reversing
changes made to feff976454.
 2019-04-26 15:32:02 -07:00
Eddie Hung 159e7cc298 Add -undef option to equiv_opt, passed to equiv_induct 2019-04-26 11:16:48 -07:00
Eddie Hung 4473fd1502 Add -undef option to equiv_opt, passed to equiv_induct 2019-04-26 11:14:33 -07:00
Eddie Hung 976d8030dc Actually use pm.st.shiftxB 2019-04-25 19:59:33 -07:00
Eddie Hung fb4348f840 Fix for when B_WIDTH has trailing zeroes 2019-04-25 19:38:19 -07:00
Eddie Hung 880652283c Merge remote-tracking branch 'origin/eddie/split_shiftx' into xc7mux 2019-04-25 18:52:20 -07:00
Eddie Hung ece2c49e92 In order to indicate a failed pattern, blacklist? 2019-04-25 18:39:13 -07:00
Eddie Hung af3c374a35 Elaborate on help message 2019-04-25 17:35:39 -07:00
Eddie Hung 3042d58330 Merge branch 'eddie/split_shiftx' into xc7mux 2019-04-25 17:31:27 -07:00
Eddie Hung ccd0729456 Add split_shiftx command 2019-04-25 17:23:59 -07:00
Eddie Hung 8d00b9ef7e Make pmgen support files more generic 2019-04-25 17:23:46 -07:00
Eddie Hung 408161ea3a
Misspelling 2019-04-25 16:46:13 -07:00
Eddie Hung d9c915042a Move clean from aigerparse to abc9 2019-04-23 13:42:35 -07:00
Clifford Wolf 71c38d9de5 Add $specrule cells for $setup/$hold/$skew specify rules 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-23 21:36:59 +02:00
Clifford Wolf 634482380c Preserve $specify[23] cells 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-23 21:36:59 +02:00
Clifford Wolf c84cdc711c Remove some left-over log_dump() 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-23 17:55:41 +02:00
Eddie Hung 4df4a97ffa Merge branch 'xaig' of github.com:YosysHQ/yosys into xaig 2019-04-22 18:20:39 -07:00
Eddie Hung 0bd2bfa737 Merge remote-tracking branch 'origin/master' into xaig 2019-04-22 18:15:28 -07:00
Eddie Hung 5f30a8795d Tidy up 2019-04-22 17:47:05 -07:00
Eddie Hung d9daf09cf3
Merge pull request #914 from YosysHQ/xc7srl 
synth_xilinx to now infer SRL16E/SRLC32E
 2019-04-22 13:31:30 -07:00
Eddie Hung 4cfef7897f Merge branch 'xaig' into xc7mux 2019-04-22 11:58:59 -07:00
Eddie Hung 4486a98fd5 Merge remote-tracking branch 'origin/xc7srl' into xc7mux 2019-04-22 11:45:49 -07:00
Eddie Hung 4883391b63 Merge remote-tracking branch 'origin/master' into xaig 2019-04-22 11:19:52 -07:00
Clifford Wolf 8ed4a53d99
Merge pull request #951 from YosysHQ/clifford/logdebug 
Add log_debug() framework
 2019-04-22 20:09:51 +02:00
Clifford Wolf 1d538ff1ec
Merge pull request #949 from YosysHQ/clifford/pmux2shimprove 
Add full_pmux feature to pmux2shiftx
 2019-04-22 20:01:43 +02:00
Eddie Hung e300b1922c Merge remote-tracking branch 'origin/master' into xc7srl 2019-04-22 10:36:27 -07:00
Clifford Wolf e158ea2097 Add log_debug() framework 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-22 17:25:52 +02:00
whitequark aeeefc32d8 attrmap: extend -remove to allow removing attributes with any value. 
Currently, `-remove foo` would only remove an attribute `foo = ""`,
which doesn't work on an attribute like `src` that may have any
value. Extend `-remove` to handle both cases. `-remove foo=""` has
the old behavior, and `-remove foo` will remove the attribute with
whatever value it may have, which is still compatible with the old
behavior.
 2019-04-22 14:18:15 +00:00
Clifford Wolf 0f0ada13f4 Add full_pmux feature to pmux2shiftx 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-22 15:26:20 +02:00
Clifford Wolf 99d5435650
Merge pull request #905 from christian-krieg/feature/python_bindings 
Feature/python bindings
 2019-04-22 14:47:52 +02:00
Clifford Wolf a98b171814
Merge pull request #944 from YosysHQ/clifford/pmux2shiftx 
Add pmux2shiftx command
 2019-04-22 08:39:37 +02:00
Eddie Hung d06d4f35c3 Merge remote-tracking branch 'origin/clifford/libwb' into xaig 2019-04-21 18:10:46 -07:00
Clifford Wolf 7b35d57592 Disable blackbox detection in techmap files 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-22 02:07:36 +02:00
Eddie Hung d99422411f Use new pmux2shiftx from #944, remove my old attempt 2019-04-21 14:16:34 -07:00
Eddie Hung 98781acf84 Merge remote-tracking branch 'origin/clifford/pmux2shiftx' into xc7srl 2019-04-20 17:24:33 -07:00
Eddie Hung 9dc11cd842 Merge remote-tracking branch 'origin/master' into xc7srl 2019-04-20 17:24:06 -07:00
Eddie Hung caec7f9d2c Merge remote-tracking branch 'origin/master' into xaig 2019-04-20 12:23:49 -07:00
Clifford Wolf f84a84e3f1
Merge pull request #943 from YosysHQ/clifford/whitebox 
[WIP] Add "whitebox" attribute, add "read_verilog -wb"
 2019-04-20 20:51:54 +02:00
Eddie Hung b25254020c Merge remote-tracking branch 'origin/pmux2shiftx' into xc7srl 2019-04-20 10:44:01 -07:00
Eddie Hung 13ad19482f Merge remote-tracking branch 'origin' into xc7srl 2019-04-20 10:41:43 -07:00
Clifford Wolf fc23af1707 Auto-initialize OnehotDatabase on-demand in pmux2shiftx.cc 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-20 18:13:37 +02:00