whitequark
c38ea9ae65
equiv_opt: new command, for verifying optimization passes.
2018-12-07 17:20:34 +00:00
whitequark
7ec740b7ad
opt_lut: leave intact LUTs with cascade feeding module outputs.
2018-12-07 17:13:52 +00:00
Clifford Wolf
7d1088afc4
Add missing .gitignore
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-12-06 07:29:37 +01:00
whitequark
9ef078848a
gate2lut: new techlib, for converting Yosys gates to FPGA LUTs.
2018-12-05 17:13:27 +00:00
whitequark
45cb6200af
opt_lut: add -dlogic, to avoid disturbing logic such as carry chains.
2018-12-05 16:30:37 +00:00
whitequark
9e072ec21f
opt_lut: new pass, to combine LUTs for tighter packing.
2018-12-05 16:30:37 +00:00
Clifford Wolf
6cd5b8b76b
Merge pull request #679 from udif/pr_syntax_error
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More meaningful SystemVerilog/Verilog parser error messages
2018-10-25 13:18:59 +02:00
Udi Finkelstein
536ae16c3a
Rename the generic "Syntax error" message from the Verilog/SystemVerilog parser into unique,
...
meaningful info on the error.
Also add 13 compilation examples that triggers each of these messages.
2018-10-25 02:37:56 +03:00
Ruben Undheim
397dfccb30
Support for SystemVerilog interfaces as a port in the top level module + test case
2018-10-20 11:58:25 +02:00
Ruben Undheim
d5aac2650f
Basic test for checking correct synthesis of SystemVerilog interfaces
2018-10-18 22:40:53 +02:00
Ruben Undheim
458a94059e
Support for 'modports' for System Verilog interfaces
2018-10-12 21:11:48 +02:00
Ruben Undheim
75009ada3c
Synthesis support for SystemVerilog interfaces
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This time doing the changes mostly in AST before RTLIL generation
2018-10-12 21:11:36 +02:00
Clifford Wolf
3d27c1cc80
Merge pull request #513 from udif/pr_reg_wire_error
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Add error checking for reg/wire/logic misuse - PR now passes 'make test' (plus a new test)
2018-08-15 13:35:41 +02:00
Udi Finkelstein
106af19b69
Fixed typo (sikp -> skip)
2018-06-05 22:41:27 +03:00
Udi Finkelstein
73d426bc87
Modified errors into warnings
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No longer false warnings for memories and assertions
2018-06-05 18:03:22 +03:00
Udi Finkelstein
80d9d15f1c
reg_wire_error test needs the -sv flag so it is run via a script so it had to be moved out of the tests/simple dir that only runs Verilog files
2018-06-05 18:00:06 +03:00
Johnny Sorocil
0295213bec
autotest.sh: Change from /bin/bash to /usr/bin/env bash
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This enables running tests on Unix systems which are not shipped with
bash installed in /bin/bash (eg *BSDs and Solaris).
2018-05-06 15:26:23 +02:00
Clifford Wolf
5e49ee5c2d
Fix tests/simple/specify.v
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-03-27 14:34:00 +02:00
Udi Finkelstein
6378e2cd46
First draft of Verilog parser support for specify blocks and parameters.
...
The only functionality of this code at the moment is to accept correct specify syntax and ignore it.
No part of the specify block is added to the AST
2018-03-27 14:34:00 +02:00
Udi Finkelstein
2b9c75f8e3
This PR should be the base for discussion, do not merge it yet!
...
It correctly detects reg/wire mix and incorrect use on blocking,nonblocking assignments within blocks and assign statements.
What it DOES'T do:
Detect registers connected to output ports of instances.
Where it FAILS:
memorty nonblocking assignments causes spurious (I assume??) errors on yosys-generated "_ADDR", "_DATA", "EN" signals.
You can test it with tests/simple/reg_wire_error.v (look inside for the comments to enable/disable specific lines)
2018-03-11 23:09:34 +02:00
Clifford Wolf
25e33d7ab8
Major redesign of Verific SVA importer
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-02-27 20:33:15 +01:00
Clifford Wolf
6d12c83d36
Add support for SVA throughout via Verific
2018-02-21 13:09:47 +01:00
Clifford Wolf
5c6247dfa6
Add support for SVA sequence concatenation ranges via verific
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-02-18 16:35:06 +01:00
Clifford Wolf
9d963cd29c
Add support for SVA until statements via Verific
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-02-18 14:57:52 +01:00
Clifford Wolf
bc8ab3ab44
Fix verific PRIM_SVA_AT handling in properties with PRIM_SVA_DISABLE_IFF
2018-02-15 15:26:37 +01:00
Clifford Wolf
baddb017fe
Remove PSL example from tests/sva/
2017-10-20 13:16:24 +02:00
Clifford Wolf
dbfd8460a9
Allow $size and $bits in verilog mode, actually check test case
2017-09-29 11:56:43 +02:00
Udi Finkelstein
e951ac0dfb
$size() now works correctly for all cases!
...
It seems the issues was that AST_MULTIRANGE is converted into a multirange_dimensions[] array on the AST_MEMORY node directly.
2017-09-26 20:34:24 +03:00
Udi Finkelstein
6ddc6a7af4
$size() seems to work now with or without the optional parameter.
...
Multidimensional arrays still don't work. I suspect the problem is that the array is flattened into a 1D array before $size() is evaluated.
2017-09-26 19:18:25 +03:00
Udi Finkelstein
2dea42e903
Added $bits() for memories as well.
2017-09-26 09:11:25 +03:00
Udi Finkelstein
17f8b41605
$size() now works with memories as well!
2017-09-26 08:36:45 +03:00
Udi Finkelstein
64eb8f29ad
Add $size() function. At the moment it works only on expressions, not on memories.
2017-09-26 06:25:42 +03:00
Clifford Wolf
4cf890dac1
Add simple VHDL+PSL example
2017-07-28 17:39:43 +02:00
Clifford Wolf
c1cfca8f54
Improve Verific SVA importer
2017-07-27 14:05:09 +02:00
Clifford Wolf
877ff1f75e
Add counter.sv SVA test
2017-07-27 12:37:16 +02:00
Clifford Wolf
b24f737759
Improve SVA tests, add Makefile and scripts
2017-07-27 11:42:05 +02:00
Clifford Wolf
84f15260b5
Add more SVA test cases for future Verific work
2017-07-22 16:35:46 +02:00
Clifford Wolf
024ba310ec
Add some simple SVA test cases for future Verific work
2017-07-22 12:31:08 +02:00
Larry Doolittle
2021ddecb3
Squelch trailing whitespace
2017-04-12 15:11:09 +02:00
Clifford Wolf
080004b19a
Fixed typo in tests/simple/arraycells.v
2017-01-04 12:39:01 +01:00
Clifford Wolf
5c96982522
Build hotfix in tests/unit/Makefile
2016-12-11 10:58:49 +01:00
rodrigosiqueira
b932e2355d
Improved unit test structure
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Signed-off-by: rodrigosiqueira <rodrigosiqueiramelo@gmail.com>
Signed-off-by: chaws <18oliveira.charles@gmail.com>
* Merged run-all-unitest inside unit-test target
* Fixed Makefile dependencies
* Updated documentation about unit test
2016-12-10 18:21:56 -02:00
rodrigosiqueira
e0152319f5
Added required structure to implement unit tests
...
Added modifications inside the main Makefile to refers the unit test Makefile.
Added separated Makefile only for compiling unit tests.
Added simple example of unit test.
Signed-off-by: Charles Oliveira <18oliveira.charles@gmail.com>
Signed-off-by: Pablo Alejandro <pabloabur@usp.br>
Signed-off-by: Rodrigo Siqueira <siqueira@ime.usp.br>
2016-12-04 11:34:27 -02:00
Clifford Wolf
70d7a02cae
Added support for hierarchical defparams
2016-11-15 13:35:19 +01:00
Clifford Wolf
1e3c2bff72
Added support for (single-clock) transparent memories to bram tests
2016-11-01 10:03:13 +01:00
Clifford Wolf
4a981a3bd8
Fixed "make test" for git head of iverilog
2016-10-11 12:12:32 +02:00
Clifford Wolf
6300c0b3c2
Merge branch 'master' of https://github.com/brouhaha/yosys
2016-09-23 13:42:08 +02:00
Eric Smith
f4240cc8a4
Add optional SEED=n command line option to Makefile, and -S n command line option to test scripts, for deterministic regression tests.
2016-09-22 11:49:29 -06:00
Clifford Wolf
0c697b9eac
Added autotest.sh -I
2016-09-20 09:29:56 +02:00
Kaj Tuomi
2c031cd24f
Fix for modules with big interfaces.
2016-09-13 13:13:27 +03:00
Clifford Wolf
450f6f59b4
Fixed bug with memories that do not have a down-to-zero data width
2016-08-22 14:27:46 +02:00
Clifford Wolf
cdd0b85e47
Added another mem2reg test case
2016-08-21 13:45:46 +02:00
Clifford Wolf
82a4a0230f
Another bugfix in mem2reg code
2016-08-21 13:23:58 +02:00
Clifford Wolf
88a67afa7d
Added "test_autotb -seed" (and "autotest.sh -S")
2016-08-06 13:32:29 +02:00
Clifford Wolf
9a101dc1f7
Fixed mem assignment in left-hand-side concatenation
2016-07-08 14:31:06 +02:00
Clifford Wolf
e420412043
Fixed autotest.sh handling of `timescale
2016-07-02 13:32:20 +02:00
Clifford Wolf
7a4ee5da74
Fixed init issue in mem2reg_test2 test case
2016-06-17 20:15:11 +02:00
Clifford Wolf
11f7b8a2a1
Added opt_expr support for div/mod by power-of-two
2016-05-29 12:17:36 +02:00
Clifford Wolf
8e9e793126
Some fixes in tests/asicworld/*_tb.v
2016-05-20 17:13:11 +02:00
Clifford Wolf
1e227caf72
Improvements and fixes in autotest.sh script and test_autotb
2016-05-20 16:58:02 +02:00
Kaj Tuomi
f6221ade95
Fix for Modelsim transcript line warp issue #164
2016-05-19 11:34:38 +03:00
Clifford Wolf
1761d08dd2
Bugfix and improvements in memory_share
2016-04-21 14:22:58 +02:00
Sergey Kvachonok
e14055edf0
Optionally use ${CC} when compiling test utils.
...
Default to gcc when not set.
2016-03-25 10:35:42 +03:00
Clifford Wolf
0f94902125
Added tests/simple/graphtest.v
2015-11-30 11:41:12 +01:00
Clifford Wolf
7ae3d1b5a9
More bugfixes in handling of parameters in tasks and functions
2015-11-12 13:02:36 +01:00
Clifford Wolf
34f2b84fb6
Fixed handling of parameters and localparams in functions
2015-11-11 10:54:35 +01:00
Clifford Wolf
ddf3e2dc65
Bugfix in memory_dff
2015-10-31 22:01:41 +01:00
Clifford Wolf
ccdbf41be6
Improvements in wreduce
2015-10-31 13:39:30 +01:00
Clifford Wolf
924d9d6e86
Added read-enable to memory model
2015-09-25 12:23:11 +02:00
Clifford Wolf
c475deec6c
Switched to Python 3
2015-08-22 09:59:33 +02:00
Larry Doolittle
6c00704a5e
Another block of spelling fixes
...
Smaller this time
2015-08-14 23:27:05 +02:00
Clifford Wolf
84bf862f7c
Spell check (by Larry Doolittle)
2015-08-14 10:56:05 +02:00
Clifford Wolf
ad8efeb13f
Fixed CRLF line endings
2015-08-13 09:35:00 +02:00
Clifford Wolf
08ad5409a2
Some ASCII encoding fixes (comments and docs) by Larry Doolittle
2015-08-13 09:30:20 +02:00
Clifford Wolf
6c84341f22
Fixed trailing whitespaces
2015-07-02 11:14:30 +02:00
Clifford Wolf
8c79765de5
Progress in SMV back-end
2015-06-19 14:08:46 +02:00
Clifford Wolf
8a86162ae9
Progress in SMV back-end
2015-06-18 16:29:11 +02:00
Clifford Wolf
6061b7bd58
bugfix in blif front-end
2015-05-18 11:15:49 +02:00
Clifford Wolf
83499dc1ba
added vloghtb test_febe.sh
2015-05-17 19:54:00 +02:00
Clifford Wolf
dae00e1d83
changed file() to open() in python scripts
2015-05-11 21:58:21 +02:00
Clifford Wolf
724cead61d
Added "pmuxtree" command
2015-04-07 20:27:10 +02:00
Clifford Wolf
604c097f98
fix for python 2.6.6
2015-03-20 09:10:02 +01:00
Clifford Wolf
e9368a1d7e
Various fixes for memories with offsets
2015-02-14 14:21:15 +01:00
Clifford Wolf
dcf2e24240
Added $meminit support to "memory" command
2015-02-14 12:55:03 +01:00
Clifford Wolf
913c304fe6
Added $meminit test case
2015-02-14 11:26:20 +01:00
Clifford Wolf
d58c3eca3a
Some test related fixes
...
(incl. removal of three bad test cases)
2015-02-12 17:45:44 +01:00
Clifford Wolf
e666611534
Bugfix in resource sharing test
2015-01-27 19:30:06 +01:00
Clifford Wolf
8d295730e5
Refactoring of memory_bram and xilinx brams
2015-01-18 19:05:29 +01:00
Clifford Wolf
694cc01f1d
improvements in muxtree/select_leaves test
2015-01-18 13:24:01 +01:00
Clifford Wolf
f630868bc9
Improvements in opt_muxtree
2015-01-18 12:57:36 +01:00
Clifford Wolf
dfa42e272c
Tiny fix in vcdcd.pl
2015-01-13 12:59:29 +01:00
Clifford Wolf
daae35319b
Added memory_bram "shuffle_enable" feature
2015-01-04 13:14:30 +01:00
Clifford Wolf
45918b8315
Added "memory -bram"
2015-01-03 17:40:20 +01:00
Clifford Wolf
a7fe87f888
Added memory_bram 'or_next_if_better' feature
2015-01-03 17:34:05 +01:00
Clifford Wolf
fd2c224c04
memory_bram transp support
2015-01-03 12:41:46 +01:00
Clifford Wolf
a7e43ae3d9
Progress in memory_bram
2015-01-03 10:57:01 +01:00
Clifford Wolf
90f4017703
Added proper clkpol support to memory_bram
2015-01-02 22:57:08 +01:00
Clifford Wolf
1dca7ae486
Fixes and improvements in bram test
2015-01-02 18:54:22 +01:00
Clifford Wolf
03b3c02540
Progress in bram testbench
2015-01-02 17:50:15 +01:00
Clifford Wolf
bbf89c4dc6
Progress in memory_bram
2015-01-02 13:59:47 +01:00
Clifford Wolf
36c20f2ede
Progress in memory_bram
2015-01-02 00:07:44 +01:00
Clifford Wolf
24ae156a74
Progress in bram testbench
2015-01-01 20:58:33 +01:00
Clifford Wolf
340e769667
Bram testbench (incomplete)
2015-01-01 17:01:17 +01:00
Clifford Wolf
1e0f6b5ddb
Added "yosys -qq" to also quiet warning messages
2014-11-09 11:02:20 +01:00
Clifford Wolf
f9c096eeda
Added support for task and function args in parentheses
2014-10-27 13:21:57 +01:00
Clifford Wolf
7815f81c32
Added "synth" command
2014-09-14 16:09:06 +02:00
Clifford Wolf
76f8128123
Fixed autotest for non-basename arguments
2014-09-06 12:10:57 +02:00
Clifford Wolf
01ef34c147
Added tests/various/constmsk_test.ys
2014-09-04 15:07:30 +02:00
Clifford Wolf
88db09255b
Added autotest -e (do not use -noexpr on write_verilog)
2014-08-30 18:34:07 +02:00
Clifford Wolf
c2df5b9175
Cosmetic changes to FSM tests
2014-08-21 17:40:49 +02:00
Clifford Wolf
28cf48e31f
Some improvements in FSM mapping and recoding
2014-08-14 11:22:45 +02:00
Clifford Wolf
1dd8252169
Added test_verific mode to tests/fsm/generate.py
2014-08-12 15:43:30 +02:00
Clifford Wolf
cad98bcd89
Added multi-dim memory test (requires iverilog git head)
2014-08-12 10:37:47 +02:00
Clifford Wolf
788bd02f97
Fixed FSM mapping for multiple reset-like signals
2014-08-10 12:04:02 +02:00
Clifford Wolf
2faef89738
Some improvements in fsm_opt and fsm_map for FSM with unreachable states
2014-08-09 14:49:51 +02:00
Clifford Wolf
51aa5544fb
Improved FSM tests
2014-08-08 15:08:11 +02:00
Clifford Wolf
c07774b0b6
Added FSM test bench
2014-08-08 13:12:18 +02:00
Clifford Wolf
91dd87e60b
Improved scope resolution of local regs in Verilog+AST frontend
2014-08-05 12:15:53 +02:00
Clifford Wolf
0129d41efa
Fixed AST handling of variables declared inside a functions main block
2014-08-05 08:35:51 +02:00
Clifford Wolf
358bf70a21
Added "wreduce" to some of the standard test benches
2014-08-03 20:22:33 +02:00
Clifford Wolf
5e641acc90
Consolidated hana test benches into fewer files
...
for pf in test_simulation_{always,and,buffer,decoder,inc,mux,nand,nor,or,seq,shifter,sop,techmap,xnor,xor}; do
gawk 'FNR == 1 { printf("\n// %s\n",FILENAME); } { gsub("^module *", sprintf("module f%d_",ARGIND)); print; }' \
${pf}_*_test.v > $pf.v; ../tools/autotest.sh $pf.v; mv -v ${pf}_*_test.v Attic/; done;
..etc..
2014-08-01 03:57:37 +02:00
Clifford Wolf
03ef9a75c6
Added "test_autotb -n <num_iter>" option
2014-08-01 03:55:51 +02:00
Clifford Wolf
7d98645fe8
Added "make -j{N}" support to "make test"
2014-07-30 19:23:26 +02:00
Clifford Wolf
e6df25bf74
Renamed "write_autotest" to "test_autotb" and moved to passes/tests/
2014-07-29 21:12:50 +02:00
Clifford Wolf
27a872d1e7
Added support for "upto" wires to Verilog front- and back-end
2014-07-28 14:25:03 +02:00
Clifford Wolf
c469be883b
Improvements in tests/vloghtb
2014-07-28 09:15:40 +02:00
Clifford Wolf
8b0f50792c
Added techmap -extern
2014-07-27 21:31:18 +02:00
Clifford Wolf
d49dec1f86
Added tests/various/.gitignore
2014-07-26 17:43:41 +02:00
Clifford Wolf
b21ebe1859
Added tests/various/submod_extract.ys
2014-07-26 17:22:18 +02:00
Clifford Wolf
027819c7e8
Use "wget -N" in tests/vloghtb/run-test.sh
2014-07-26 14:08:43 +02:00
Clifford Wolf
50f22ff30c
Renamed some of the test cases in tests/simple to avoid name collisions
2014-07-25 13:01:45 +02:00
Clifford Wolf
0229d68fc9
Use "opt -fine" in test/vloght/test_mapopt.sh
2014-07-21 21:39:59 +02:00
Clifford Wolf
1241a9fd50
Added "opt_const -fine" and "opt_reduce -fine"
2014-07-21 16:34:16 +02:00
Clifford Wolf
668306d00f
Various improvements in test/vloghtb
2014-07-21 14:40:57 +02:00
Clifford Wolf
3cb61d03f8
Wider range of cell types supported in "share" pass
2014-07-21 12:18:29 +02:00
Clifford Wolf
8836943693
Added yet another resource sharing test case
2014-07-20 21:15:01 +02:00
Clifford Wolf
e9506bb2da
Supercell creation for $div/$mod worked all along, fixed test benches
2014-07-20 18:54:06 +02:00
Clifford Wolf
7a6d578b81
Improved tests/share/generate.py
2014-07-20 17:06:57 +02:00
Clifford Wolf
4af8d84f01
Small fix in tests/vloghtb/run-test.sh
2014-07-20 17:05:20 +02:00
Clifford Wolf
4c38ec1cc8
Added "miter -equiv -flatten"
2014-07-20 15:33:07 +02:00
Clifford Wolf
2e358bd667
Added tests/vloghtb/test_share.sh
2014-07-20 15:33:05 +02:00
Clifford Wolf
6f450d0224
Added tests/share for testing "share" supercell creation
2014-07-20 15:32:59 +02:00
Clifford Wolf
3f9f0c047d
Added tests/vloghtb
2014-07-20 02:19:44 +02:00
Clifford Wolf
297a0962ea
Added SAT-based write-port sharing to memory_share
2014-07-19 15:33:55 +02:00
Clifford Wolf
26f982ac0b
Fixed bug in memory_share feedback-to-en code
2014-07-19 15:32:14 +02:00
Clifford Wolf
e441f07d89
Added translation from read-feedback to en-signals in memory_share
2014-07-18 16:46:40 +02:00
Clifford Wolf
ddb01df42e
Bugfix in tests/memories/run-test.sh
2014-07-18 13:45:25 +02:00
Clifford Wolf
5d9127418b
added tests/memories
2014-07-18 13:25:19 +02:00
Clifford Wolf
ec3a798194
Also simulate unmapped memories in "make test"
2014-07-17 16:53:52 +02:00
Clifford Wolf
9b183539af
Implemented dynamic bit-/part-select for memory writes
2014-07-17 16:49:23 +02:00
Clifford Wolf
5867f6bcdc
Added support for bit/part select to mem2reg rewriter
2014-07-17 13:49:32 +02:00
Clifford Wolf
6d69d4aaa8
Added support for constant bit- or part-select for memory writes
2014-07-17 13:13:21 +02:00
Clifford Wolf
73a345294a
Changed tests/techmap/mem_simple_4x1_map for new $mem/$memwr WR_EN interface
2014-07-16 14:08:51 +02:00
Clifford Wolf
964a67ac41
Added note to "make test": use git checkout of iverilog
2014-07-16 10:03:07 +02:00
Clifford Wolf
3b52121d32
now ignore init attributes on non-register wires in sat command
2014-07-05 11:18:38 +02:00
Clifford Wolf
ee8ad72fd9
fixed parsing of constant with comment between size and value
2014-07-02 06:27:04 +02:00
Clifford Wolf
076182c34e
Fixed handling of mixed real/int ternary expressions
2014-06-25 10:05:36 +02:00
Clifford Wolf
3345fa0bab
Little steps in realmath test bench
2014-06-21 21:43:04 +02:00
Clifford Wolf
df76da8fd7
Added test case for AstNode::MEM2REG_FL_CMPLX_LHS
2014-06-17 21:49:59 +02:00
Clifford Wolf
798ff88855
Improved handling of relational op of real values
2014-06-17 12:47:51 +02:00
Clifford Wolf
88470283c9
Little steps in realmath test bench
2014-06-16 15:21:08 +02:00
Clifford Wolf
398482eced
Removed long running tests from tests/simple/realexpr.v (replaced by tests/realmath)
2014-06-15 09:39:22 +02:00
Clifford Wolf
a4ec19c25c
Added tests/realmath to "make test"
2014-06-15 09:31:03 +02:00
Clifford Wolf
656685fa31
Improved realmath test bench
2014-06-15 08:48:41 +02:00
Clifford Wolf
11d2add1b9
improved realmath test bench
2014-06-14 21:00:51 +02:00
Clifford Wolf
39eb347c67
progress in realmath test bench
2014-06-14 19:56:22 +02:00
Clifford Wolf
ebe2d73330
added first draft of real math testcase generator
2014-06-14 19:24:01 +02:00
Clifford Wolf
f3b4a9dd24
Added support for math functions
2014-06-14 13:36:23 +02:00
Clifford Wolf
406f86a91e
Added realexpr.v test case
2014-06-14 12:01:17 +02:00
Clifford Wolf
482d9208aa
Added read_verilog -sv options, added support for bit, logic,
...
allways_ff, always_comb, and always_latch
2014-06-12 11:54:20 +02:00
Clifford Wolf
3af7c69d1e
added tests for new verilog features
2014-06-07 12:26:11 +02:00
Clifford Wolf
c82db39935
Added tests/simple/repwhile.v
2014-06-06 17:47:20 +02:00
Clifford Wolf
a67cd2d4a2
Progress in Verific bindings
2014-03-17 01:56:00 +01:00
Clifford Wolf
0ac915a757
Progress in Verific bindings
2014-03-14 11:46:13 +01:00
Clifford Wolf
bada3ee815
Fixed yosys path in tests/techmap/mem_simple_4x1_runtest.sh
2014-03-11 11:59:58 +01:00
Clifford Wolf
4fd1a4c12b
Use "verilog -noattr" in tests/techmap/mem_simple_4x1 test (for old iverilog)
2014-03-11 11:39:30 +01:00
Clifford Wolf
3c5e973092
Use private namespace in mem_simple_4x1_map
2014-02-21 12:14:38 +01:00
Clifford Wolf
81b3f52519
Added tests/techmap/mem_simple_4x1
2014-02-21 12:06:40 +01:00
Clifford Wolf
772330608a
Added vcd2txt.pl and txt2tikztiming.py (tests/tools/...)
2014-02-19 12:40:49 +01:00
Clifford Wolf
30379ea20d
Added frontend (-f) option to autotest.sh
2014-02-15 15:40:17 +01:00
Clifford Wolf
7664f5d92b
Updated ABC and some related changes
2014-02-13 08:07:08 +01:00
Clifford Wolf
9ce7b0fc3b
Disabled "abc -dff" in "make test" for now (waiting for scorr bugfix in ABC)
2014-02-12 13:11:58 +01:00
Clifford Wolf
039bb456cc
Added test cases for expose -evert-dff
2014-02-08 21:31:56 +01:00
Clifford Wolf
244e8ce1f4
Added splice command
2014-02-07 20:30:56 +01:00
Clifford Wolf
849fd62cfe
Added counters sat test case
2014-02-06 01:00:56 +01:00
Clifford Wolf
aa9da46807
Removed old unused files from tests/
2014-02-05 01:55:39 +01:00
Clifford Wolf
7a66b38c3e
Added test cases for sat command
2014-02-04 13:43:34 +01:00
Clifford Wolf
a6750b3753
Added TRANSPARENT parameter to $memrd (and RD_TRANSPARENT to $mem)
2014-02-03 13:01:45 +01:00
Clifford Wolf
de9226a64f
Replaced isim with xsim in tests/tools/autotest.sh, removed xst support
2014-02-03 13:00:55 +01:00
Clifford Wolf
4df7e03ec9
Bugfix in name resolution with generate blocks
2014-01-30 15:01:28 +01:00
Clifford Wolf
fb2bf934dc
Added correct handling of $memwr priority
2014-01-03 00:22:17 +01:00
Clifford Wolf
6dec0e0b3e
Added autotest.sh -p option
2014-01-02 17:52:48 +01:00
Clifford Wolf
ab3f6266ad
Use "abc -dff" in "make test"
2013-12-31 21:25:34 +01:00
Clifford Wolf
a582b9d184
Fixed commented out techmap call in tests/tools/autotest.sh
2013-12-31 13:51:25 +01:00
Clifford Wolf
ecc30255ba
Added proper === and !== support in constant expressions
2013-12-27 13:50:08 +01:00
Clifford Wolf
994c83db01
Added multiplier test case from eda playground
2013-12-18 13:43:53 +01:00
Clifford Wolf
fbd06a1afc
Added elsif preproc support
2013-12-18 13:41:36 +01:00
Clifford Wolf
921064c200
Added support for macro arguments
2013-12-18 13:21:02 +01:00
Clifford Wolf
4a4a3fc337
Various improvements in support for generate statements
2013-12-04 21:06:54 +01:00
Clifford Wolf
93a70959f3
Replaced RTLIL::Const::str with generic decoder method
2013-12-04 14:14:05 +01:00
Clifford Wolf
a2d053694b
Fix in sincos testbench gen
2013-12-04 09:24:52 +01:00
Clifford Wolf
d1517b7982
Added sincos test case
2013-12-04 09:10:41 +01:00
Clifford Wolf
1afe6589df
Renamed stdcells_sim.v to simcells.v and fixed blackbox.v
2013-11-24 20:44:00 +01:00
Clifford Wolf
7eaad2218d
Removed now obsolete test cases
2013-11-24 17:30:04 +01:00
Clifford Wolf
609caa23b5
Implemented correct handling of signed module parameters
2013-11-24 17:17:21 +01:00
Clifford Wolf
1e6836933d
Added modelsim support to autotest
2013-11-24 15:10:43 +01:00
Clifford Wolf
65ad556f3d
Another name resolution bugfix for generate blocks
2013-11-20 13:57:40 +01:00
Clifford Wolf
92035fb38e
Implemented indexed part selects
2013-11-20 13:05:27 +01:00
Clifford Wolf
19dba2561e
Implemented part/bit select on memory read
2013-11-20 10:51:32 +01:00
Clifford Wolf
c5e26f839c
Added additional mem2reg testcase
2013-11-18 19:55:39 +01:00
Clifford Wolf
2a25e3bca3
Fixed parsing of default cases when not last case
2013-11-18 16:10:50 +01:00
Clifford Wolf
fc6dc0d7b8
Fixed handling of power operator
2013-11-07 22:20:00 +01:00
Clifford Wolf
ada80545fa
Behavior should be identical now to rev. 0b4a64ac6a
(next: testing before constfold fixes)
2013-11-02 21:13:01 +01:00
Clifford Wolf
943329c1dc
Various ast changes for early expression width detection (prep for constfold fixes)
2013-11-02 13:00:17 +01:00
Clifford Wolf
628b994cf6
Added support for complex set-reset flip-flops in proc_dff
2013-10-24 16:54:05 +02:00
Clifford Wolf
d61699843f
Improved handling of dff with async resets
2013-10-21 14:51:58 +02:00
Clifford Wolf
288ba9618a
Moved common techlib files to techlibs/common
2013-09-15 11:52:57 +02:00
Clifford Wolf
759852914d
Added support for "2**n" shifter encoding
2013-08-12 14:47:50 +02:00
Clifford Wolf
c8763301b4
Added $div and $mod technology mapping
2013-08-09 17:09:24 +02:00
Clifford Wolf
3650fd7fbe
More fixes in ternary op sign handling
2013-07-12 13:13:04 +02:00
Clifford Wolf
ded769c98c
Fixed sign handling in ternary operator
2013-07-12 01:15:37 +02:00
Clifford Wolf
b380c8c790
Another vloghammer related bugfix
2013-07-11 19:24:59 +02:00
Clifford Wolf
5dab327b30
More fixes in ast expression sign/width handling
2013-07-09 23:41:43 +02:00
Clifford Wolf
618b2ac994
Merge branch 'master' of github.com:cliffordwolf/yosys
2013-07-09 19:00:10 +02:00
Clifford Wolf
7daeee340a
Fixed shift ops with large right hand side
2013-07-09 18:59:59 +02:00
Clifford Wolf
00a6c1d9a5
Major redesign of expr width/sign detecion (verilog/ast frontend)
2013-07-09 14:31:57 +02:00
Clifford Wolf
e8da3ea7b6
Fixed another bug found using vloghammer
2013-07-07 16:49:30 +02:00
Clifford Wolf
52d21a63ca
Removed tests/xsthammer
...
This test is now available as 'vloghammer' in a seperate repository:
https://github.com/cliffordwolf/VlogHammer
2013-07-07 13:01:15 +02:00
Clifford Wolf
92a5961fd3
Fixed vivado related xsthammer bugs
2013-07-05 19:33:42 +02:00
Clifford Wolf
940f838dae
Various improvements in xsthammer report generator
2013-07-05 16:04:02 +02:00
Clifford Wolf
3fd37061bf
Added work-around to isim bug in xsthammer report script
2013-07-05 15:29:03 +02:00
Clifford Wolf
238ff14810
Added CARRY4 Xilinx cell to xsthammer cell lib
2013-07-05 14:46:33 +02:00
Clifford Wolf
45105faf25
Added xsthammer report generator
2013-07-05 14:46:06 +02:00
Clifford Wolf
cd33db25d1
Improved xsthammer quartus support
2013-07-04 21:26:49 +02:00
Clifford Wolf
14c84c111b
Added Altera Cyclon III cell library to xsthammer
2013-07-04 14:50:03 +02:00
Clifford Wolf
56432a920f
Added defparam support to Verilog/AST frontend
2013-07-04 14:12:33 +02:00
Clifford Wolf
be1fca3428
Added Altera Quartus support to xsthammer
2013-07-03 20:40:54 +02:00
Clifford Wolf
28539541ed
Progress in xsthammer
2013-07-03 11:19:18 +02:00
Clifford Wolf
a5fe2565b7
Added vivado support to xsthammer
2013-06-26 12:34:06 +02:00
Clifford Wolf
8fbb5b6240
Added timout functionality to SAT solver
2013-06-20 12:49:10 +02:00
Clifford Wolf
21e38bed98
Added "eval" pass
2013-06-19 09:30:37 +02:00
Clifford Wolf
5cf04f33fa
Added more stuff to xsthammer, found first xst bug
2013-06-17 11:30:25 +02:00
Clifford Wolf
6ef8c6fb8a
Added ternary op and concat op to xsthammer
2013-06-15 11:00:34 +02:00
Clifford Wolf
30db70b1ba
Added consteval testing to xsthammer and fixed bugs
2013-06-13 19:51:13 +02:00
Clifford Wolf
7f6c83a853
More xsthammer improvements (using xst 14.5 now)
2013-06-13 17:23:51 +02:00
Clifford Wolf
bf2c149329
Another fix for a bug found using xsthammer
2013-06-12 19:09:14 +02:00
Clifford Wolf
4b311b7b99
Further improved and extended xsthammer
2013-06-11 19:49:35 +02:00
Clifford Wolf
8ce99fa686
More xsthammer improvements
2013-06-10 21:07:22 +02:00
Clifford Wolf
9026511821
Progress xsthammer scripts
2013-06-10 16:17:09 +02:00
Clifford Wolf
a6370ce857
Progress in xsthammer: working proof for cell models
2013-06-10 14:02:11 +02:00
Clifford Wolf
d07b32ade5
Progress on xsthammer
2013-06-10 12:37:05 +02:00
Clifford Wolf
af83ed168e
Added first xsthammer scripts
2013-06-10 01:40:20 +02:00
Clifford Wolf
cc05404128
Fixed undef behavior in tests/asicworld/code_verilog_tutorial_fsm_full_tb.v
2013-05-24 15:15:59 +02:00
Clifford Wolf
fbadb54b9b
Removed test cases that have been moved to yosys-test.
...
https://github.com/cliffordwolf/yosys-tests/
2013-05-17 15:32:30 +02:00
Clifford Wolf
ff4a1dd06c
Improved vcdcd.pl (added -d option)
2013-05-14 09:41:47 +02:00
Clifford Wolf
be8ecd6d16
Some improvements in vcdcd.pl
2013-05-14 08:50:59 +02:00
Clifford Wolf
e0c408cb4a
Fixed a bug in AST frontend for cases with non-blocking assigned variables as case values
2013-04-13 21:19:10 +02:00
Clifford Wolf
f1a2fd966f
Now only use value from "initial" when no matching "always" block is found
2013-03-31 11:51:12 +02:00
Clifford Wolf
5640b7d607
Added test cases from 2012 paper on comparison of foss verilog synthesis tools
2013-03-31 11:17:56 +02:00
Clifford Wolf
04843bdcbe
Added k68 (m68k compatible cpu) test case from verilator
2013-03-31 11:00:46 +02:00
Clifford Wolf
d9bc024d29
Renamed hansimem.v test case to mem_arst.v
2013-03-24 15:25:08 +01:00
Clifford Wolf
c3c9e5a02f
Added hansimem testcase (memory with async reset)
2013-03-24 10:40:40 +01:00
Clifford Wolf
e6cbeb5b16
Set execute bit on tests/openmsp430/run-synth.sh for real
2013-03-17 09:10:09 +01:00
Johann Glaser
a6f004e6f8
set executable flags to run-synth.sh, added .gitignore
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2013-03-17 09:06:02 +01:00
Johann Glaser
3cfbc18601
added ckeck for Icarus Verilog, otherwise the tests are silently stopped
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2013-03-17 09:05:15 +01:00
Clifford Wolf
2d9cbd3b02
added more .gitignore files (make test)
2013-01-05 11:35:52 +01:00
Clifford Wolf
7764d0ba1d
initial import
2013-01-05 11:13:26 +01:00