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Fix in sincos testbench gen

This commit is contained in:
Clifford Wolf 2013-12-04 09:24:52 +01:00
parent d1517b7982
commit a2d053694b
1 changed files with 1 additions and 1 deletions
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2
tests/simple/sincos.v
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@ -39,7 +39,7 @@ input start;
input clock;
input reset;
(* gentb_constant="0" *)
(* gentb_constant = 1'b0 *)
wire reset;
always @(posedge clock, posedge reset) begin: DESIGN_PROCESSOR