mirror of https://github.com/YosysHQ/yosys.git
Improved FSM tests
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parent
58ac605470
commit
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1
Makefile
1
Makefile
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@ -218,6 +218,7 @@ test: $(TARGETS) $(EXTRA_TARGETS)
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+cd tests/asicworld && bash run-test.sh
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+cd tests/realmath && bash run-test.sh
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+cd tests/share && bash run-test.sh
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+cd tests/fsm && bash run-test.sh
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+cd tests/techmap && bash run-test.sh
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+cd tests/memories && bash run-test.sh
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+cd tests/various && bash run-test.sh
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@ -0,0 +1 @@
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temp
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@ -30,7 +30,7 @@ def random_expr(variables):
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return "%d'd%s" % (bits, random.randint(0, 2**bits-1))
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raise AssertionError
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for idx in range(100):
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for idx in range(50):
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with file('temp/uut_%05d.v' % idx, 'w') as f, redirect_stdout(f):
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print('module uut_%05d(clk, rst, a, b, c, x, y, z);' % (idx))
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print(' input clk, rst;')
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@ -79,5 +79,5 @@ for idx in range(100):
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print('opt; wreduce; share; opt; fsm;;')
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print('cd ..')
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print('miter -equiv -flatten -ignore_gold_x -make_outputs -make_outcmp gold gate miter')
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print('sat -verify -seq 5 -set-at 1 in_rst 1 -prove trigger 0 -prove-skip 1 -show-inputs -show-outputs miter')
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print('sat -verify-no-timeout -timeout 20 -seq 5 -set-at 1 in_rst 1 -prove trigger 0 -prove-skip 1 -show-inputs -show-outputs miter')
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@ -18,6 +18,7 @@ python generate.py
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echo "temp/uut_${idx}.log: temp/uut_${idx}.ys temp/uut_${idx}.v"
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echo " @echo -n '[$i]'"
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echo " @../../yosys -ql temp/uut_${idx}.log temp/uut_${idx}.ys"
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echo " @grep -q 'SAT proof finished' temp/uut_${idx}.log && echo -n K || echo -n T"
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all_targets="$all_targets temp/uut_${idx}.log"
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done
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echo "$all_targets"
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