mirror of https://github.com/YosysHQ/yosys.git
Added k68 (m68k compatible cpu) test case from verilator
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04843bdcbe
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@ -0,0 +1,25 @@
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diff --git a/bench/bench.cpp b/bench/bench.cpp
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index 47a50c4..de27fbb 100755
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--- a/bench/bench.cpp
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+++ b/bench/bench.cpp
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@@ -71,6 +71,7 @@ int main(int argc, char **argv, char **env) {
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main_time++;
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top->arbclk_i = !top->arbclk_i;
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if (main_time%5 == 0) top->clk = !top->clk;
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+ if (main_time%100000 == 0) cout<<"Partial sum = "<<hex<<top->sum<<"\n";
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}
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cout<<"Final sum = "<<hex<<top->sum<<"\n";
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diff --git a/rtl/k68_clkgen.v b/rtl/k68_clkgen.v
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index c201a97..55b9cad 100755
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--- a/rtl/k68_clkgen.v
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+++ b/rtl/k68_clkgen.v
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@@ -57,7 +57,7 @@ module k68_clkgen (/*AUTOARG*/
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assign clk4_o = cnt[1];
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assign clk_o = ~clk_i;
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- initial cnt = 0; // Power up state doesn't matter, but can't be X
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+ // initial cnt = 0; // Power up state doesn't matter, but can't be X
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always @(posedge clk_i) begin
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cnt <= cnt + 1'b1;
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@ -0,0 +1,6 @@
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#!/bin/bash
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set -ex
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rm -rf verilog-sim-benchmarks
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git clone http://git.veripool.org/git/verilog-sim-benchmarks
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cd verilog-sim-benchmarks
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patch -p1 < ../changes.diff
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@ -0,0 +1,30 @@
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#!/bin/bash
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if (
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set -ex
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cd verilog-sim-benchmarks
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rm -rf obj_dir_* synth
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cd rtl
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mkdir -p ../synth
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yosys -o ../synth/k68_soc.v -p 'hierarchy -check -top k68_soc; proc; opt; memory; opt' \
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k68_soc.v k68_arb.v k68_cpu.v k68_load.v k68_clkgen.v k68_decode.v k68_execute.v \
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k68_fetch.v k68_regbank.v k68_buni.v k68_b2d.v k68_ccc.v k68_d2b.v k68_rox.v \
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k68_calc.v k68_dpmem.v k68_sasc.v sasc_brg.v sasc_top.v sasc_fifo4.v
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cd ..
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VERILATOR_OPT="-Wno-fatal -Ibench --cc bench/k68_soc_test.v --exe bench/bench.cpp -prefix m68 -x-assign 0"
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verilator -Mdir obj_dir_rtl -Irtl $VERILATOR_OPT; make -C obj_dir_rtl -f m68.mk
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verilator -Mdir obj_dir_synth -Isynth $VERILATOR_OPT; make -C obj_dir_synth -f m68.mk
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./obj_dir_rtl/m68 100000 | tee output_rtl.txt
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./obj_dir_synth/m68 100000 | tee output_synth.txt
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diff -u <( grep ' sum ' output_rtl.txt; ) <( grep ' sum ' output_synth.txt; )
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); then
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echo OK
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exit 0
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else
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echo ERROR
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exit 1
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fi
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