mirror of https://github.com/YosysHQ/yosys.git
Major redesign of Verific SVA importer
Signed-off-by: Clifford Wolf <clifford@clifford.at>
This commit is contained in:
Clifford Wolf
parent
6f26695d9b
commit
25e33d7ab8
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@ -24,7 +24,6 @@
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// not prop
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// prop or prop
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// prop and prop
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// seq |-> prop
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// seq |=> prop
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// if (expr) prop [else prop]
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// prop until prop
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@ -35,7 +34,6 @@
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//
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// seq:
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// expr
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// expr ##N seq
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// expr ##[N:M] seq
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// seq or seq
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// seq and seq
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@ -43,12 +41,24 @@
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// first_match (seq)
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// expr throughout seq
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// seq within seq
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// seq [*N]
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// seq [*N:M]
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// expr [=N]
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// expr [=N:M]
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// expr [->N]
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// expr [->N:M]
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//
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// Notes:
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// |=> is a placeholder for |-> and |=>
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// "until" is a placeholder for all until operators
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// ##[N:M], [*N:M], [=N:M], [->N:M] includes ##N, [*N], [=N], [->N]
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//
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// Currently supported property styles:
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// not seq
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// seq |=> seq
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// seq |=> seq until seq
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//
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// Currently supported sequence operators:
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// ##[N:M]
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// [*N:M]
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// throughout
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#include "kernel/yosys.h"
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@ -60,6 +70,316 @@ USING_YOSYS_NAMESPACE
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using namespace Verific;
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#endif
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PRIVATE_NAMESPACE_BEGIN
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struct SvaFsmNode
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{
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vector<pair<int, SigBit>> edges, links;
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};
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struct SvaFsm
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{
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Module *module;
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SigBit clock;
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bool clockpol;
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SigBit trigger_sig = State::S1, disable_sig;
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SigBit accept_sig = State::Sz, reject_sig = State::Sz;
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SigBit throughout_sig = State::S1;
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bool materialized = false;
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vector<SigBit> disable_stack;
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vector<SigBit> throughout_stack;
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int startNode, acceptNode, rejectNode;
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vector<SvaFsmNode> nodes;
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SvaFsm(Module *mod, SigBit clk, bool clkpol, SigBit dis = State::S0, SigBit trig = State::S1)
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{
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module = mod;
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clock = clk;
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clockpol = clkpol;
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disable_sig = dis;
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trigger_sig = trig;
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startNode = createNode();
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acceptNode = createNode();
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rejectNode = createNode();
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}
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void pushDisable(SigBit sig)
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{
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log_assert(!materialized);
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disable_stack.push_back(disable_sig);
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if (disable_sig == State::S0)
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disable_sig = sig;
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else
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disable_sig = module->Or(NEW_ID, disable_sig, sig);
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}
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void popDisable()
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{
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log_assert(!materialized);
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log_assert(!disable_stack.empty());
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disable_sig = disable_stack.back();
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disable_stack.pop_back();
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}
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void pushThroughout(SigBit sig)
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{
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log_assert(!materialized);
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throughout_stack.push_back(throughout_sig);
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if (throughout_sig == State::S1)
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throughout_sig = sig;
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else
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throughout_sig = module->And(NEW_ID, throughout_sig, sig);
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}
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void popThroughout()
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{
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log_assert(!materialized);
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log_assert(!throughout_stack.empty());
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throughout_sig = throughout_stack.back();
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throughout_stack.pop_back();
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}
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SigBit getAccept()
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{
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if (accept_sig != State::Sz)
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return accept_sig;
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log_assert(!materialized);
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accept_sig = module->addWire(NEW_ID);
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return accept_sig;
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}
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SigBit getReject()
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{
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if (reject_sig != State::Sz)
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return reject_sig;
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log_assert(!materialized);
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reject_sig = module->addWire(NEW_ID);
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return reject_sig;
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}
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int createNode()
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{
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log_assert(!materialized);
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int idx = GetSize(nodes);
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nodes.push_back(SvaFsmNode());
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return idx;
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}
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void createEdge(int from_node, int to_node, SigBit ctrl = State::S1)
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{
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log_assert(!materialized);
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log_assert(0 <= from_node && from_node < GetSize(nodes));
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log_assert(0 <= to_node && to_node < GetSize(nodes));
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if (throughout_sig != State::S1) {
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if (ctrl != State::S1)
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ctrl = module->And(NEW_ID, throughout_sig, ctrl);
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else
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ctrl = throughout_sig;
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}
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nodes[from_node].edges.push_back(make_pair(to_node, ctrl));
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}
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void createLink(int from_node, int to_node, SigBit ctrl = State::S1)
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{
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log_assert(!materialized);
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log_assert(0 <= from_node && from_node < GetSize(nodes));
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log_assert(0 <= to_node && to_node < GetSize(nodes));
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if (throughout_sig != State::S1) {
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if (ctrl != State::S1)
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ctrl = module->And(NEW_ID, throughout_sig, ctrl);
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else
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ctrl = throughout_sig;
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}
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nodes[from_node].links.push_back(make_pair(to_node, ctrl));
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}
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void make_link_order(vector<int> &order, int node, int min)
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{
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order[node] = std::max(order[node], min);
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for (auto &it : nodes[node].links)
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make_link_order(order, it.first, order[node]+1);
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}
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void materialize_ndfsm()
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{
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log_assert(!materialized);
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materialized = true;
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vector<SigBit> next_state_sig(GetSize(nodes));
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vector<SigBit> state_sig(GetSize(nodes));
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// Create state FFs
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{
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SigBit not_disable = State::S1;
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if (disable_sig != State::S0)
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not_disable = module->Not(NEW_ID, disable_sig);
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for (int i = 0; i < GetSize(nodes); i++)
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{
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next_state_sig[i] = module->addWire(NEW_ID);
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Wire *w = module->addWire(NEW_ID);
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w->attributes["\\init"] = Const(0, 1);
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state_sig[i] = w;
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module->addDff(NEW_ID, clock, next_state_sig[i], state_sig[i], clockpol);
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if (i == startNode)
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state_sig[i] = module->Or(NEW_ID, state_sig[i], trigger_sig);
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if (disable_sig != State::S0)
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state_sig[i] = module->And(NEW_ID, state_sig[i], not_disable);
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}
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}
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// Follow Links
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{
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vector<int> node_order(GetSize(nodes));
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vector<vector<int>> order_to_nodes;
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for (int i = 0; i < GetSize(nodes); i++)
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make_link_order(node_order, i, 0);
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for (int i = 0; i < GetSize(nodes); i++) {
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if (node_order[i] >= GetSize(order_to_nodes))
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order_to_nodes.resize(node_order[i]+1);
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order_to_nodes[node_order[i]].push_back(i);
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}
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for (int order = 0; order < GetSize(order_to_nodes); order++)
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for (int node : order_to_nodes[order])
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{
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for (auto &it : nodes[node].links)
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{
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int target = it.first;
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SigBit ctrl = state_sig[node];
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if (it.second != State::S1)
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ctrl = module->And(NEW_ID, ctrl, it.second);
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state_sig[target] = module->Or(NEW_ID, state_sig[target], ctrl);
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}
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}
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}
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// Construct activations
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{
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vector<SigSpec> activate_sig(GetSize(nodes));
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vector<SigBit> activate_bit(GetSize(nodes));
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for (int i = 0; i < GetSize(nodes); i++) {
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for (auto &it : nodes[i].edges)
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activate_sig[it.first].append(module->And(NEW_ID, state_sig[i], it.second));
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}
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for (int i = 0; i < GetSize(nodes); i++) {
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if (GetSize(activate_sig[i]) == 0)
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activate_bit[i] = State::S0;
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else if (GetSize(activate_sig[i]) == 1)
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activate_bit[i] = activate_sig[i];
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else
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activate_bit[i] = module->ReduceOr(NEW_ID, activate_sig[i]);
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}
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if (activate_bit[rejectNode] != State::S0)
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{
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SigBit not_rej = module->Not(NEW_ID, next_state_sig[rejectNode]);
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for (int i = 0; i < GetSize(nodes); i++)
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if (i != rejectNode && activate_bit[i] != State::S0)
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activate_bit[i] = module->And(NEW_ID, activate_bit[i], not_rej);
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activate_bit[rejectNode] = State::S0;
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}
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for (int i = 0; i < GetSize(nodes); i++) {
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module->connect(next_state_sig[i], activate_bit[i]);
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}
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}
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// Construct output signals
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if (accept_sig != State::Sz) {
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module->connect(accept_sig, state_sig[acceptNode]);
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}
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if (reject_sig != State::Sz)
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{
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SigBit fsm_active = module->ReduceOr(NEW_ID, state_sig);
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SigBit fsm_next_active = module->ReduceOr(NEW_ID, next_state_sig);
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module->addEq(NEW_ID, {state_sig[acceptNode], fsm_next_active, fsm_active}, SigSpec(1, 3), reject_sig);
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}
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}
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void materialize_dfsm()
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{
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// FIXME
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log_abort();
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}
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bool is_linear()
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{
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for (int i = 0; i < GetSize(nodes); i++)
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if (GetSize(nodes[i].edges) + GetSize(nodes[i].links) > 1)
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return false;
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return true;
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}
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void dump()
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{
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log("-----------\n");
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for (int i = 0; i < GetSize(nodes); i++)
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{
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log("node %d:\n", i);
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if (i == startNode)
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log(" startNode\n");
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if (i == rejectNode)
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log(" rejectNode\n");
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if (i == acceptNode)
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log(" acceptNode\n");
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for (auto &it : nodes[i].edges) {
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if (it.second != State::S1)
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log(" egde %s -> %d\n", log_signal(it.second), it.first);
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else
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log(" egde -> %d\n", it.first);
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}
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for (auto &it : nodes[i].links) {
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if (it.second != State::S1)
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log(" link %s -> %d\n", log_signal(it.second), it.first);
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else
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log(" link -> %d\n", it.first);
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}
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}
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log("-----------\n");
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}
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};
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PRIVATE_NAMESPACE_END
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YOSYS_NAMESPACE_BEGIN
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pool<int> verific_sva_prims = {
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@ -254,6 +574,253 @@ struct VerificSvaImporter
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// ----------------------------------------------------------
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// SVA Importer
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int parse_sequence(SvaFsm *fsm, int start_node, Net *net)
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{
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Instance *inst = net_to_ast_driver(net);
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if (inst == nullptr) {
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int node = fsm->createNode();
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fsm->createLink(start_node, node, importer->net_map_at(net));
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return node;
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}
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if (inst->Type() == PRIM_SVA_SEQ_CONCAT)
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{
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const char *sva_low_s = inst->GetAttValue("sva:low");
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const char *sva_high_s = inst->GetAttValue("sva:high");
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int sva_low = atoi(sva_low_s);
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int sva_high = atoi(sva_high_s);
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bool sva_inf = !strcmp(sva_high_s, "$");
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int node = parse_sequence(fsm, start_node, inst->GetInput1());
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for (int i = 0; i < sva_low; i++) {
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int next_node = fsm->createNode();
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fsm->createEdge(node, next_node);
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node = next_node;
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}
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if (sva_inf)
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{
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fsm->createEdge(node, node);
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}
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else
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{
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for (int i = sva_low; i < sva_high; i++)
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{
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int next_node = fsm->createNode();
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fsm->createEdge(node, next_node);
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fsm->createLink(node, next_node);
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node = next_node;
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}
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}
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node = parse_sequence(fsm, node, inst->GetInput2());
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return node;
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}
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if (inst->Type() == PRIM_SVA_CONSECUTIVE_REPEAT)
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{
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const char *sva_low_s = inst->GetAttValue("sva:low");
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const char *sva_high_s = inst->GetAttValue("sva:high");
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int sva_low = atoi(sva_low_s);
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int sva_high = atoi(sva_high_s);
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bool sva_inf = !strcmp(sva_high_s, "$");
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int node = parse_sequence(fsm, start_node, inst->GetInput());
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for (int i = 1; i < sva_low; i++)
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{
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int next_node = fsm->createNode();
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fsm->createEdge(node, next_node);
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node = parse_sequence(fsm, next_node, inst->GetInput());
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}
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if (sva_inf)
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{
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int next_node = fsm->createNode();
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fsm->createEdge(node, next_node);
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next_node = parse_sequence(fsm, next_node, inst->GetInput());
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fsm->createLink(next_node, node);
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}
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else
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{
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for (int i = sva_low; i < sva_high; i++)
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{
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int next_node = fsm->createNode();
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fsm->createEdge(node, next_node);
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next_node = parse_sequence(fsm, next_node, inst->GetInput());
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fsm->createLink(node, next_node);
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node = next_node;
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}
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}
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return node;
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}
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if (inst->Type() == PRIM_SVA_THROUGHOUT)
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{
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log_assert(get_ast_input1(inst) == nullptr);
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SigBit expr = importer->net_map_at(inst->GetInput1());
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fsm->pushThroughout(expr);
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int node = parse_sequence(fsm, start_node, inst->GetInput2());
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fsm->popThroughout();
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return node;
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}
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// Handle unsupported primitives
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if (!importer->mode_keep)
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log_error("Verific SVA primitive %s (%s) is currently unsupported in this context.\n", inst->View()->Owner()->Name(), inst->Name());
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log_warning("Verific SVA primitive %s (%s) is currently unsupported in this context.\n", inst->View()->Owner()->Name(), inst->Name());
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return start_node;
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}
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void import()
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{
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module = importer->module;
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netlist = root->Owner();
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RTLIL::IdString root_name = module->uniquify(importer->mode_names || root->IsUserDeclared() ? RTLIL::escape_id(root->Name()) : NEW_ID);
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// parse SVA property clock event
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Instance *at_node = get_ast_input(root);
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// asynchronous immediate assertion/assumption/cover
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if (at_node == nullptr && (root->Type() == PRIM_SVA_IMMEDIATE_ASSERT ||
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root->Type() == PRIM_SVA_IMMEDIATE_COVER || root->Type() == PRIM_SVA_IMMEDIATE_ASSUME))
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{
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SigSpec sig_a = importer->net_map_at(root->GetInput());
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RTLIL::Cell *c = nullptr;
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if (eventually) {
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if (mode_assert) c = module->addLive(root_name, sig_a, State::S1);
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if (mode_assume) c = module->addFair(root_name, sig_a, State::S1);
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} else {
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if (mode_assert) c = module->addAssert(root_name, sig_a, State::S1);
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if (mode_assume) c = module->addAssume(root_name, sig_a, State::S1);
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if (mode_cover) c = module->addCover(root_name, sig_a, State::S1);
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}
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|
||||
importer->import_attributes(c->attributes, root);
|
||||
return;
|
||||
}
|
||||
|
||||
log_assert(at_node && at_node->Type() == PRIM_SVA_AT);
|
||||
|
||||
VerificClockEdge clock_edge(importer, get_ast_input1(at_node));
|
||||
clock = clock_edge.clock_sig;
|
||||
clock_posedge = clock_edge.posedge;
|
||||
|
||||
// parse disable_iff expression
|
||||
|
||||
Net *sequence_net = at_node->GetInput2();
|
||||
|
||||
while (1)
|
||||
{
|
||||
Instance *sequence_node = net_to_ast_driver(sequence_net);
|
||||
|
||||
if (sequence_node && sequence_node->Type() == PRIM_SVA_S_EVENTUALLY) {
|
||||
eventually = true;
|
||||
sequence_net = sequence_node->GetInput();
|
||||
continue;
|
||||
}
|
||||
|
||||
if (sequence_node && sequence_node->Type() == PRIM_SVA_DISABLE_IFF) {
|
||||
disable_iff = importer->net_map_at(sequence_node->GetInput1());
|
||||
sequence_net = sequence_node->GetInput2();
|
||||
continue;
|
||||
}
|
||||
|
||||
break;
|
||||
}
|
||||
|
||||
// parse SVA sequence into trigger signal
|
||||
|
||||
SigBit prop_okay;
|
||||
Instance *inst = net_to_ast_driver(sequence_net);
|
||||
|
||||
if (inst == nullptr)
|
||||
{
|
||||
prop_okay = importer->net_map_at(sequence_net);
|
||||
}
|
||||
else
|
||||
if (inst->Type() == PRIM_SVA_OVERLAPPED_IMPLICATION ||
|
||||
inst->Type() == PRIM_SVA_NON_OVERLAPPED_IMPLICATION)
|
||||
{
|
||||
Net *antecedent_net = inst->GetInput1();
|
||||
Net *consequent_net = inst->GetInput2();
|
||||
int node;
|
||||
|
||||
SvaFsm antecedent_fsm(module, clock, clock_posedge, disable_iff);
|
||||
node = parse_sequence(&antecedent_fsm, antecedent_fsm.startNode, antecedent_net);
|
||||
if (inst->Type() == PRIM_SVA_NON_OVERLAPPED_IMPLICATION) {
|
||||
int next_node = antecedent_fsm.createNode();
|
||||
antecedent_fsm.createEdge(node, next_node);
|
||||
node = next_node;
|
||||
}
|
||||
antecedent_fsm.createLink(node, antecedent_fsm.acceptNode);
|
||||
|
||||
SigBit antecedent_accept = antecedent_fsm.getAccept();
|
||||
antecedent_fsm.materialize_ndfsm();
|
||||
antecedent_fsm.dump();
|
||||
|
||||
SvaFsm consequent_fsm(module, clock, clock_posedge, disable_iff, antecedent_accept);
|
||||
node = parse_sequence(&consequent_fsm, consequent_fsm.startNode, consequent_net);
|
||||
consequent_fsm.createLink(node, consequent_fsm.acceptNode);
|
||||
|
||||
SigBit consequent_reject = consequent_fsm.getReject();
|
||||
prop_okay = module->Not(NEW_ID, consequent_reject);
|
||||
|
||||
if (consequent_fsm.is_linear())
|
||||
consequent_fsm.materialize_ndfsm();
|
||||
else
|
||||
log_error("Currently only linear sequences are allowed as impliciation consequent.\n");
|
||||
}
|
||||
else
|
||||
{
|
||||
// Handle unsupported primitives
|
||||
|
||||
if (!importer->mode_keep)
|
||||
log_error("Verific SVA primitive %s (%s) is currently unsupported in this context.\n", inst->View()->Owner()->Name(), inst->Name());
|
||||
log_warning("Verific SVA primitive %s (%s) is currently unsupported in this context.\n", inst->View()->Owner()->Name(), inst->Name());
|
||||
return;
|
||||
}
|
||||
|
||||
// add final FF stage
|
||||
|
||||
Wire *prop_okay_q = module->addWire(NEW_ID);
|
||||
prop_okay_q->attributes["\\init"] = Const(mode_cover ? 0 : 1, 1);
|
||||
module->addDff(NEW_ID, clock, prop_okay, prop_okay_q, clock_posedge);
|
||||
|
||||
// generate assert/assume/cover cell
|
||||
|
||||
RTLIL::Cell *c = nullptr;
|
||||
|
||||
if (eventually) {
|
||||
log_error("No support for eventually in Verific SVA bindings yet.\n");
|
||||
// if (mode_assert) c = module->addLive(root_name, prop_okay_q, prop_start_q);
|
||||
// if (mode_assume) c = module->addFair(root_name, prop_okay_q, prop_start_q);
|
||||
} else {
|
||||
if (mode_assert) c = module->addAssert(root_name, prop_okay_q, State::S1);
|
||||
if (mode_assume) c = module->addAssume(root_name, prop_okay_q, State::S1);
|
||||
if (mode_cover) c = module->addCover(root_name, prop_okay_q, State::S1);
|
||||
}
|
||||
|
||||
importer->import_attributes(c->attributes, root);
|
||||
}
|
||||
|
||||
#if 0
|
||||
// ----------------------------------------------------------
|
||||
// Old SVA Importer
|
||||
|
||||
vector<SigBit> sva_until_list_inclusive;
|
||||
vector<SigBit> sva_until_list_exclusive;
|
||||
vector<vector<SigBit>*> sva_sequence_alive_list;
|
||||
|
|
@ -603,6 +1170,7 @@ struct VerificSvaImporter
|
|||
|
||||
importer->import_attributes(c->attributes, root);
|
||||
}
|
||||
#endif
|
||||
};
|
||||
|
||||
void svapp_assert(Instance *inst)
|
||||
|
|
|
|||
|
|
@ -5,7 +5,7 @@ module top (
|
|||
default clocking @(posedge clk); endclocking
|
||||
|
||||
assert property (
|
||||
a ##[*] b |=> c until ##[*] d
|
||||
a ##[*] b |=> c until d
|
||||
);
|
||||
|
||||
`ifndef FAIL
|
||||
|
|
|
|||
Loading…
Reference in New Issue