mirror of https://github.com/YosysHQ/yosys.git
Fixed vivado related xsthammer bugs
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parent
940f838dae
commit
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@ -32,6 +32,11 @@ cat ../../xl_cells.v ../../cy_cells.v > cells.v
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echo -n > fail_patterns.txt
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for p in syn_vivado syn_quartus syn_xst syn_yosys rtl; do
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for q in syn_vivado syn_quartus syn_xst syn_yosys rtl; do
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if test -f result.${q}.${p}.txt; then
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cp result.${q}.${p}.txt result.${p}.${q}.txt
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continue
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fi
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{
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echo "read_verilog -DGLBL $p.v"
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echo "rename $job ${job}_1"
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@ -12,10 +12,11 @@ set -e
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mkdir -p vivado vivado_temp/$job
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cd vivado_temp/$job
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sed 's/^module/(* use_dsp48="no" *) module/;' < ../../rtl/$job.v > rtl.v
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cat > $job.tcl <<- EOT
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read_verilog ../../rtl/$job.v
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read_verilog rtl.v
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synth_design -part xc7k70t -top $job
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write_verilog ../../vivado/$job.v
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write_verilog -force ../../vivado/$job.v
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EOT
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/opt/Xilinx/Vivado/2013.2/bin/vivado -mode batch -source $job.tcl
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@ -88,6 +88,12 @@ output O;
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assign O = S ? I1 : I0;
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endmodule
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module MUXF8(O, I0, I1, S);
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input I0, I1, S;
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output O;
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assign O = S ? I1 : I0;
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endmodule
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module VCC(P);
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output P;
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assign P = 1;
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