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Fixed init issue in mem2reg_test2 test case

This commit is contained in:
Clifford Wolf 2016-06-17 20:15:11 +02:00
parent f498204ae4
commit 7a4ee5da74
1 changed files with 6 additions and 2 deletions
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8
tests/simple/mem2reg.v
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@ -19,9 +19,9 @@ endmodule
// ------------------------------------------------------
module mem2reg_test2(clk, mode, addr, data);
module mem2reg_test2(clk, reset, mode, addr, data);
input clk, mode;
input clk, reset, mode;
input [2:0] addr;
output [3:0] data;
@ -33,6 +33,10 @@ assign data = mem[addr];
integer i;
always @(posedge clk) begin
if (reset) begin
for (i=0; i<8; i=i+1)
mem[i] <= i;
end else
if (mode) begin
for (i=0; i<8; i=i+1)
mem[i] <= mem[i]+1;