mirror of https://github.com/YosysHQ/yosys.git
Use "verilog -noattr" in tests/techmap/mem_simple_4x1 test (for old iverilog)
This commit is contained in:
parent
78c64a6401
commit
4fd1a4c12b
|
@ -2,7 +2,7 @@
|
|||
|
||||
set -ev
|
||||
|
||||
yosys -o mem_simple_4x1_synth.v -p 'proc; opt; memory -nomap; techmap -map mem_simple_4x1_map.v;; techmap; opt; abc;; stat' mem_simple_4x1_uut.v
|
||||
yosys -b 'verilog -noattr' -o mem_simple_4x1_synth.v -p 'proc; opt; memory -nomap; techmap -map mem_simple_4x1_map.v;; techmap; opt; abc;; stat' mem_simple_4x1_uut.v
|
||||
|
||||
iverilog -o mem_simple_4x1_gold_tb mem_simple_4x1_tb.v mem_simple_4x1_uut.v
|
||||
iverilog -o mem_simple_4x1_gate_tb mem_simple_4x1_tb.v mem_simple_4x1_synth.v mem_simple_4x1_cells.v
|
||||
|
|
Loading…
Reference in New Issue