Renamed hansimem.v test case to mem_arst.v

2013-03-24 15:25:08 +01:00 · 2013-03-24 15:25:08 +01:00 · d9bc024d29
parent e1a80b356e
commit d9bc024d29
1 changed files with 0 additions and 1 deletions
--- a/tests/simple/mem_arst.v
+++ b/tests/simple/mem_arst.v
@ -21,7 +21,6 @@ module MyMem #(

  always @(negedge Reset_n_i or posedge Clk_i)
  begin
-    //$display("Data1 = %b, Data11 = %b, Data12 = %b, Data2 = %b, Data21 = %b, Data22 = %b",Data1_i,Data11,Data12,Data2_i,Data21,Data22);
    if (!Reset_n_i)
    begin
      Data_o <= 'bx;