mirror of https://github.com/YosysHQ/yosys.git
Some improvements in vcdcd.pl
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@ -8,14 +8,21 @@ use Verilog::VCD qw(parse_vcd list_sigs);
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$| = 1;
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my $opt_width = 0;
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if ($ARGV[0] eq '-w') {
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$opt_width = +$ARGV[1];
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shift @ARGV;
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shift @ARGV;
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}
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if ($#ARGV != 1) {
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print STDERR "\n";
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print STDERR "VCDCD - Value Change Dump Change Dumper\n";
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print STDERR "\n";
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print STDERR "Usage: $0 gold.vcd gate.vcd\n";
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print STDERR "Usage: $0 [-w N] gold.vcd gate.vcd\n";
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print STDERR "\n";
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print STDERR "Compare a known-good (gold) vcd file with a second (gate) vcd file.\n";
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print STDERR "This is not very efficient -- so use with care with large vcd files.\n";
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print STDERR "This is not very efficient -- so use with care on large vcd files.\n";
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print STDERR "\n";
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exit 1;
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}
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@ -112,6 +119,8 @@ for my $key (keys %$vcd_gate) {
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}
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}
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$signal_maxlen = $opt_width if $opt_width > 0;
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my $diffcount = 0;
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my %state_gold;
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my %state_gate;
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@ -161,8 +170,11 @@ sub cmp_signal($$)
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my @a = split //, $a;
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my @b = split //, $b;
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unshift @a, "-" while $#a < $#b;
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unshift @b, "-" while $#b < $#a;
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my $trail_a = $#a < 0 ? '-' : $a[0] eq '1' ? '0' : $a[0];
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my $trail_b = $#b < 0 ? '-' : $b[0] eq '1' ? '0' : $b[0];
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unshift @a, $trail_a while $#a < $#b;
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unshift @b, $trail_b while $#b < $#a;
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for (my $i = 0; $i <= $#a; $i++) {
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return 0 if $a[$i] ne "x" && $a[$i] ne $b[$i];
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