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Added another mem2reg test case

This commit is contained in:
Clifford Wolf 2016-08-21 13:45:46 +02:00
parent 82a4a0230f
commit cdd0b85e47
1 changed files with 11 additions and 0 deletions
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11
tests/simple/mem2reg.v
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@ -81,3 +81,14 @@ module mem2reg_test4(result1, result2, result3);
assign result3 = intermediate[depth2Index(3)];
endmodule
// ------------------------------------------------------
module mem2reg_test5(input ctrl, output out);
wire [0:0] foo[0:0];
wire [0:0] bar[0:1];
assign foo[0] = ctrl;
assign bar[0] = 0, bar[1] = 1;
assign out = bar[foo[0]];
endmodule