mirror of https://github.com/YosysHQ/yosys.git
Added autotest.sh -I
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e788ad4885
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@ -10,6 +10,9 @@ makejmode=false
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frontend="verilog"
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backend_opts="-noattr -noexpr"
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autotb_opts=""
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include_opts=""
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xinclude_opts=""
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minclude_opts=""
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scriptfiles=""
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scriptopt=""
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toolsdir="$(cd $(dirname $0); pwd)"
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@ -19,7 +22,7 @@ if [ ! -f $toolsdir/cmp_tbdata -o $toolsdir/cmp_tbdata.c -nt $toolsdir/cmp_tbdat
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( set -ex; ${CC:-gcc} -Wall -o $toolsdir/cmp_tbdata $toolsdir/cmp_tbdata.c; ) || exit 1
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fi
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while getopts xmGl:wkjvref:s:p:n:S: opt; do
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while getopts xmGl:wkjvref:s:p:n:S:I: opt; do
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case "$opt" in
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x)
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use_xsim=true ;;
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@ -52,8 +55,12 @@ while getopts xmGl:wkjvref:s:p:n:S: opt; do
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autotb_opts="$autotb_opts -n $OPTARG" ;;
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S)
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autotb_opts="$autotb_opts -seed $OPTARG" ;;
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I)
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include_opts="$include_opts -I $OPTARG"
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xinclude_opts="$xinclude_opts -i $OPTARG"
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minclude_opts="$minclude_opts +incdir+$OPTARG" ;;
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*)
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echo "Usage: $0 [-x|-m] [-G] [-w] [-k] [-j] [-v] [-r] [-e] [-l libs] [-f frontend] [-s script] [-p cmdstring] [-n iters] [-S seed] verilog-files\n" >&2
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echo "Usage: $0 [-x|-m] [-G] [-w] [-k] [-j] [-v] [-r] [-e] [-l libs] [-f frontend] [-s script] [-p cmdstring] [-n iters] [-S seed] [-I incdir] verilog-files\n" >&2
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exit 1
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esac
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done
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@ -63,18 +70,14 @@ compile_and_run() {
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if $use_modelsim; then
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altver=$( ls -v /opt/altera/ | grep '^[0-9]' | tail -n1; )
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/opt/altera/$altver/modelsim_ase/bin/vlib work
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/opt/altera/$altver/modelsim_ase/bin/vlog +define+outfile=\"$output\" "$@"
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/opt/altera/$altver/modelsim_ase/bin/vlog $minclude_opts +define+outfile=\"$output\" "$@"
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/opt/altera/$altver/modelsim_ase/bin/vsim -c -do 'run -all; exit;' testbench
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elif $use_xsim; then
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(
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set +x
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files=( "$@" )
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xilver=$( ls -v /opt/Xilinx/Vivado/ | grep '^[0-9]' | tail -n1; )
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/opt/Xilinx/Vivado/$xilver/bin/xvlog -d outfile=\"$output\" "${files[@]}"
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/opt/Xilinx/Vivado/$xilver/bin/xelab -R work.testbench
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)
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xilver=$( ls -v /opt/Xilinx/Vivado/ | grep '^[0-9]' | tail -n1; )
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/opt/Xilinx/Vivado/$xilver/bin/xvlog $xinclude_opts -d outfile=\"$output\" "$@"
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/opt/Xilinx/Vivado/$xilver/bin/xelab -R work.testbench
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else
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iverilog -Doutfile=\"$output\" -s testbench -o "$exe" "$@"
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iverilog $include_opts -Doutfile=\"$output\" -s testbench -o "$exe" "$@"
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vvp -n "$exe"
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fi
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}
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@ -109,7 +112,7 @@ do
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egrep -v '^\s*`timescale' ../$fn > ${bn}_ref.v
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if [ ! -f ../${bn}_tb.v ]; then
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"$toolsdir"/../../yosys -b "test_autotb $autotb_opts" -o ${bn}_tb.v ${bn}_ref.v
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"$toolsdir"/../../yosys -f "$frontend $include_opts" -b "test_autotb $autotb_opts" -o ${bn}_tb.v ${bn}_ref.v
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else
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cp ../${bn}_tb.v ${bn}_tb.v
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fi
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@ -135,16 +138,16 @@ do
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fi
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if [ -n "$scriptfiles" ]; then
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test_passes ${bn}_ref.v $scriptfiles
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test_passes -f "$frontend $include_opts" ${bn}_ref.v $scriptfiles
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elif [ -n "$scriptopt" ]; then
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test_passes -f "$frontend" -p "$scriptopt" ${bn}_ref.v
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test_passes -f "$frontend $include_opts" -p "$scriptopt" ${bn}_ref.v
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elif [ "$frontend" = "verific" ]; then
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test_passes -p "verific -vlog2k ${bn}_ref.v; verific -import -all; opt; memory;;"
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elif [ "$frontend" = "verific_gates" ]; then
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test_passes -p "verific -vlog2k ${bn}_ref.v; verific -import -gates -all; opt; memory;;"
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else
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test_passes -f "$frontend" -p "hierarchy; proc; opt; memory; opt; fsm; opt -full -fine" ${bn}_ref.v
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test_passes -f "$frontend" -p "hierarchy; synth -run coarse; techmap; opt; abc -dff" ${bn}_ref.v
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test_passes -f "$frontend $include_opts" -p "hierarchy; proc; opt; memory; opt; fsm; opt -full -fine" ${bn}_ref.v
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test_passes -f "$frontend $include_opts" -p "hierarchy; synth -run coarse; techmap; opt; abc -dff" ${bn}_ref.v
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fi
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touch ../${bn}.log
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}
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