Eddie Hung
dc3b21c1c0
abc9_ops -reintegrate: process box connections
2020-01-07 09:48:57 -08:00
Eddie Hung
6e12ba218b
Fix tabs and cleanup
2020-01-07 09:32:58 -08:00
Eddie Hung
5d9050a955
abc_exe: move 'count_outputs' check to abc
2020-01-07 08:00:32 -08:00
Eddie Hung
cf3a13746d
Add abc9_ops -reintegrate; moved out from now abc9_exe
2020-01-06 15:52:59 -08:00
Eddie Hung
46ed507b93
abc9_map: drop padding in box connections
2020-01-06 15:14:54 -08:00
Eddie Hung
1e2ab19f42
Merge remote-tracking branch 'origin/xaig_dff' into eddie/abc9_refactor
2020-01-06 15:05:08 -08:00
Eddie Hung
98ee8c14df
Merge remote-tracking branch 'origin/master' into xaig_dff
2020-01-06 15:02:44 -08:00
Eddie Hung
aa58472a29
Revert "write_xaiger to pad, not abc9_ops -prep_holes"
...
This reverts commit b5f60e055d
.
2020-01-06 13:34:45 -08:00
Eddie Hung
2bf442ca01
Cleanup
2020-01-06 13:02:04 -08:00
Eddie Hung
36ae2e52e4
Fix bad merge
2020-01-06 12:28:58 -08:00
Eddie Hung
6728a62d92
abc9: uncomment nothing to map message
2020-01-06 12:21:50 -08:00
Eddie Hung
921ff0f5e3
Merge remote-tracking branch 'origin/xaig_dff' into eddie/abc9_refactor
2020-01-06 12:04:08 -08:00
Eddie Hung
64ace4b0dc
Fixes
2020-01-06 11:53:48 -08:00
Eddie Hung
d152fe961f
Fixes
2020-01-06 11:50:55 -08:00
Eddie Hung
275e937fc1
abc9: remove -markgroups option, since operates on fully selected mod
2020-01-06 10:43:21 -08:00
Eddie Hung
1cf974ff40
abc9: cleanup
2020-01-06 10:26:49 -08:00
N. Engelhardt
fcc1c14adc
error if multiple -g options are given for abc
2020-01-06 19:10:13 +01:00
Eddie Hung
f576721a37
Add abc9.dff scratchpad option
2020-01-06 09:46:02 -08:00
Eddie Hung
45f87bb8ad
Merge remote-tracking branch 'origin/master' into xaig_dff
2020-01-06 09:44:17 -08:00
N. Engelhardt
7764b62d23
check scratchpad for arguments in abc pass too
2020-01-06 10:46:44 +01:00
N. Engelhardt
b376548fb9
inherit default values when checking scratchpad for arguments
2020-01-06 10:46:10 +01:00
Eddie Hung
b5f60e055d
write_xaiger to pad, not abc9_ops -prep_holes
2020-01-05 10:20:24 -08:00
Eddie Hung
8293a3fe74
Cleanup
2020-01-04 09:30:48 -08:00
Eddie Hung
6556a1347a
Fix when -dff not given
2020-01-04 09:17:01 -08:00
Eddie Hung
930f03e883
Call -prep_holes before aigmap; fix topo ordering
2020-01-03 15:38:18 -08:00
Eddie Hung
a819656972
WIP
2020-01-03 14:59:55 -08:00
Eddie Hung
559f3379e8
Preserve topo ordering from -prep_holes to write_xaiger
2020-01-03 14:37:58 -08:00
Eddie Hung
bb70915fb8
WIP
2020-01-03 13:21:56 -08:00
Eddie Hung
e1f494ab1d
WIP
2020-01-03 13:08:52 -08:00
N. Engelhardt
b2ad781b07
share codepath for scratchpad argument handling with command arguments
2020-01-03 14:11:41 +01:00
N. Engelhardt
341fd872b5
Merge branch 'master' of https://github.com/YosysHQ/yosys into abc_scratchpad_script
2020-01-03 12:28:48 +01:00
Eddie Hung
a050f9c808
Remove a few log_{push,pop}()
2020-01-02 16:14:04 -08:00
Eddie Hung
4eaf415052
aigmap everything
2020-01-02 16:13:44 -08:00
Eddie Hung
7fe268fcdb
Move scc operations out of inner loop
2020-01-02 16:00:26 -08:00
Eddie Hung
222e5e58ad
Cleanup
2020-01-02 15:58:45 -08:00
Eddie Hung
c28bea0382
Merge remote-tracking branch 'origin/xaig_dff' into eddie/abc9_refactor
2020-01-02 15:57:35 -08:00
Eddie Hung
5f97086302
Merge remote-tracking branch 'origin/master' into eddie/abc9_refactor
2020-01-02 15:14:12 -08:00
Eddie Hung
b454735bea
Merge remote-tracking branch 'origin/master' into xaig_dff
2020-01-02 12:44:06 -08:00
Eddie Hung
ca42af56a4
Update doc
2020-01-02 12:41:57 -08:00
Eddie Hung
8e507bd807
abc9 -keepff -> -dff; refactor dff operations
2020-01-02 12:36:54 -08:00
Eddie Hung
d6242be802
Merge pull request #1601 from YosysHQ/eddie/synth_retime
...
"abc -dff" to no longer retime by default
2020-01-02 08:46:24 -08:00
Eddie Hung
6dc63e84ef
Cleanup abc9, update doc for -keepff option
2020-01-01 08:34:57 -08:00
Eddie Hung
c40b1aae42
Restore abc9 -keepff
2020-01-01 08:34:43 -08:00
Eddie Hung
ac808c5e2a
attributes.count() -> get_bool_attribute()
2020-01-01 08:33:32 -08:00
Miodrag Milanovic
e0c879684f
take skip wire bits into account
2020-01-01 16:13:14 +01:00
Eddie Hung
96db05aaef
parse_xaiger to not take box_lookup
2019-12-31 17:06:03 -08:00
Eddie Hung
cac7f5d82e
Do not re-order carry chain ports, just precompute iteration order
2019-12-31 16:12:40 -08:00
Eddie Hung
dacdc6cc94
Remove abc9 -clk option
2019-12-30 22:59:14 -08:00
Eddie Hung
f1bf44ae8f
abc9_ops -prep_dff cope with lack of holes module
2019-12-30 22:58:39 -08:00
Eddie Hung
a367f703ea
Rename struct
2019-12-30 22:56:19 -08:00
Eddie Hung
fad99c2ec7
Merge remote-tracking branch 'origin/xaig_dff' into eddie/abc9_refactor
2019-12-30 20:14:24 -08:00
Eddie Hung
b42b64e8ed
Move Pass::call() out of abc9_ops into abc9
2019-12-30 19:23:54 -08:00
Eddie Hung
52f649dcfd
Use function arg
2019-12-30 18:47:06 -08:00
Eddie Hung
0317a2b476
holes_module to be whitebox
2019-12-30 18:46:22 -08:00
Eddie Hung
b50de28c04
Add abc9_ops -prep_holes
2019-12-30 18:00:49 -08:00
Eddie Hung
16c4ec7eda
Add abc9_ops -prep_dff
2019-12-30 16:36:33 -08:00
Eddie Hung
88b9c8d46d
Restore count_outputs, move process check to abc
2019-12-30 16:29:08 -08:00
Eddie Hung
dbffbeef5c
Fix struct name
2019-12-30 16:21:20 -08:00
Eddie Hung
7649ec72c9
Merge remote-tracking branch 'origin/xaig_dff' into eddie/abc9_refactor
2019-12-30 16:20:58 -08:00
Eddie Hung
4c3f517425
Remove delay targets doc
2019-12-30 16:11:42 -08:00
Eddie Hung
658f424d7d
Merge remote-tracking branch 'origin/master' into eddie/abc9_refactor
2019-12-30 16:01:38 -08:00
Eddie Hung
0735572934
write_xaiger to use scratchpad for stats; cleanup abc9
2019-12-30 15:35:33 -08:00
Eddie Hung
22fe931c86
Grammar
2019-12-30 15:07:15 -08:00
Eddie Hung
405e974fe5
Merge remote-tracking branch 'origin/master' into xaig_dff
2019-12-30 14:31:42 -08:00
Eddie Hung
d7ada66497
Add "synth_xilinx -dff" option, cleanup abc9
2019-12-30 14:13:16 -08:00
Eddie Hung
566d9fb77f
Revert "ABC to call retime all the time"
...
This reverts commit 9aa94370a5
.
2019-12-30 13:28:29 -08:00
Eddie Hung
52a27700e2
Grammar
2019-12-30 12:26:39 -08:00
Eddie Hung
f348ffa44d
abc9_techmap -> _map; called from abc9 script pass along with abc9_ops
2019-12-28 05:07:46 -08:00
Eddie Hung
ec25394808
Rename abc9.cc -> abc9_techmap.cc
2019-12-28 03:16:28 -08:00
Marcin Kościelnicki
a24596def3
iopadmap: Emit tristate buffers with const OE for some edge cases.
2019-12-25 17:37:58 +01:00
Eddie Hung
509070f82f
Disable clock domain partitioning in Yosys pass, let ABC do it
2019-12-23 08:36:20 -08:00
Eddie Hung
1ea1e8e54f
Merge remote-tracking branch 'origin/master' into xaig_dff
2019-12-20 13:56:13 -08:00
Eddie Hung
979bf36fb0
Split into $__ABC9_ASYNC[01], do not add cell->type to clkdomain_t
2019-12-19 11:23:41 -08:00
Eddie Hung
3b559de6e9
Interpret "abc9 -lut" as lut string only if [0-9:]
2019-12-18 12:21:12 -08:00
Eddie Hung
c9c77a90b3
Remove &verify -s
2019-12-17 16:11:54 -08:00
Eddie Hung
b1b99e421e
Use pool<> instead of std::set<> to preserver ordering
2019-12-17 16:10:40 -08:00
N. Engelhardt
c8bc1793a4
check scratchpad variable abc9.scriptfile
2019-12-17 19:39:55 +01:00
Eddie Hung
d9bf7061cd
Put $__ABC9_{FF_,ASYNC} into same clock domain as abc9_flop
2019-12-16 16:49:48 -08:00
N. Engelhardt
91f427d719
check scratchpad variables for custom abc scripts
2019-12-13 12:54:52 +01:00
Eddie Hung
abf99d4dae
tribuf: set scratchpad boolean 'tribuf.added_something'
2019-12-12 14:32:29 -08:00
Eddie Hung
a46a7e8a67
Merge remote-tracking branch 'origin/master' into xaig_dff
2019-12-06 23:22:52 -08:00
Eddie Hung
ab667d3d47
Call abc9 with "&write -n", and parse_xaiger() to cope
2019-12-06 16:35:57 -08:00
Eddie Hung
fce527f4f7
Fix abc9 re-integration, remove abc9_control_wire, use cell->type as
...
as part of clock domain for mergeability class
2019-12-06 16:20:18 -08:00
Eddie Hung
01a3cc29ba
abc9 to do clock partitioning again
2019-12-05 17:26:22 -08:00
Marcin Kościelnicki
2abe38e73e
iopadmap: Refactor and fix tristate buffer mapping. ( #1527 )
...
The previous code for rerouting wires when inserting tristate buffers
was overcomplicated and didn't handle all cases correctly (in
particular, only cell connections were rewired — internal connections
were not).
2019-12-04 08:44:08 +01:00
Eddie Hung
d66d06b91d
Add assertion
2019-12-03 19:21:42 -08:00
Eddie Hung
a181ff66d3
Add abc9_init wire, attach to abc9_flop cell
2019-12-03 18:47:09 -08:00
Eddie Hung
6398b7c17c
Cleanup
2019-12-01 23:43:28 -08:00
David Shah
e9ce4e658b
abc9: Fix breaking of SCCs
...
Signed-off-by: David Shah <dave@ds0.me>
2019-12-01 20:44:56 +00:00
Eddie Hung
6831510f5b
Fix debug
2019-11-25 12:59:34 -08:00
Eddie Hung
d087024caf
Merge remote-tracking branch 'origin/master' into xaig_dff
2019-11-25 12:42:09 -08:00
Eddie Hung
180cb39395
abc9 to contain time call
2019-11-25 12:35:57 -08:00
Eddie Hung
f50b6422b0
abc9 to no longer to clock partitioning, operate on whole modules only
2019-11-25 12:35:38 -08:00
Marcin Kościelnicki
6cdea425b8
clkbufmap: Add support for inverters in clock path.
2019-11-25 20:40:39 +01:00
Eddie Hung
bf1167bc64
Conditioning abc9 on POs not accurate due to cells
2019-11-23 10:26:55 -08:00
Eddie Hung
1851f4b488
Merge remote-tracking branch 'origin/eddie/clkpart' into xaig_dff
2019-11-22 23:01:18 -08:00
Eddie Hung
900c806d4e
Move clkpart into passes/hierarchy
2019-11-22 17:25:53 -08:00
Eddie Hung
bf7d36627e
Merge remote-tracking branch 'origin/eddie/clkpart' into xaig_dff
2019-11-22 17:00:35 -08:00
Eddie Hung
95af8f56e4
Only action if there is more than one clock domain
2019-11-22 17:00:11 -08:00
Eddie Hung
00d76f6cc4
Replace TODO
2019-11-22 16:58:08 -08:00
Eddie Hung
698854955c
Merge branch 'eddie/clkpart' into xaig_dff
2019-11-22 15:41:48 -08:00
Eddie Hung
84153288bb
Brackets
2019-11-22 15:41:34 -08:00
Eddie Hung
3df191cec5
Entry in Makefile.inc
2019-11-22 15:41:23 -08:00
Eddie Hung
bd56161775
Merge branch 'eddie/clkpart' into xaig_dff
2019-11-22 15:38:48 -08:00
Eddie Hung
856a3dc98d
New 'clkpart' to {,un}partition design according to clock/enable
2019-11-22 15:35:51 -08:00
Eddie Hung
c4ec42ac38
When expanding upwards, do not capture $__ABC9_{FF,ASYNC}_
...
Since they should be captured downwards from the owning flop
2019-11-21 16:17:03 -08:00
Eddie Hung
729c6b93e8
endomain -> ctrldomain
2019-11-20 14:32:01 -08:00
Eddie Hung
09ee96e8c2
Merge remote-tracking branch 'origin/master' into xaig_dff
2019-11-19 15:40:39 -08:00
Marcin Kościelnicki
38e72d6e13
Fix #1496 .
2019-11-18 04:16:48 +01:00
whitequark
c68722818a
flowmap: when doing mincut, ensure source is always in X, not X̅.
...
Fixes #1475 .
2019-11-12 00:15:43 +00:00
whitequark
eef32195bd
flowmap: don't break if that creates a k+2 (and larger) LUT either.
...
Fixes #1405 .
2019-11-11 23:13:00 +00:00
Eddie Hung
2cb2116b4c
Use "abc9_period" attribute for delay target
2019-10-07 15:03:44 -07:00
Eddie Hung
3879ca1398
Do not require changes to cells_sim.v; try and work out comb model
2019-10-05 22:55:18 -07:00
Eddie Hung
a5ac33f230
Merge branch 'master' into eddie/abc_to_abc9
2019-10-04 17:53:20 -07:00
Eddie Hung
f0cadb0de8
Fix from merge
2019-10-04 17:52:19 -07:00
Eddie Hung
bbc0e06af3
Merge remote-tracking branch 'origin/master' into xaig_dff
2019-10-04 17:39:08 -07:00
Eddie Hung
0acc51c3d8
Add temporary `abc9 -nomfs` and use for `synth_xilinx -abc9`
2019-10-04 17:35:43 -07:00
Eddie Hung
7959e9d6b2
Fix merge issues
2019-10-04 17:21:14 -07:00
Eddie Hung
7a45cd5856
Merge remote-tracking branch 'origin/eddie/abc_to_abc9' into xaig_dff
2019-10-04 16:58:55 -07:00
Eddie Hung
aae2b9fd9c
Rename abc_* names/attributes to more precisely be abc9_*
2019-10-04 11:04:10 -07:00
Eddie Hung
549d6ea467
Merge remote-tracking branch 'origin/master' into xaig_dff
2019-10-03 10:55:23 -07:00
Clifford Wolf
0e05424885
Merge pull request #1422 from YosysHQ/eddie/aigmap_select
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Add -select option to aigmap
2019-10-03 11:54:04 +02:00
Eddie Hung
265a655ef9
Also rename cells with _TECHMAP_REPLACE_. prefix, as per @cliffordwolf
2019-10-02 12:43:35 -07:00
Eddie Hung
edc3780723
techmap wires named _TECHMAP_REPLACE_.<identifier> to create alias
2019-09-30 17:20:12 -07:00
Eddie Hung
1b96d29174
No need to punch ports at all
2019-09-30 17:02:20 -07:00
Eddie Hung
390b960c8c
Resolve FIXME on calling proc just once
2019-09-30 16:37:29 -07:00
Eddie Hung
e529872b01
Remove need for $currQ port connection
2019-09-30 16:33:40 -07:00
Eddie Hung
f2f19df2d4
Add -select option to aigmap
2019-09-30 15:26:29 -07:00
Eddie Hung
e0aa772663
Add comment
2019-09-30 15:19:02 -07:00
Eddie Hung
a6994c5f16
scc call on active module module only, plus cleanup
2019-09-30 12:57:19 -07:00
Eddie Hung
8684b58bed
Merge remote-tracking branch 'origin/master' into xaig_dff
2019-09-30 12:29:35 -07:00
Miodrag Milanović
0d27ffd4e6
Merge pull request #1416 from YosysHQ/mmicko/frontend_binary_in
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Open aig frontend as binary file
2019-09-30 17:49:23 +02:00
Eddie Hung
1123c09588
Merge remote-tracking branch 'origin/master' into xaig_dff
2019-09-29 19:39:12 -07:00
Eddie Hung
8474c5b366
Merge pull request #1359 from YosysHQ/xc7dsp
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DSP inference for Xilinx (improved for ice40, initial support for ecp5)
2019-09-29 11:26:22 -07:00
Eddie Hung
5a4011e8c9
Fix "scc" call inside abc9 to consider all wires
2019-09-29 09:58:00 -07:00
Miodrag Milanovic
3f70c1fd26
Open aig frontend as binary file
2019-09-29 13:22:11 +02:00
Eddie Hung
79b6edb639
Big rework; flop info now mostly in cells_sim.v
2019-09-28 23:48:17 -07:00
Eddie Hung
313d2478e9
Split ABC9 based on clocking only, add "abc_mergeability" attr for en
2019-09-27 18:41:04 -07:00
Eddie Hung
fe722b737c
Add -select option to aigmap
2019-09-27 17:44:01 -07:00
Eddie Hung
8f5710c464
Merge remote-tracking branch 'origin/master' into xaig_dff
2019-09-27 15:14:31 -07:00
Marcin Kościelnicki
fd0e3a2c43
Fix _TECHMAP_REMOVEINIT_ handling.
...
Previously, this wire was handled in the code that populated the "do or
do not" techmap cache, resulting in init value removal being performed
only for the first use of a given template.
Fixes the problem identified in #1396 .
2019-09-27 18:34:12 +02:00
Eddie Hung
44374b1b2b
"abc_padding" attr for blackbox outputs that were padded, remove them later
2019-09-23 21:58:40 -07:00
Eddie Hung
ec08a031b5
Revert abc9.cc
2019-09-20 17:52:23 -07:00
Eddie Hung
72ce06909e
Trim mismatched connection to be same (smallest) size
2019-09-20 17:51:36 -07:00
Eddie Hung
567e5f0aa7
Fix first testcase in #1391
2019-09-20 17:51:27 -07:00
Clifford Wolf
b76fac3ac3
Add techmap_autopurge attribute, fixes #1381
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-09-19 20:00:52 +02:00
Marcin Kościelnicki
c9f9518de4
Added extractinv pass
2019-09-19 04:02:48 +02:00
Eddie Hung
9a73adde50
Explicitly order function arguments
2019-09-13 16:18:05 -07:00
Marcin Kościelnicki
f72765090c
Add -match-init option to dff2dffs.
2019-09-11 19:38:20 +02:00
Marcin Kościelnicki
a82e8df7d3
techmap: Add support for extracting init values of ports
2019-09-07 16:30:43 +02:00
Eddie Hung
903cd58acf
Merge pull request #1312 from YosysHQ/xaig_arrival
...
Allow arrival times of sequential outputs to be specified to abc9
2019-09-05 12:00:23 -07:00
Clifford Wolf
30f1ac7ce9
Rename conflicting wires on flatten/techmap, add "hierconn" attribute, fixes #1220
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-09-05 13:51:53 +02:00
Clifford Wolf
694a8f75cf
Add flatten handling of pre-existing wires as created by interfaces, fixes #1145
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-09-05 13:30:58 +02:00
Eddie Hung
c7f1ccbcb0
Merge remote-tracking branch 'origin/master' into xaig_arrival
2019-08-30 12:28:35 -07:00
Eddie Hung
999fb33fd0
Merge pull request #1340 from YosysHQ/eddie/abc_no_clean
...
abc9 to not call "clean" at end of run (often called outside)
2019-08-30 12:27:09 -07:00
Eddie Hung
f0fef90e9d
Merge remote-tracking branch 'origin/master' into xaig_arrival
2019-08-30 10:30:46 -07:00
Eddie Hung
6e475484b2
Merge remote-tracking branch 'origin/master' into eddie/xilinx_srl
2019-08-30 09:37:32 -07:00
Eddie Hung
18cabe9370
Output has priority over input when stitching in abc9
2019-08-29 17:24:03 -07:00
Eddie Hung
3e0f73c3df
abc9 to not call "clean" at end of run (often called outside)
2019-08-29 12:12:59 -07:00
Eddie Hung
1467761060
Fix typo that's gone unnoticed for 5 months!?!
2019-08-29 10:33:28 -07:00
Eddie Hung
c4e5310823
Use a dummy box file if none specified
2019-08-28 20:58:55 -07:00
Eddie Hung
1b08f861b6
Merge branch 'eddie/xilinx_srl' into xaig_arrival
2019-08-28 15:31:48 -07:00
Eddie Hung
8d820a9884
Merge remote-tracking branch 'origin/master' into xaig_arrival
2019-08-28 15:19:10 -07:00
Eddie Hung
ba5d81c7f1
Merge remote-tracking branch 'origin/master' into eddie/xilinx_srl
2019-08-28 09:21:03 -07:00
Clifford Wolf
47ffbf554e
Fix typo
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-08-28 10:06:42 +02:00
Clifford Wolf
0fda0e821c
Add "paramap" pass
...
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-08-28 10:03:27 +02:00
Marcin Kościelnicki
5fb4b12cb5
improve clkbuf_inhibit propagation upwards through hierarchy
2019-08-27 17:26:47 +02:00
Eddie Hung
48c424e45b
Cleanup
2019-08-23 13:46:05 -07:00
Eddie Hung
619f2414e5
clkbufmap to only check clkbuf_inhibit if no selection given
2019-08-23 11:14:42 -07:00
Eddie Hung
4d89c3f468
Review comment from @cliffordwolf
2019-08-23 10:03:41 -07:00
Eddie Hung
6872805a3e
Merge remote-tracking branch 'origin/master' into mwk/xilinx_bufgmap
2019-08-23 10:00:50 -07:00
Eddie Hung
53fed4f7e9
Actually, there might not be any harm in updating sigmap...
2019-08-22 16:16:56 -07:00
Eddie Hung
cfafd360d5
Add comment as per @cliffordwolf
2019-08-22 16:16:56 -07:00
Eddie Hung
8691596d19
Revert "Try way that doesn't involve creating a new wire"
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This reverts commit 2f427acc9e
.
2019-08-22 16:16:34 -07:00
Eddie Hung
5ff75b1cdc
Try way that doesn't involve creating a new wire
2019-08-22 16:16:34 -07:00
Eddie Hung
e1fff34dde
If d_bit already in sigbit_chain_next, create extra wire
2019-08-22 16:16:34 -07:00
Eddie Hung
36d94caec1
Remove `shregmap -tech xilinx` additions
2019-08-22 11:22:09 -07:00
Eddie Hung
affe9c9c1a
Merge branch 'eddie/fix_techmap' into xaig_arrival
2019-08-20 20:06:47 -07:00
Eddie Hung
fe61dcce8b
Grammar
2019-08-20 20:05:51 -07:00
Eddie Hung
193eae0c84
techmap -max_iter to apply to each module individually
2019-08-20 19:50:20 -07:00
Eddie Hung
57493e328a
techmap -max_iter to apply to each module individually
2019-08-20 19:48:16 -07:00
Eddie Hung
f1a206ba03
Revert "Remove sequential extension"
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This reverts commit 091bf4a18b
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2019-08-20 18:17:14 -07:00
Eddie Hung
091bf4a18b
Remove sequential extension
2019-08-20 18:16:37 -07:00
Eddie Hung
fad15d276d
retime_mode -> dff_mode
2019-08-20 18:08:58 -07:00
Eddie Hung
505d062daf
Fix use of {CLK,EN}_POLARITY, also add a FIXME
2019-08-20 13:33:31 -07:00
Eddie Hung
c4d4c6db3f
Merge remote-tracking branch 'origin/master' into xaig_dff
2019-08-20 12:00:12 -07:00
Eddie Hung
14c03861b6
Merge pull request #1304 from YosysHQ/eddie/abc9_refactor
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Refactor abc9 to use port attributes, not module attributes
2019-08-20 11:59:31 -07:00
Eddie Hung
1f03154a0c
Merge remote-tracking branch 'origin/master' into xaig_dff
2019-08-19 15:19:32 -07:00
Eddie Hung
e29df7d5fa
Remove debug
2019-08-19 12:44:43 -07:00
Eddie Hung
91687d3fea
Add (* abc_arrival *) attribute
2019-08-19 12:33:24 -07:00
Eddie Hung
ba2261e21a
Move from cell attr to module attr
2019-08-19 11:18:33 -07:00
Eddie Hung
7e010834eb
Fix typo
2019-08-19 10:41:18 -07:00
Eddie Hung
2f4e0a5388
Merge remote-tracking branch 'origin/master' into xaig_dff
2019-08-19 10:07:27 -07:00
Eddie Hung
d81a090d89
Unify abc_carry_{in,out} into abc_carry and use port dir, as @mithro
2019-08-19 09:56:17 -07:00
Eddie Hung
e301440a0b
Use attributes instead of params
2019-08-19 09:51:49 -07:00
Eddie Hung
9bfe924e17
Set abc_flop and use it in toposort
2019-08-19 09:40:01 -07:00
Clifford Wolf
2a78a1fd00
Merge pull request #1283 from YosysHQ/clifford/fix1255
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Fix various NDEBUG compiler warnings
2019-08-17 15:07:16 +02:00
Clifford Wolf
8915f496d9
Merge pull request #1300 from YosysHQ/eddie/cleanup2
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Use ID::{A,B,Y,keep,blackbox,whitebox} instead of ID()
2019-08-17 15:01:31 +02:00
Eddie Hung
24c934f1af
Merge branch 'eddie/abc9_refactor' into xaig_dff
2019-08-16 16:51:22 -07:00
Eddie Hung
5abe133323
Use ID()
2019-08-16 16:38:49 -07:00