This reverts commit 047b1a8fc2.
Commit 047b1a8fc2 ("target/image: zero-initialize ELF segments
up to p_memsz") breaks the backward compatibility introducing some
problem:
- an empty bss segment with paddr in SRAM gets zero filled at load
but does not survive after a reset, causing verify to fail;
- an empty bss segment with paddr in FLASH causes excessive flash
usage, which can exceed flash size (causing error) and makes
flash aging faster.
Revert it while looking for a better implementation.
Change-Id: Iaaf926dafce46a220a5bbe20c8576eb449996d76
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reported-by: Marian Buschsieweke <marian.buschsieweke@ovgu.de>
Reviewed-on: https://review.openocd.org/c/openocd/+/7658
Reviewed-by: Bohdan Tymkiv <bohdan200@gmail.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-by: Nemui Trinomius <nemuisan_kawausogasuki@live.jp>
Reviewed-by: Peter Collingbourne <pcc@google.com>
Tested-by: jenkins
This way if you connect to a running target, before it's hit a breakpoint,
then when it does hit the breakpoint OpenOCD will catch it.
Change-Id: I6f1e5f169fa385f46759015786e664693c3872e4
Signed-off-by: Tim Newsome <tim@sifive.com>
Poll failure just means poll failed. It's safer to assume the target is
still running, because then if it is running and subsequently halts we can
relay this to gdb correctly. We can't do the other way around, because once
gdb thinks the target has halted, it can't deal with it spontaneously
running.
Change-Id: Idb56137f1d6baa9afc1b0e55e4a48f407b8ebe83
Signed-off-by: Tim Newsome <tim@sifive.com>
When a DM was powered down, we end up in examine() again, and clearly if
the DM was powered down we need to invalidate that cache.
Change-Id: I5eb6a289939f313e06c09cac22245db083026aa3
Signed-off-by: Tim Newsome <tim@sifive.com>
The error state is sticky, so this has to be done to recover.
Change-Id: I589f3cdab0f2351fd25f89951830cbc16c39bd93
Signed-off-by: Tim Newsome <tim@sifive.com>
When a DMI operation does not succeed (either because of a timeout
or an error), the specification says that the error in the `op`
field is sticky and needs to cleared by writing `dmireset` in `dtmcs`.
This is already done for timeouts in increase_dmi_busy_delay
but not for errors.
Change-Id: I7c5f27a5cf145511a1a8b64a45a586521e1cbe41
Signed-off-by: Amaury Pouly <amaury.pouly@lowrisc.org>
Reviewed-on: https://review.openocd.org/c/openocd/+/7688
Tested-by: jenkins
Reviewed-by: Tim Newsome <tim@sifive.com>
Reviewed-by: Jan Matyas <jan.matyas@codasip.com>
This commit introduces a new function, which can be used to reduce number
of register accesses.
Change-Id: I125809726eb7797b11121175c3ad66bedb66dd0d
Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
Since writing a register can make some GPRs dirty (e.g. S0, S1), registers
should be flushed in reverse order, so GPRs are flushed last.
Change-Id: Ice352a4df4ae064619c0f9905db634a7b57e4711
Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
The struct containing SWD and JTAG operations are declared as
extern in the C file.
Mode them in include file arm_adi_v5.h to silent 'sparse' error
for global variable definition without declaration in an include
file.
Change-Id: I59088512c052d5a120c38404a882ed512a68ca02
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7675
Tested-by: jenkins
The internal variable 'gdb_actual_connections' is used by log and
by semihosting to determine if there are active GDB connections.
Keep the variable local in server's code and only export its value
through a dedicated function.
This solves the issue detected by 'parse' of the variable defined
as global but not declared in any include file.
Change-Id: I6e14f4cb1097787404094636f8a2a291340222dd
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7673
Tested-by: jenkins
The static analyser 'sparse' complains, while compiling a target's
file, that the struct target_type is declared in the file as non
static, but it is not exposed through an include file.
The message is:
warning: symbol 'XXX' was not declared. Should it be static?
Move the list of target_type's declaration in target_type.h
While there, fix a name clash in stm8.c
Change-Id: Ia9c681e0825cfd04d509616dbc04a0cf4944f379
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7659
Tested-by: jenkins
In case in the future I have the same idea of optimizing progbuf writes
again.
Change-Id: Ie383487691cceeff75e2c22f4c85fc1fe4873937
Signed-off-by: Tim Newsome <tim@sifive.com>
Small cleanup in target.c to get rid of few upstream differences:
- removed a pointless check for `reg->exists` - already checked
few lines above
- unify one log message with what's in upstream
Change-Id: I3fd761157382670611fa90de84e2dfc90192f473
Signed-off-by: Jan Matyas <jan.matyas@codasip.com>
While there, add the missing .usage field and move in target.c the
enum nvp_assert.
Change-Id: Ia4f2f962887b5a35faeaa4eae128fa2865569b24
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7559
Tested-by: jenkins
For some trivial case only, replace calls to jim-nvp with calls
to the new OpenOCD nvp.
Change-Id: Ifd9aff32b67748af8ab808e6a6b6e64f5271b888
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7553
Tested-by: jenkins
New gcc does not understand that the variable 'restore_ms' is set
to 'true' only when the variable 'ms' is assigned in
static int xtensa_write_dirty_registers(...)
{
xtensa_reg_val_t ms;
bool restore_ms = false;
...
if (...) {
ms = regval;
restore_ms = true;
...
}
...
if (restore_ms) {
USE(ms);
}
...
}
and complains about possible use of uninitialized variable 'ms'.
Sadly initialize 'ms' to zero to hide this false positive.
Change-Id: I1fb3949070c8abbf4aa45a740f0ca2fdb753d4fa
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7681
Reviewed-by: Erhan Kurubas <erhan.kurubas@espressif.com>
Reviewed-by: Ian Thompson <ianst@cadence.com>
Tested-by: jenkins
Current code tests a function pointer against a numeric value that
is the same enum type as returned by the pointed function.
Clearly the author was willing to call the function and check its
returned value.
Fix the check by calling the function.
Detected through 'sparse' tool.
Change-Id: I27d18d26c2c797160a397daa32835c199014b70b
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Checkpatch-ignore: GIT_COMMIT_ID
Fixes: 237e894805 ("reworked etm/etb into a generic etm part with trace capture")
Reviewed-on: https://review.openocd.org/c/openocd/+/7599
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Let source file to include its file .h to validate the exported
prototypes.
Detected through 'sparse' tool.
Change-Id: I8ae2f8f1fdaea5683e157247463533b17237e464
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7602
Tested-by: jenkins
On 32 bit hosts, gcc should consider constants without suffix as
32 bits values.
Use the suffix 'ULL' to guarantee it is a 64 bit.
Detected through 'sparse' tool.
Change-Id: I205ca986968fef9a536f87492d1f6c80e41829f3
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7601
Tested-by: jenkins
It looks like a false positive.
Scan-build considers as possible to:
- have list_empty() return false;
- list_for_each_safe() to not execute any loop, thus not assigning
a non-NULL value to 'block';
- the NULL pointer 'block' is passed to list_del().
This is not possible because with list_empty(), the loop runs at
least once.
Rewrite the function to simplify the code and making it easier for
scan-build to check it.
This also drops an incorrect use of list_for_each_safe(), where
the 'safe' version was not required.
Change-Id: Ia8b1d221cf9df73db1196e3f51986023dcaf78eb
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Fixes: 8d1dcf293a ("target/espressif: add application tracing functionality over JTAG")
Reviewed-on: https://review.openocd.org/c/openocd/+/7608
Reviewed-by: Erhan Kurubas <erhan.kurubas@espressif.com>
Tested-by: jenkins
When the function xtensa_queue_dbg_reg_read() returns error, the
array 'tmp' remains not initialized and scan-build complains while
computing buf_get_u32() that:
Result of operation is garbage or undefined
Check the returned value of xtensa_queue_dbg_reg_read() and
propagate it.
Change-Id: If0aaad068b97ef0a76560e262d16429afd469585
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Fixes: 8d1dcf293a ("target/espressif: add application tracing functionality over JTAG")
Reviewed-on: https://review.openocd.org/c/openocd/+/7607
Tested-by: jenkins
Reviewed-by: Erhan Kurubas <erhan.kurubas@espressif.com>
Below warnings are fixed.
1- A function declaration without a prototype is deprecated in all
versions of C [-Werror,-Wstrict-prototypes]
2- error: variable set but not used [-Werror,-Wunused-but-set-variable]
Signed-off-by: Erhan Kurubas <erhan.kurubas@espressif.com>
Change-Id: I1cf14b8e5e3e732ebc9cacc4b1cb9009276a8ea9
Reviewed-on: https://review.openocd.org/c/openocd/+/7569
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
ARMv8-R platforms are similar to ARMv8-A regarding
JTAG and most cpu registers. ARMv8-R doesn't has MMU
but has MPU instead.
ARMv8-R platforms can be AArch32 only such as Cortex-R52,
or AArch64 capable like Cortex-R82.
Signed-off-by: Julien Massot <julien.massot@iot.bzh>
Change-Id: Ib086f71685d1e3704b396d478ae9399dd8a391e1
Reviewed-on: https://review.openocd.org/c/openocd/+/6843
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
This feature allows to transfer arbitrary data between host and
ESP32 via JTAG.
The main use cases:
1- Collecting application specific data
2- Lightweight logging to the host
3- System behaviour analysis with SEGGER SystemView
4- Source code coverage
Signed-off-by: Erhan Kurubas <erhan.kurubas@espressif.com>
Change-Id: I95dee00ac22891fa326915a3fcac3c088cbb2afc
Reviewed-on: https://review.openocd.org/c/openocd/+/7163
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
If hart can't change pc (e.g. it is running), resume command should
fail.
Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
Change-Id: I14627366d574d806ea16262b7d305d8161f8bcc2
Add the fast read method to speed up flash verification
after programming. Works the same as fast write already
implemented.
Signed-off-by: François LEGAL <devel@thom.fr.eu.org>
Change-Id: I74611a3542a88212f0483ec8ee368aba3d1f03c7
Reviewed-on: https://review.openocd.org/c/openocd/+/7564
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
The condition to check if the workspace area (used by actual MIPS code
executed on target) and data area (sandbox to put data to be read/written
to/from flash) is wrong, thus preventing the use of FAST_* commands to
program/verify FLASH.
Signed-off-by: François LEGAL <devel@thom.fr.eu.org>
Change-Id: Ic68424b7f42d44e550433a120093db5e7980fd56
Reviewed-on: https://review.openocd.org/c/openocd/+/7563
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Since the deletion of `-rtos hwthread`, there is no need to treat harts
with `-rtos` specified differently on reset.
Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
Change-Id: I88a9129936b5172bb7479dfa1255e29ff460c054
No other attempt is made at doing anything hypervisor-specific. Are
other things necessary?
Change-Id: Ib65f114888840cf0878f9bfe028c9a42b436aa3f
Signed-off-by: Tim Newsome <tim@sifive.com>
This also fixes an incorrect return ERROR_xx from a jim command,
propagated from return value of rtos_smp_init().
Change-Id: Icf4893c00aabd8fadd60077c5e8a2e926f687518
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7511
Tested-by: jenkins
Print one entry per line.
While there add the mandatory 'usage' field.
Change-Id: Ia832684817f3bdbfa4cb943cd97e3f9fb2605902
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7510
Tested-by: jenkins
Print one entry per line.
While there add the mandatory 'usage' field.
Change-Id: I135556e12154e33fdbd0f71d89f6fe37c69813b7
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7509
Tested-by: jenkins
While there add the mandatory 'usage' field.
Change-Id: I3e5b826ca58f7ade30a443ada0cb4a9cd9ea35c2
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7508
Tested-by: jenkins
While there add the mandatory 'usage' field.
Change-Id: I5389881dac25877dc32930ec36ee546e48ecc14d
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7507
Tested-by: jenkins
While there, fix typo on 'exceeds'.
In a following patch, the output could be formatted and split in N
values per line to make it easier to read by humans.
Change-Id: I295111a80934393011e46311f6cf6c13f2bdc0a3
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7503
Tested-by: jenkins
While there, format in a human readable way the output list by
using one line per tpiu name.
Change-Id: I937c92b6c1e92509cf8aa96be1517a51bc363600
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7501
Tested-by: jenkins
While there, format in a human readable way the output list by
using one line per dap name.
Change-Id: I24a47350105b90db15808c61790f05d807120739
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7498
Tested-by: jenkins
While there, format in a human readable way the output list by
using one line per cti name.
Change-Id: I6d4870ee512fe7e6935d73355c2377ad805ccc3b
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7492
Tested-by: jenkins
While there, add a check for target halted and check the number of
parameters accordingly to the command name.
Change-Id: I9e8bb109c35039561997d14782fac682267aee65
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7491
Tested-by: jenkins
This also fixes an incorrect return ERROR_TARGET_NOT_HALTED from a
jim command.
Change-Id: I99a02a21bedb64e60944e295c7cf24356e07be60
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7490
Tested-by: jenkins
The code for JTAG WAIT recovery did not handle DP_SELECT
endianness.
While on it, mark missing ADIv6 DP SELECT1 handling as TODO.
Change-Id: I44f3bc8fc9fd2483c0293b6d4f2c51a60ca01873
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/7540
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
The multidrop SWD is also supported.
Change-Id: I9fefc54fc9d40a75194285cd6e0f10c5c347d9b6
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/7537
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
The value returned by target_get_gdb_arch() is something specific for GDB.
There could be several variants of the same CPU.
If we start implementing all the variants, checking the string value,
could become incorrect.
It's better to check for xtensa->common_magic == XTENSA_COMMON_MAGIC
Signed-off-by: Erhan Kurubas <erhan.kurubas@espressif.com>
Change-Id: I20f3fdced176c3b9ab00f889743161ecad7280f9
Reviewed-on: https://review.openocd.org/c/openocd/+/7536
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Icount triggers don't have a maskmax field at all. This is a cut and
paste error.
Change-Id: I001b3d41bf683599706dba713f7be475e8dd1668
Signed-off-by: Tim Newsome <tim@sifive.com>
When permission bits R, W, and X in PTE all three are zero,
the PTE is a pointter to the next level of the page table;
otherwise, it is a leaf PTE. Here PTE_W is missed.
Change-Id: I82a4cc4e64280f0fcad75b20e51b617520aff29b
Signed-off-by: panciyan <panciyan@eswincomputing.com>
- Manual integration of NX support from xt0.2 release
- No new clang static analysis warnings
Signed-off-by: Ian Thompson <ianst@cadence.com>
Change-Id: I95b51ccc83e56c0d4dbf09e01969ed6a4a93d497
Reviewed-on: https://review.openocd.org/c/openocd/+/7356
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
We were previously not zero-initializing ELF segments between p_filesz
and p_memsz (aka BSS). However, this may be necessary depending on the
user's application. Therefore, start doing so.
Change-Id: I5a743390069583aca7ee276f53afeccf2cac0855
Signed-off-by: Peter Collingbourne <pcc@google.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7513
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Untested, because I don't have a target that implements this.
Change-Id: Iff82c124e7caf8e8960a9da62d8e727afb2c6b8a
Signed-off-by: Tim Newsome <tim@sifive.com>
It is possible for triggers of the same type to support different match
field values, so it is needed to try all the triggers, not just the
first one.
Fixes issue #788.
Signed-off-by: Evgeniy Naydanov evgeniy.naydanov@syntacore.com
Change-Id: I4c9fbc98bae7259377456d9ad8e770232724a592
We should avoid using x16~x31 register in program buffer because there
are no such general purpose registers in RVE(Embedded) extension.
For targets that support rvE, when the parameter increment=0
and count>1 of the read_memory_progbuf function, openocd will cause
an error due to the use of the s2 register.
For example:
{Command} {riscv repeat_read} count address [size=4]
Change-Id: I8b74dcc15cd00a400f2f1354c577a82132394435
Signed-off-by: Hang Xu <xuhang@eswincomputing.com>
* target/riscv: hide_csrs configuration option
This option allows users to mark certain CSRs as hidden so they could be
expluded from *reg* output and target.xml
Change-Id: Iddf8456cd3901f572f8590329ebba5229974d24a
* Update doc/openocd.texi
Co-authored-by: Jan Matyas <50193733+JanMatCodasip@users.noreply.github.com>
Signed-off-by: Anatoly Parshintsev <114445139+aap-sc@users.noreply.github.com>
* Update src/target/riscv/riscv.c
Co-authored-by: Jan Matyas <50193733+JanMatCodasip@users.noreply.github.com>
Signed-off-by: Anatoly Parshintsev <114445139+aap-sc@users.noreply.github.com>
---------
Signed-off-by: Anatoly Parshintsev <114445139+aap-sc@users.noreply.github.com>
Co-authored-by: Jan Matyas <50193733+JanMatCodasip@users.noreply.github.com>
* Add command "exec_progbuf"
Command "exec_progbuf" allows to execute a user-specified sequence
of instructions using the program buffer.
Change-Id: If3b9614129d0b6fcbc33fade29d3d60b35e52f98
Signed-off-by: Jan Matyas <jan.matyas@codasip.com>
* Updated the doc:
- Minor reword and reorder of the sentences.
- Added information about C-instructions in progbuf.
- Fixed a typo (per the review).
- Added examples.
Change-Id: I88c9a3ff3c6b60614be7eafd3a6f21be722a77b7
Signed-off-by: Jan Matyas <jan.matyas@codasip.com>
* Cosmetic changes
Change-Id: I7135c9f435f640e189c7d7922a2702814dfd595f
Signed-off-by: Jan Matyas <jan.matyas@codasip.com>
---------
Signed-off-by: Jan Matyas <jan.matyas@codasip.com>
Co-authored-by: Jan Matyas <jan.matyas@codasip.com>
Also refactor shared code for clearing itrigger/etrigger/icount.
Change-Id: Iac2e756332c89d2ed43435391e3c097abc825255
Signed-off-by: Tim Newsome <tim@sifive.com>
Because riscv_program_exec() tries to add an instruction every time
through.
This would cause an error accessing vector registers where VL > 14(?).
Change-Id: Ie676ca8c9be786b46aa2a4b4028ac8b27f7a4b40
Signed-off-by: Tim Newsome <tim@sifive.com>
This should make vector accesses work on 64-bit harts that implement
Zve32*. There doesn't appear to be any way to easily determine what vsew
values are allowed, so try and notice the failure.
Change-Id: Ide0722d0d67da402a4fbe88163830094e46beb84
Signed-off-by: Tim Newsome <tim@sifive.com>
While there, fix some coding style error and remove the now unused
function jim_arc_read_reg_name_field() and the macro
JIM_CHECK_RETVAL().
Change-Id: I140b4b929978b2936f2310e0b7d1735ba726c517
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7426
Tested-by: jenkins
Reviewed-by: Evgeniy Didin <didin@synopsys.com>
Use a COMMAND_HELPER() to avoid memory leaks when the helper
COMMAND_PARSE_NUMBER() returns due to an error.
While there:
- fix potential SIGSEGV due to dereference 'type' before checking
it's not NULL;
- fix an incorrect NUL byte termination while copying to
type->data_type.id and to bitfields[cur_field].name;
- fix some coding style error;
- remove the now unused function jim_arc_read_reg_type_field().
Change-Id: I7158fd93b5d4742f11654b8ae4a7abd409ad06e2
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7425
Tested-by: jenkins
Reviewed-by: Evgeniy Didin <didin@synopsys.com>
Use a COMMAND_HELPER() to avoid memory leaks when the helper
COMMAND_PARSE_NUMBER() returns due to an error.
While there:
- fix potential SIGSEGV due to dereference 'type' before checking
it's not NULL;
- fix an incorrect NUL byte termination while copying to
type->data_type.id and to bitfields[cur_field].name;
- fix some coding style error.
Change-Id: Ide4cbc829871a6a523026ccc0d3100dadc2afd06
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7424
Tested-by: jenkins
Reviewed-by: Evgeniy Didin <didin@synopsys.com>
The command is specified through COMMAND_HANDLER. It should not
return JIM_OK / JIM_ERR.
Change-Id: I56666414d49b0298ecc23ec7ef30c77e1e27afa8
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7413
Tested-by: jenkins
Reviewed-by: Evgeniy Didin <didin@synopsys.com>
Also drop arc_cmd_jim_get_uint32() that is now unused.
Change-Id: Ic26c3f008376db3f01215bf736fca736dd1c1a4f
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7412
Tested-by: jenkins
Reviewed-by: Evgeniy Didin <didin@synopsys.com>
This also fixes several incorrect return ERROR_xxx from a jim
command.
Change-Id: I34fe3552d3dc344eac67bf504c5d5709b707fdfd
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7411
Tested-by: jenkins
Reviewed-by: Evgeniy Didin <didin@synopsys.com>
This also fixes an incorrect return ERROR_OK from a jim command.
Change-Id: I72a522645f62b99b313573c8bad6d4f674c5ae53
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7410
Tested-by: jenkins
Reviewed-by: Evgeniy Didin <didin@synopsys.com>
This also fixes an incorrect return ERROR_OK from a jim command.
Change-Id: I1f9cf5d1dfa38b8a06042b5f54209e6ee2fc4e0e
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7409
Tested-by: jenkins
Reviewed-by: Evgeniy Didin <didin@synopsys.com>
This also fixes an incorrect return ERROR_OK from a jim command.
Change-Id: Iab9bc7c25181341a632f608a8ef2d8b0bea72520
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7408
Tested-by: jenkins
Reviewed-by: Evgeniy Didin <didin@synopsys.com>
This also fixes an incorrect return ERROR_OK from a jim command.
Change-Id: I3c51355e7e05965327ce819a3114e370f2de5249
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7407
Tested-by: jenkins
Reviewed-by: Evgeniy Didin <didin@synopsys.com>
OpenOCD currently uses improper "fence" instruction:
"FENCE" opcode with empty predecessor and successor sets.
Such instruction has no effect and is reserved for future use
as a HINT instruction (RISC-V Unprivileged ISA spec V20191213,
section 2.9).
This patch fixes it by using the proper "fence rw,rw"
instruction.
Change-Id: Ia2a66059009153efef27279410850ddfd73dae38
Signed-off-by: Jan Matyas <jan.matyas@codasip.com>
This generalizes the little endian CRC32 function used in the OR1K
target and moves it to a common helper, so that other places do not need
to reinvent the wheel. It is directly used in the OR1K target.
Change-Id: I0e55340281a5bfd80669bb1994f3a96fecc1248a
Signed-off-by: Marian Buschsieweke <marian.buschsieweke@ovgu.de>
Reviewed-on: https://review.openocd.org/c/openocd/+/7415
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
The org.gnu.gdb.arm.m-system GDB feature defines the name in lowercase
letters.[1] Not adhering to the definition can cause issues with tools
interacting with the GDB which expect the correct casing.
[1]: https://sourceware.org/gdb/onlinedocs/gdb/ARM-Features.html
Change-Id: I0b6584a78f86b053947d79686baad5dac3ec4a00
Signed-off-by: Boris-Chengbiao Zhou <bobo1239@web.de>
Reviewed-on: https://review.openocd.org/c/openocd/+/7292
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Cortex-M support for SMP multicore targets.
This SMP implementation unlike older ones does not act
on the first halted target found. It polls targets
until a SMP group is finished and stores eventual
'halted' events instead of emitting them. As soon as polling
of a group is done, poll proceeds with SMP related tasks.
This approach improves detection of a reason why debug
stopped - a correct reason is detected for all targets,
not only for the first found.
Drawback: SMP target group should be defined in the same
order as the targets were defined.
Obsolete gdb 'J' packet/smp_gdb command core switching is not implemented,
use with rtos hwthread.
Only one core is resumed if debug_execution is requested.
Some ideas taken from Graham Sanderson's [4936]
and src/target/aarch64.c
Added error checking of armv7m_restore_context().
Change-Id: I60f5b79e74b624dc2b5835ff10e38ac2ccb23792
Link: [4936]: target/cortex_m: Add smp support for Cortex M | https://review.openocd.org/c/openocd/+/4936
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/7239
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
When pointer authentication is enabled, some upper bits of the link
register (LR[63:VA_SIZE]) are used to store a signature. Therefore, GDB
need to remove the signature to get backtraces.
GDB has support of pointer authentication. When pointer authenticaion is
enabled, GDB requests 8-bytes mask to the target to remove the
signature. mask[63:VA_SIZE] should be all set and mask[VA_SIZE-1:0]
should be all cleared. GDB removes the signature by addr&~mask or
addr|mask.
I added a feature to provide the mask for pointer authentication.
Signed-off-by: Koudai Iwahori <koudai@google.com>
Change-Id: I56fbbf9cc23619b6536ecd326f350c8bf137f322
Reviewed-on: https://review.openocd.org/c/openocd/+/7248
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
In any case flag will be set as examined.
Signed-off-by: Erhan Kurubas <erhan.kurubas@espressif.com>
Change-Id: I5177ee656f726a807269e2f4725223f50e49e855
Reviewed-on: https://review.openocd.org/c/openocd/+/7231
Tested-by: jenkins
Reviewed-by: Ian Thompson <ianst@cadence.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
The target nds32 and its companion adapter aice have not received
any real improvement since 2013.
It has been hard to keep them aligned during the evolution of
OpenOCD code, with no way for maintainers to really check if they
are still working.
No real documentation is present for them in OpenOCD.
The nds32 code triggers ~50 errors/warnings with scan-build.
The arch nds32 has been dropped from Linux kernel v5.18-rc1.
For all the reasons above, this code has been deprecated with
commit 2e5df83de7 ("nds32: deprecate it, together with aice
adapter driver") and tagged to be dropped before v0.13.0.
Let it r.i.p. in OpenOCD git history.
While there, drop from checkpatch list the camelcase symbols that
where only used in this code.
Change-Id: Ide52a217f2228e9da2f1cc5036c48f3536f26952
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7382
Tested-by: jenkins
This patch fixes two corner-cases of finding RTT control block.
The first one is when there was a partial match (even single byte) at
the end of loaded buffer (uint8_t buf[1024]), but this was not part of
full match. In that case `cb_offset` was not updated correctly and the
returned `*address` was lower by the legth of the partial match. In case
of searched 'SEGGER RTT' (the default control block ID) string, it was
enough to match `buf[1023] == 'S'`, which is quite likely to happen, and
the `*address` was offset by 1 (e.g. it was 0x20000fff instead of
0x20010000).
Updating (or even maintaining) `cb_offset` is not needed, as start
address of control block can be calculated based on memory address that
was loaded into `uint8_t buf[1024]`, the offset within this buffer and
the length of expected string.
The second issue is when control block is prepended with a byte that
matches first ID character, e.g. there is `SEGGER RTT` control block ID
is prepended by another `S`, making memory contents be `SSEGGER RTT`. In
that case there was no match found.
Fix that issue by making sure that tested byte is always compared with
first byte of expected control block ID.
While at it, change names of local variables to better describe their
meaning.
Signed-off-by: Marcin Niestroj <m.niestroj@emb.dev>
Change-Id: I12aa6e202bf12bedcbb888ab595751a2a2518a24
Reviewed-on: https://review.openocd.org/c/openocd/+/7429
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
This command is supposed to be a start at a compliance test for system
bus access. It doesn't pass against spike because it doesn't handle all
cases where the interface might be busy. It's not documented. As far as
I know nobody uses it.
So delete 400 lines of code instead of trying to fix it.
Change-Id: Ib94f2acb95a48f7c07d4f44206ff7373b03857f3
Signed-off-by: Tim Newsome <tim@sifive.com>
Signed-off-by: Tim Newsome <tim@sifive.com>
This lets the user set an itrigger trigger, which doesn't fit in the
normal breakpoint abstraction.
This implementation only allows control of a single itrigger. Hardware
could support more than one, and that may be useful to catch different
interrupts in different execution modes. But it would make the code/UI
more complex and it feels like an unlikely use case.
Change-Id: I76c88636ee73d4bd298b2bd1435cb5d052e86c91
Signed-off-by: Tim Newsome <tim@sifive.com>
Cores armv8m, e.g. Cortex-M33, can be instantiated without the
optional Security Extension.
In this case, the secure registers are not present and when GDB
try accessing them it triggers a set of errors.
For armv8m cores without security extension, don't provide to GDB
the description of the secure registers.
Change-Id: I254478a4cf883e85b786df3f62c726b2f40d88d9
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reported-by: Torbjörn SVENSSON <torbjorn.svensson@foss.st.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7402
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
When target is stopped in WFI/WFE or is in an infinite loop, the
sampled PC will always return the same value.
Command 'profile' requires that distance between min and max PC
should be at least 2, which is not the case for constant PC, and
incorrectly enforces the check through as assert().
Move the code that reads the optional parameters 'start' and 'end'
and check the gap 'end - start' before running the profile.
For self-computed min and max, increase max (or decrease min) to
match the required constraint.
Drop the assert().
Change-Id: I2be8df8568ce8c889923888c492e4f7ce354b16b
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Fixes: https://sourceforge.net/p/openocd/tickets/370/
Reviewed-on: https://review.openocd.org/c/openocd/+/7400
Tested-by: jenkins
The implementation of command 'monitor profile' has few
issues:
- the address_space is a signed int, so cannot wrap-around on
space over INT_MAX;
- max address is incremented without check for overflow;
- assert() used on errors instead of returning error codes;
- only handles 32 bits PC;
- output file created and left empty on error.
This patch fixes the first two issues, as a wider fix would be too
invasive and should be postponed in a following series.
Change-Id: Id8ead3f6db0fd5730682a0d1638f11836d06a632
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Fixes: https://sourceforge.net/p/openocd/tickets/370/
Reviewed-on: https://review.openocd.org/c/openocd/+/7394
Tested-by: jenkins
Clang complains about the variable 'orig_dfsr' that can be used
uninitialized both in cortex_a_read_cpu_memory() and in
cortex_a_write_cpu_memory().
The issue is caused by an incorrect error path that used to jump
through 'goto out'. The code after the label 'out' is specific to
handle the case of an error during memory R/W; it is incorrect to
jump there to handle an error during the initialization that
precedes the memory R/W.
Replace the 'goto out' with 'return retval'.
Remove the label 'out' that is now unused.
Change-Id: Ib4b140221d1c1b63419de109579bde8b63fc2e8c
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7393
Tested-by: jenkins
Commit 35a503b08d ("arm_adi_v5: add ap refcount and add get/put
around ap use") modifies the examine functions of mem_ap, cortex_m,
cortex_a and aarch64 by calling dap_put_ap() and then looking again
for the mem-ap and calling dap_get_ap().
This causes an issue if the system is irresponsive and the examine
fails and left the AP pointer to NULL. If the system was already
examined the NULL pointer will cause a SIGSEGV.
Commit b6dad912b8 ("target/cortex_m: prevent segmentation fault
in cortex_m_poll()") proposes a fix for one specific case and only
on cortex_m.
Modify all the examine functions by skipping look-up for the AP if
it was already set in a previous examine; the target's AP is not
supposed to change during runtime.
Remove the partial fix for cortex_m as it is not needed anymore.
Change-Id: I806ec3b1b02fcc76e141c8dd3a65044febbf0a8c
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Fixes: 35a503b08d ("arm_adi_v5: add ap refcount and add get/put around ap use")
Reviewed-on: https://review.openocd.org/c/openocd/+/7392
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Without the fix, will see "Can not find free FP Comparator" error log
Change-Id: Id0d91cc02b7055e44d27507f9c05ccd48ff49838
Signed-off-by: Nima Palizban <n.palizban@gmail.com>
Fixes: fb43f1ff4e (target: Rework 'set' variable of break-/watchpoints)
Reviewed-on: https://review.openocd.org/c/openocd/+/7389
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
If multiple targets are specified as -rtos <rtos_type>, the
rtos_update_threads was called only if the last target was specified as
rtos, which is inconsistent with other checks of whether or not smp target
is an rtos one.
Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
Change-Id: Ie52bc6b6c8f841d31b9590fcbc44e985d3cba0eb
Reviewed-on: https://review.openocd.org/c/openocd/+/7244
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Then also set it when we resume in examine(), which doesn't use the full
abstractions because not all required data structures are filled out
yet.
Hopefully fixes#749.
Change-Id: I0c6ab16da1f035ca2fbdb9f7be1462d44ddce3a0
Signed-off-by: Tim Newsome <tim@sifive.com>
Exit the loop when no harts are running, instead of when at least one
hart has halted.
Change-Id: Ia69b626bf1fee4034bd5ccc800a651bfe0e53685
Signed-off-by: Tim Newsome <tim@sifive.com>
It used to set all states to halted, but that's not right for harts that
are now unavailable. (It might be possible to call poll() at the right
time instead of duplicating some of its code, but I didn't see an easy
way to do that. The real requirement is that target->state is set to
TARGET_UNAVAILABLE before TARGET_EVENT_HALTED is is sent in
halt_finish(), because that's what triggers hwthread_update_threads(),
which must know about unavailable harts so they can be hidden from gdb.
Change-Id: I0a0bbdd4ec9ff8c9898e04045b84e1d2512c9336
Signed-off-by: Tim Newsome <tim@sifive.com>
There used to be entirely separate code paths depending on whether we're
in SMP mode or not. Now they're both the same.
Change-Id: I8f46295e4bc005f441af0c03d4f608c53b8a6586
Signed-off-by: Tim Newsome <tim@sifive.com>
This ensures that we populate the register cache and set target->state.
Some RISC-V changes had upset the balance.
Change-Id: I47fbf8ebd8fe39fa5b752212080f87e3b7e6e5e5
Signed-off-by: Tim Newsome <tim@sifive.com>
We don't correctly write it, so we shouldn't expect it to read back the
same value. Fixes hardware breakpoints on mcontrol triggers.
Change-Id: Ie5e445060ec9c8887af933fd8887e57308330f09
Indicate to the JTAG driver that it does not need
to read and return the DR register value after scanning the
JTAG chain.
riscv_batch_run(), calls jtag_add_dr_scan() to schedule a
DR scan operation. Eventually, this will result in the JTAG
driver performing a JTAG scan to write to or read from DR.
The decision on whether to write to and/or read from DR
register is determined by the second parameter to
jtag_add_dr_scan(), i.e. a "struct scan_field".
Of particular interest here is if
batch->fields[i]->in_value is not NULL, the JTAG developer
must return the DR value collected from the JTAG scan
operation.
When creating the DR scan operation instruction with
riscv_batch_add_dmi_write(), batch->fields[i]->in_value points
to a location in batch->data_in buffer,
meaning batch->field[i]->in_value is not NULL, and the JTAG
developer must therefore read and return the DR value collected.
The returning of the DR value is redundant in a write
operation.
This patch set batch->fields[i]->in_value to NULL to indicate
the DR value need not be returned. This allows the JTAG
developer to optimize away any code associated with returning
the DR value.
Normally, the extra work to return the DR value is negligible.
However, in one usecase it introduces significant delays
In this use case a JTAG driver forwards
all JTAG scan to a server on a network. If the server has to
return the DR value, it has to perform the JTAG scan before
replying to the JTAG driver, and only then the JTAG driver
can send the next JTAG scan operation. However, if there is
no need to return the DR value, the server can
acknowledge the JTAG operation request immediately,thus
signalling to the JTAG driver that it is free to send the next
JTAG scan operation. At the same time of receiving the second
JTAG operation the server will process the original JTAG scan.
This saves time and mitigates network delay. Also, not having
to include the DR value in resulting in smaller reply packet
from server to JTAG driver and save on network traffic.
This doubles download speeds to spike using remote bitbang.
Change-Id: Ibb37c3e32af0cc7006b22b8c4e1f31ed29c21d0f
Signed-off-by: Ooi, Cinly <cinly.ooi@intel.com>
Signed-off-by: Tim Newsome <tim@sifive.com>
Signed-off-by: Ooi, Cinly <cinly.ooi@intel.com>
Signed-off-by: Tim Newsome <tim@sifive.com>
Co-authored-by: Ooi, Cinly <cinly.ooi@intel.com>
It's only used to change what callback events are generated, and there
are none anyway. (That's probably a bug, but since 0.11 is so rare I'm
not going to worry about it.)
Fixes#757.
Change-Id: I5b5df3a9bec927fb0368304229533e2875a83f6b
Signed-off-by: Tim Newsome <tim@sifive.com>
breakpoint_add should use rtos only if request is done by gdb.
Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
Change-Id: I779d1a905c6a3640869dca162e3cc001919e8f42
Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
armv7m_start_algorithm() saves register values to arch_info->context.
armv7m_wait_algorithm() restores register values from arch_info->context.
Exclude registers with flag exist = false from both loops.
While on it refactor the register restore: introduce 'struct reg' pointer
and dereference it instead of numerous accesses by a full path
from armv7m pointer.
Change-Id: I1600084db84809ee13bcf8e7828b79f8c9ff9077
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/7276
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
On some boards there is a HW bug: if fp unit is disabled (fs in mstatus
set to 0), accessing any fp register results in a hang (any abstract
command timeouts, untill the board is rebooted).
Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
Change-Id: I0c0d1033889f15dcc326c4078bf9cbb5a8558565
Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
Clang get confused by initializing the array uint16_t lock_word[],
casting it to (uint8_t *), then accessing the second element of
the uint8_t pointer.
src/target/dsp5680xx.c:2046:41: warning: The left operand of '<<'
is a garbage value [core.UndefinedBinaryOperatorResult]
uint16_t tmp = (buffer[0] | (buffer[1] << 8));
~~~~~~~~~ ^
Fix it by replacing the array with a single uint16_t.
The code is still depending on host endianness; no fix for this is
proposed.
Change-Id: I16dfd60cab117dd145aeecf10d9593574ff233a2
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7302
Tested-by: jenkins
The function esirisc_jtag_recv() can be called with argument
num_in_fields = 0, for example as consequence of calling
esirisc_jtag_continue().
In this case, num_in_bytes is zero and the allocation of the
variable-length array 'r' requires size zero.
src/target/esirisc_jtag.c:133:2: warning: Declared variable-length
array (VLA) has zero size [core.VLASize]
uint8_t r[num_in_bytes * 2];
^~~~~~~~~ ~~~~~~~~~~~~~~~~
Fix it by forcing size one when num_in_bytes is zero.
Change-Id: Id764c7b5ec4f5b3c18c7da650bbff39fc98ed049
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7301
Tested-by: jenkins
Clang assumes that size could assume a value that is not 1 nor 2
nor 4. In such condition the buffer in t is allocated (size != 1)
and not initialized. This triggers an error:
src/target/openrisc/or1k_du_adv.c:655:14: warning: 2nd function
call argument is an uninitialized value [core.CallAndMessage]
crc_calc = adbg_compute_crc(crc_calc, data[i], 8);
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Add the default case to cover other values of size.
After this fix, clang still complains on the same line, this time
misunderstanding the limits of the loop and considering that
buf_bswap16() only swaps the first 16 bits, thus passing not
initialized value data[2] to adbg_compute_crc()
Replace malloc() with calloc() to silent it.
Change-Id: I358d7fb2ebefd69255670641bd435b770762a301
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7300
Tested-by: jenkins
E.g. the Zve* vector extensions have all the same registers as the full
V extension, but leaves misa.V clear.
Change-Id: Ib08c3612c52bb3a6b074d9431e3396c8f2f0ff27
Signed-off-by: Tim Newsome <tim@sifive.com>
Signed-off-by: Tim Newsome <tim@sifive.com>
Prep work for handling unavailable harts.
Change-Id: I9c00ed4cdad8edeaa5a13fbec7f88f40d8af9028
Signed-off-by: Tim Newsome <tim@sifive.com>
Signed-off-by: Tim Newsome <tim@sifive.com>
* Use match field for trigger
The watchpoint cannot capture all data modifications only through the
trigger of ANY SIZE and EQUAL, and an error will occur. This patch
accommodates watchpoints by adding more types of matches
Change-Id: I5c3c908dbd49ca47755b06f5cdbe451be3a81c8b
Signed-off-by: Xiang W <wxjstz@126.com>
Signed-off-by: Tim Newsome <tim@sifive.com>
* Update src/target/riscv/riscv.c
Co-authored-by: Jan Matyas <50193733+JanMatCodasip@users.noreply.github.com>
Signed-off-by: Xiang W <wxjstz@126.com>
* Update src/target/riscv/riscv.c
Co-authored-by: Jan Matyas <50193733+JanMatCodasip@users.noreply.github.com>
Signed-off-by: Xiang W <wxjstz@126.com>
* Update src/target/riscv/riscv.c
Co-authored-by: Jan Matyas <50193733+JanMatCodasip@users.noreply.github.com>
Signed-off-by: Xiang W <wxjstz@126.com>
* Update src/target/riscv/riscv.c
Co-authored-by: Jan Matyas <50193733+JanMatCodasip@users.noreply.github.com>
Signed-off-by: Xiang W <wxjstz@126.com>
* Update src/target/riscv/riscv.c
Co-authored-by: Jan Matyas <50193733+JanMatCodasip@users.noreply.github.com>
Signed-off-by: Xiang W <wxjstz@126.com>
* Update src/target/riscv/riscv.c
Co-authored-by: Jan Matyas <50193733+JanMatCodasip@users.noreply.github.com>
Signed-off-by: Xiang W <wxjstz@126.com>
* Update src/target/riscv/riscv.c
Change-Id: I3670347c4b00bf508373f7cc2f4950cbc09d6e2a
Signed-off-by: Xiang W <wxjstz@126.com>
* Add variable type trigger support
Change-Id: I60922c5f98574040b9a160e2aa0355871a581fe1
Signed-off-by: Xiang W <wxjstz@126.com>
* remove trailing whitespace
Change-Id: I168812e12b459ae3c4b3017c27a9b897e65d9f84
Signed-off-by: Xiang W <wxjstz@126.com>
* update triggers enumerate
Change-Id: I23a66afb0f772934b8911b522d0e4f116917519f
Signed-off-by: Xiang W <wxjstz@126.com>
Signed-off-by: Xiang W <wxjstz@126.com>
Signed-off-by: Tim Newsome <tim@sifive.com>
Co-authored-by: Jan Matyas <50193733+JanMatCodasip@users.noreply.github.com>
* target/riscv: Deal with DMI busy in sample_memory_bus_v1()
Change-Id: I810a4c4b7f02cb40ea99b7a500dce23c1bbd9231
Signed-off-by: Tim Newsome <tim@sifive.com>
* Comment code more clearly.
Co-authored-by: Jan Matyas <50193733+JanMatCodasip@users.noreply.github.com>
Signed-off-by: Tim Newsome <tim@sifive.com>
* Remove extra tab
Co-authored-by: Jan Matyas <50193733+JanMatCodasip@users.noreply.github.com>
Signed-off-by: Tim Newsome <tim@sifive.com>
Signed-off-by: Tim Newsome <tim@sifive.com>
Co-authored-by: Jan Matyas <50193733+JanMatCodasip@users.noreply.github.com>
* target/riscv Fix dm->current_hartid corruption on hartsellen discovery
Change-Id: Iec969df2675b608365eda2c3a83a4185752430f2
Signed-off-by: Charles Papon <charles.papon.90@gmail.com>
* target/riscv Ensure HART_INDEX_DIRTY does not have side effects
Change-Id: Ie89c94d97cd4f15c1be0327fddff75beea6ae027
Signed-off-by: Charles Papon <charles.papon.90@gmail.com>
Signed-off-by: Charles Papon <charles.papon.90@gmail.com>
This is added for future RISC-V changes. The RISC-V debug interface can
explicitly tell a debugger when a hart is unavailable. This is used for
instance when that hart is powered down (or yet to be powered up out of
reset).
Change-Id: I8a062d59eea1e5b3c788281a75159592db024683
Signed-off-by: Tim Newsome <tim@sifive.com>
`xtensa_do_step` is invoked from `xtensa_prepare_resume` to silently
step over BP/WP before resuming.
For example; in the case of WPs (DEBUGCAUSE_DB), in the current
implementation `xtensa_do_step` will generate one more
`TARGET_EVENT_HALTED` after the original one caused by WP itself.
This patch moves the halted event cb call after
the step is done successfully.
Signed-off-by: Erhan Kurubas <erhan.kurubas@espressif.com>
Change-Id: I9048e14fb316dc124847a42cfaefb1f76b5ce53e
Reviewed-on: https://review.openocd.org/c/openocd/+/7274
Tested-by: jenkins
Reviewed-by: Ian Thompson <ianst@cadence.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
- Fix the declaration of riscv command 'set_mem_access'.
- Remove non existing riscv command 'set_scratch_ram'.
- Add riscv commands 'info', 'reset_delays'; copy the description
from the 'help' text.
- Don't add riscv commands 'set_prefer_sba' and 'test_sba_config_reg'
as they are marked as deprecated.
- Ensure that 'test_sba_config_reg' prints a deprecation warning
when used.
Change-Id: I39dc3aec4e7f13b69ac19685f1b593790acdde83
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Signed-off-by: Jan Matyas <matyas@codasip.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7268
Reviewed-by: Tim Newsome <tim@sifive.com>
Tested-by: jenkins
* target/riscv: Correctly set target->state in deassert_reset
This bug didn't lead to problems, but it would with some upcoming
changes.
Change-Id: I552acbae9977150c4c9e573f8852033bc80fcebb
Signed-off-by: Tim Newsome <tim@sifive.com>
* Keep debug_reason in sync with state
Co-authored-by: Jan Matyas <50193733+JanMatCodasip@users.noreply.github.com>
Signed-off-by: Tim Newsome <tim@sifive.com>
Signed-off-by: Tim Newsome <tim@sifive.com>
Co-authored-by: Jan Matyas <50193733+JanMatCodasip@users.noreply.github.com>
Currently 'number' field is zero in the register cache and
this causes an issue on `rtos get_thread_reg_list` calls.
Signed-off-by: Erhan Kurubas <erhan.kurubas@espressif.com>
Change-Id: Iaef11e01f55d012969bbc1933f82847d5e02fec5
Reviewed-on: https://review.openocd.org/c/openocd/+/7246
Tested-by: jenkins
Reviewed-by: Ian Thompson <ianst@cadence.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
* [riscv] step operation handler should respect handle_breakpoints parameter
When step operation is requested the OpenOCD frontend (like gdb server
or TCL server) has an option to control how existing breakpoints are
handled upon step.
Some OpenOCD frontends (like gdbserver) may choose to disable special
handling of existing breakpoints - thus handle_breakpoints is set to 0,
while others (like TCL server) expect target handler to temporary
disable the matching breakpoint to allow the step operation to complete
successfully.
In the current implementation handle_breakpoints parameter was ignored
by target-specific handler. Thus, the following sequence of commands:
```
halt
bp <current_pc> 4
step
```
Resulted in *step* operation to not change PC because of bp match.
This commit addresses this issue.
* Adjusted calls to logging facilities (addressed review comments)
Co-authored-by: Tim Newsome <tim@sifive.com>
Signed-off-by: Anatoly Parshintsev <114445139+aap-sc@users.noreply.github.com>
Signed-off-by: Anatoly Parshintsev <114445139+aap-sc@users.noreply.github.com>
Co-authored-by: Tim Newsome <tim@sifive.com>
* Properly track selecting multiple harts at once.
use_hasel is a bit of a hack.
Change-Id: Ia589ebc16bca32038d915df9988361b88e940917
Signed-off-by: Tim Newsome <tim@sifive.com>
* Clarifying comment.
Co-authored-by: Jan Matyas <50193733+JanMatCodasip@users.noreply.github.com>
Signed-off-by: Tim Newsome <tim@sifive.com>
* Rename set_hartsel to set_dmcontrol_hartsel
Change-Id: Iab28531281aa6fc604ec7d34974ed444ea9ea850
* Make set_dmcontrol_hartsel() more idiomatic.
Change-Id: I56a885043c515359e33b9c8a03aed637c81d1486
* Use constant for multiple harts instead of -1.
Change-Id: Iefeaf74202f2b4918d21f15f7ff7ca514175b8fb
Signed-off-by: Tim Newsome <tim@sifive.com>
Signed-off-by: Tim Newsome <tim@sifive.com>
Co-authored-by: Jan Matyas <50193733+JanMatCodasip@users.noreply.github.com>
Also add an early exit for if any harts are unavailable.
Change-Id: I0875d4d213c9faf87b219d8d57e440881366c8f8
Signed-off-by: Tim Newsome <tim@sifive.com>
arp_waitstate will not work on not-examined state
Change-Id: I56c3e1c7e63af108e4ed1dbacebb567f9bf46264
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/7230
Tested-by: jenkins
Reviewed-by: Erwan Gouriou
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
An application often idling in real sleep mode may make a Cortex-M target
hard to access as CPU clock are gated and debug requests are responded
by WAIT ack.
Try to examine the target under reset as the last resort.
Change-Id: I7c3de39fb1e6c23b76e2a0a85ab75f23aac94c4d
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/7229
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
An application often idling in real sleep mode may make a Cortex-M target
hard to access as CPU clock are gated and debug requests are responded
by WAIT ack.
Try to examine the target under reset as the last resort.
Change-Id: Ife875a966a838c37dde987bc584ad0a1f4d020d6
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/7228
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
After merging [1] 'reset halt' does not work on not responding Cortex-M.
Relax the examined tests and try to set vector catch VC_CORERESET
if debug_ap is available.
While on it add an info about examination state to debug logs.
Fixes: [1] commit 98d9f1168c ("target: reset target examined flag if target::examine() fails")
Change-Id: Ie2e018610026180af5997d70231061a275f05c76
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/6745
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
For 64-bit TAR setup, if 'tar_valid == false' perform the upper 32-bit
write even if the cached copy matches the upper TAR value to be written.
Signed-off-by: Daniel Goehring <dgoehrin@os.amperecomputing.com>
Change-Id: I320377dc90a9d1d7b64cbb281b2527e56c7621ee
Reviewed-on: https://review.openocd.org/c/openocd/+/7245
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
Read values must be at albuff so that can be copied to buffer
on function exit.
Signed-off-by: Erhan Kurubas <erhan.kurubas@espressif.com>
Change-Id: I74a533e8f12f1002ca06a98a7c7cd928552b4cc5
Reviewed-on: https://review.openocd.org/c/openocd/+/7226
Tested-by: jenkins
Reviewed-by: Ian Thompson <ianst@cadence.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Actually they are the base of epc and eps
Signed-off-by: Erhan Kurubas <erhan.kurubas@espressif.com>
Change-Id: I4f43b9609a9929399fb5d3fa0203efc8a98e94c9
Reviewed-on: https://review.openocd.org/c/openocd/+/7227
Tested-by: jenkins
Reviewed-by: Ian Thompson <ianst@cadence.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
armv7m_start_algorithm() stored all non-debug execution
registers from register cache without checking validity.
Check if the register cache is valid.
Try to read from CPU if not valid.
Issue a warning if register read fails.
Change-Id: I365f86d65243230cf521b13909575e5986a87a50
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/7240
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Jonathan Bell <jonathan@raspberrypi.com>
This was used to track which hart a given operation must apply to. But
we already have a target associated with each operation, and from there
we can find the desired hart id. dm013_info_t already tracks
current_hartid (meaning which hart ID is currently selected by the DM).
This makes the code simpler to understand. Also it turns out we don't
need to make sure the correct hart ID is currently selected because
there are only a few real entry points.
Change-Id: Ibe8d5e156523397f245edd6ec0a5df3239b717bf
Signed-off-by: Tim Newsome <tim@sifive.com>
swd_multidrop_select() uses its own retry loop.
If select fails, do_reconnect flag remains set on exit and causes
useless reconnect.
Clear do_reconnect flag in retry loop.
Change-Id: Ie06d6967d7f4a977774c8530bb8d4b3e5ab4f62c
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/7217
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Jonathan Bell <jonathan@raspberrypi.com>
Tested-by: jenkins
Implementation of ADI v6 introduced banking of DP reg 0.
The accompanying change preventing DP SELECT write before
DP IDR read during connect was added to swd_connect_single() only.
Unchanged swd_connect_multidrop() / swd_multidrop_select_inner()
was broken as it emited DP SELECT and put DP to protocol error state.
Copy dap->select handling to swd_multidrop_select_inner().
Fixes: 72fb88613f (adiv6: add low level swd transport)
Change-Id: I514cd6d9ae2ba97ce3657b459df22638c278a0b1
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/7213
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Jonathan Bell <jonathan@raspberrypi.com>
According to RISC-V External Debug Support Version 0.13.2 (paragraph
3.12.6), cmderr field contains a valid value only if busy is 0, so it is
incorrect to analize it on timeout.
Increase "value_buf" size so it can hold a 64-bit number represented
as a string. Previous size could only hold a 32-bit number string.
Signed-off-by: Daniel Goehring <dgoehrin@os.amperecomputing.com>
Change-Id: If6fbc875236e6ddc59522fbc25db0129eb60ee27
Reviewed-on: https://review.openocd.org/c/openocd/+/7221
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Scan-build reports:
Logic error: Uninitialized argument value
riscv.c:2688 2nd function call argument is an uninitialized value
This is a real error cause by running the command "riscv
authdata_write" without arguments. In such case 'value' is not
initialized and is passed to and used by r->authdata_write().
Reorganize the code to:
- detect the correct amount or command's arguments;
- drop the LOG_ERROR() on ERROR_COMMAND_SYNTAX_ERROR;
- drop the 'else' after 'return'.
Change-Id: I62e031220593b8308bc674b753e15d16d4c5c9ac
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7210
Tested-by: jenkins
Reviewed-by: Jan Matyas <matyas@codasip.com>
Reviewed-by: Tim Newsome <tim@sifive.com>
Scan-build reports:
Logic error: Result of operation is garbage or undefined
riscv.c:1614 The result of the left shift is undefined due
to shifting by '4294967281', which is greater or
equal to the width of type 'target_addr_t'
This is a false warning due to clang that considers the impossible
case of 32 bits hart (xlen = 32) in SATP_MODE_SV48 mode
(info->va_bits = 48).
Under such case:
riscv.c:1614 ... ((target_addr_t)1 << (xlen - (info->va_bits - 1))) ...
the shift amount wraps around the unsigned type and assumes the
value 4294967281 (0xfffffff1).
Use assert() to prevent clang from complaining.
Change-Id: I08fdd2a806c350d061641e28cf15a51b397db099
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7209
Reviewed-by: Tim Newsome <tim@sifive.com>
Reviewed-by: Jan Matyas <matyas@codasip.com>
Tested-by: jenkins
Scan-build reports:
Unused code: Dead nested assignment
riscv.c:459 Although the value stored to 'ir_user4_raw' is
used in the enclosing expression, the value is
never actually read from 'ir_user4_raw'
This is caused by the value reassigned in 'ir_user4_raw':
riscv.c:459 ir_user4[3] = (uint8_t)(ir_user4_raw >>= 8);
but never used.
Drop the DIY conversion in favor of h_u32_to_le() that does not
reassign the input value.
Change-Id: Ifad29f4c46d4a2d0a2f5a5c4104d768cc3db2794
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7208
Reviewed-by: Tim Newsome <tim@sifive.com>
Reviewed-by: Jan Matyas <matyas@codasip.com>
Tested-by: jenkins
Scan-build reports:
Unused code: Dead assignment
riscv.c:716 Value stored to 'result' is never read
Remove the initialization of variable 'result'.
Change-Id: Ied67bb4fcfa5bace186522074247ead43a5d5cd5
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7207
Reviewed-by: Tim Newsome <tim@sifive.com>
Reviewed-by: Jan Matyas <matyas@codasip.com>
Tested-by: jenkins
Scan-build reports:
Unused code: Dead initialization
riscv-013.c:2362 Value stored to 'control' during its
initialization is never read
Remove the initialization of variable 'control'.
Change-Id: I548f8175530b9a2aa4c1788549d6467bf9824584
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7206
Reviewed-by: Tim Newsome <tim@sifive.com>
Reviewed-by: Jan Matyas <matyas@codasip.com>
Tested-by: jenkins
Scan-build complains about variable 'sbcs_orig' that can be used
not initialized.
Logic error: Assigned value is garbage or undefined
riscv-013.c:4468 Assigned value is garbage or undefined
This is caused by not checking the return value of the call
riscv-013.c:4466 dmi_read(target, &sbcs_orig, DM_SBCS);
In fact when dmi_read() returns error, the variable 'sbcs_orig' is
not assigned.
Check the returned value.
Change-Id: Ia9032a0229aa243138f95f4e13f765726a4ceae9
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7205
Reviewed-by: Tim Newsome <tim@sifive.com>
Reviewed-by: Jan Matyas <matyas@codasip.com>
Tested-by: jenkins
Scan-build triggers a warning:
Unix API: Allocator sizeof operand mismatch
dsp563xx.c:2143 Result of 'calloc' is converted to a pointer
of type 'uint8_t', which is incompatible with sizeof
operand type 'uint32_t'
It's a false positive because calloc() is properly used in this
case, as the uint8_t array is used in blocks of 4 elements to read
or write uint32_t values.
Either
calloc(sizeof(uint32_t), count);
and
malloc(count * sizeof(uint32_t));
keep triggering the same warning.
Drop the warning by using the constant '4' as size of uint32_t, as
already used few lines below.
Change-Id: I5bb1ece177774eefdc5d9cd049338f8f2be87cd7
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7203
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
With the old checkpatch we cannot use the correct format for the
SPDX tags in the file .c, in fact the C99 comments are not allowed
and we had to use the block comment.
With the new checkpatch, let's switch to the correct SPDX format.
Change created automatically through the command:
sed -i \
's,^/\* *\(SPDX-License-Identifier: .*[^ ]\) *\*/$,// \1,' \
$(find src/ contrib/ -name \*.c)
Change-Id: I6da16506baa7af718947562505dd49606d124171
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7153
Tested-by: jenkins
Resolves issues where registers are accessed when poll() logic is inactive or has not yet been triggered.
Signed-off-by: Ian Thompson <ianst@cadence.com>
Change-Id: If7a4d00938fb188b008325249627f7773c3484c5
Reviewed-on: https://review.openocd.org/c/openocd/+/7197
Tested-by: jenkins
Reviewed-by: Erhan Kurubas <erhan.kurubas@espressif.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Read PS from EPS[debuglevel] during fetch such that it reflects the correct value when read via telnet (not just via gdb_server).
Signed-off-by: Ian Thompson <ianst@cadence.com>
Change-Id: I8504f68989bc6d5fe451a8cb69d01c86f4ec0100
Reviewed-on: https://review.openocd.org/c/openocd/+/7195
Tested-by: jenkins
Reviewed-by: Erhan Kurubas <erhan.kurubas@espressif.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Requested in https://review.openocd.org/c/openocd/+/6964.
I'm making the change here so I have a chance to test it properly before
pushing it upstream.
A nice effect of this change is that we avoid some unnecessary polling
early on when gdb is connecting and we would poll once every time we
send gdb a qXfer packet.
Change-Id: I4bdb9f05839e8c1e01ff6dde49d6589595418095
Signed-off-by: Tim Newsome <tim@sifive.com>
The method soft_reset_halt is optional; no need to add an
empty function.
Remove mips_mips64_soft_reset_halt() and move the TODO comment
in struct target_type.
Change-Id: Id541a75e7a08645568961d59b73a120c2238701f
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7184
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Read buffer is sized for 32-bit APB version of PWRSTAT/PWRCTL registers. Initialize to zero so 8-bit JTAG register mirrors are accurate.
Signed-off-by: Ian Thompson <ianst@cadence.com>
Change-Id: I81310649fa7180893d0188aab3c8a14315aaea0a
Reviewed-on: https://review.openocd.org/c/openocd/+/7183
Tested-by: jenkins
Reviewed-by: Erhan Kurubas <erhan.kurubas@espressif.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Symbols that are not used outside the file should not be exported
and should be declared as static.
Change-Id: Icbe7f7bce287b903edec9dc9db3370722c51fbd5
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7173
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Symbols that are not used outside the file should not be exported
and should be declared as static.
Move the existing comments to the static declarations.
Change-Id: Idf208e3fda4b3f8df789553cf03ebf5f20d811bb
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7170
Reviewed-by: Jan Matyas <matyas@codasip.com>
Reviewed-by: Tim Newsome <tim@sifive.com>
Tested-by: jenkins
Symbols that are not exported should be declared as static.
Change-Id: I2475524f4c14520e3163572560f4a9f276356ed5
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7168
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Symbols that are not exported should be declared as static.
Change-Id: Ieb627f7f896e4663b0d5b18c4ab1853b39d23d03
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7167
Reviewed-by: Erhan Kurubas <erhan.kurubas@espressif.com>
Reviewed-by: Ian Thompson <ianst@cadence.com>
Tested-by: jenkins
Symbols that are not exported should be declared as static.
Change-Id: Ie3bd17535c8cb2a0fec5d3bedfe7de3e0a702613
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7166
Tested-by: jenkins
Reviewed-by: Tim Newsome <tim@sifive.com>
Reviewed-by: Jan Matyas <matyas@codasip.com>
For some configurations, notably on DAP systems, resolve issue where single-stepping does not always transition into the HALTED state.
Signed-off-by: Ian Thompson <ianst@cadence.com>
Change-Id: I053f4eaffad8c3228878ba87580ada640e4bd2fe
Reviewed-on: https://review.openocd.org/c/openocd/+/7150
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
- Enable ADIv5 DAP systems via JTAG or SWD transport
- Select correct PWRCTL/PWRSTAT bits for XDM/APB
Signed-off-by: Ian Thompson <ianst@cadence.com>
Change-Id: I5894210c804f85075da868d0cfc6fb20b589d99f
Reviewed-on: https://review.openocd.org/c/openocd/+/7144
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
We have left the camelcase symbols *xPSR* for some time, to avoid
any conflict with possibly pending patches in gerrit.
With the approaching v0.12.0-rc1, it's time to revisit it.
The patches in gerrit that conflict with this rename are all not
merge-able due to conflicts or due to negative review.
Drop these CamelCase symbols.
Change-Id: Ifbac4c1df9cc55994e024971a2aaebeed2ea4ed3
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7155
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Without the help of checkpatch, some CamelCase symbol passed
through the filter of maintainer's review.
Drop them.
Change-Id: If5fb07b2ffb89e853dd2a61f20d4134aa6e20d24
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Fixes: 48f267d4ad ("flash/stm32l4x: avoid using magic numbers for device ids")
Fixes: 5ab74bde06 ("semihosting: User defined operation, Tcl command exec on host")
Reviewed-on: https://review.openocd.org/c/openocd/+/7154
Tested-by: jenkins
Otherwise OpenOCD simply doesn't work without giving any indication why.
Change-Id: I21703fc1a0d9bed2f59da95f8a8395fe139484a4
Signed-off-by: Tim Newsome <tim@sifive.com>
* Don't read dmcontrol to set hartsel
We already know what dmcontrol should be. This addresses a long-standing
TODO. In a toy test, this reduced the number of scans by 10+%. (Most of
those are probably in poll(), so don't actually affect perceived
performance.)
Change-Id: I18e5ca391f0f5fb35f30d44dfef834e5a66aee20
Signed-off-by: Tim Newsome <tim@sifive.com>
* Make code easier to read
Co-authored-by: Jan Matyas <50193733+JanMatCodasip@users.noreply.github.com>
Signed-off-by: Tim Newsome <tim@sifive.com>
Signed-off-by: Tim Newsome <tim@sifive.com>
Co-authored-by: Jan Matyas <50193733+JanMatCodasip@users.noreply.github.com>
Use indirect enum IDs to access XDM registers in preparation for supporting both NAR (JTAG) and APB (DAP). No new clang static analysis warnings.
Signed-off-by: Ian Thompson <ianst@cadence.com>
Change-Id: I0b742fe4661ff3cf609454b8650493d141a1e1ff
Reviewed-on: https://review.openocd.org/c/openocd/+/7143
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested with an PLUS-F5270 board which uses the MM32F5277E9PV.
Signed-off-by: iysheng <iyysheng@gmail.com>
Change-Id: Icb75ae8337fdc6fa60e39d3d74dd8bc163707bdd
Reviewed-on: https://review.openocd.org/c/openocd/+/7136
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Scan-build of target/xtensa/ has no clang analyzer warnings from xtensa source files.
Signed-off-by: Ian Thompson <ianst@cadence.com>
Change-Id: I11a125c923ece9a6fd0d9ee1698f742f88ee5cab
Reviewed-on: https://review.openocd.org/c/openocd/+/7141
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Hopefully this will be the final version.
Change-Id: Ib2f8cd6f613c5e0f8e8bf7a16c3edbf2d9b439b2
Signed-off-by: Tim Newsome <tim@sifive.com>
Signed-off-by: Tim Newsome <tim@sifive.com>
See https://github.com/riscv/riscv-opcodes/pull/139
Change-Id: I77ae5ab369e6cde26ad44d177dcae38c0fbe08ef
Signed-off-by: Tim Newsome <tim@sifive.com>
Signed-off-by: Tim Newsome <tim@sifive.com>
Fix Unused code Dead assignment at line 657
Fix Memory error Double free at line 2851
Fix Memory error Memory leak at line 2530
Fix error: 'a3' may be used uninitialized at line 758
Fix error: '%04x' directive writing between 4 and 8 bytes
into a region of size 5 at line 2471
Signed-off-by: Erhan Kurubas <erhan.kurubas@espressif.com>
Change-Id: I0382a622bc7c4108a335fd741816577e79240397
Reviewed-on: https://review.openocd.org/c/openocd/+/7137
Tested-by: jenkins
Reviewed-by: Ian Thompson <ianst@cadence.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Generic Xtensa LX support extends the original Espressif/Xtensa
patch-set to support arbitrary Xtensa configurations, as defined in
a core-specific .cfg file. Not yet fully-featured. Additional
functionality to be added:
- Xtensa NX support
- DAP/SWD support
- File-IO support
- Generic Xtensa multi-core support
Valgrind-clean, no new Clang analyzer warnings
Signed-off-by: Ian Thompson <ianst@cadence.com>
Change-Id: I08e7bf8fa57c25b5d0cb75a1aa7a2ac13a380c52
Reviewed-on: https://review.openocd.org/c/openocd/+/7055
Tested-by: jenkins
Reviewed-by: Erhan Kurubas <erhan.kurubas@espressif.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Also used type helper (PRId64) to specify format of int64_t
Signed-off-by: Erhan Kurubas <erhan.kurubas@espressif.com>
Change-Id: I594863eab594aff621c26fefcc69a1872e9730ee
Reviewed-on: https://review.openocd.org/c/openocd/+/7111
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Now we get the license comment on the first line, which is required.
Change-Id: I54414db3c89ee6027e159ce9348459bc923b8595
Signed-off-by: Tim Newsome <tim@sifive.com>
Signed-off-by: Tim Newsome <tim@sifive.com>
Some files have author info some doesn't. For the consistency we removed all.
Signed-off-by: Erhan Kurubas <erhan.kurubas@espressif.com>
Change-Id: Ie6f1ec012302e3a954c75c5106f12820722cb715
Reviewed-on: https://review.openocd.org/c/openocd/+/7104
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
The S_RESET_ST sticky bit is reset after DHCSR read.
It is set at power-on reset and keeps active until the debuger reads DHCSR.
Ignore S_RESET_ST at the very first read after OpenOCD start
and suppress possibly misleading message "external reset detected"
if we cannot guarantee the reset happened recently.
While on it add a TODO comment.
Change-Id: I15217c2ca6f69ac97aff8be86bce67cba94a42cd
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/7109
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Provide a customizable hook for handling target-specific GDB queries
Valgrind-clean, no new Clang analyzer warnings
Signed-off-by: Ian Thompson <ianst@cadence.com>
Change-Id: I684a259ed29f3651cbce668101cff421e522f79e
Reviewed-on: https://review.openocd.org/c/openocd/+/7082
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
The same flag 'jtag_poll' is currently used as local data for the
command 'poll' and to temporarily mask the target polling.
This can cause unexpected behavior if the command 'poll' is
executed while polling is temporarily masked.
Add a new flag 'jtag_poll_en' to hold the temporarily mask
condition and keep 'jtag_poll' for the 'poll' command only.
While there, change the initial assignment of 'jtag_poll' using
the proper boolean value.
Change-Id: I18dcf7c65b07aefadf046caaa2fcd2d74fa6fbae
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7009
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Tested-by: jenkins
This one doesn't have the license in there, which means now it's
acceptable to GPLv2 again.
See https://github.com/riscv/riscv-openocd/pull/711
Change-Id: I8ba27801172ffa955470d2627fa656cad282ee99
Signed-off-by: Tim Newsome <tim@sifive.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7087
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tcl commands 'arm reg', 'arm mcr/mrc' do not work on M-profile based devices.
Isolate them from 'arm core_state' and 'arm disassemble' and do not chain
them from armv7m_command_handlers.
Change-Id: I2c6befdf82575e95cf05ed158ab5e6faa1a182c3
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/7101
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
Tcl command 'arm core_state' was exposed even on Cortex-M devices.
However it returned message "Unsupported Command" without error status
on such device.
Set the only possible arm->core_state ARM_STATE_THUMB in armv7m init.
Block setting core_state to arm on Cortex-M.
Change-Id: I9525553ac8863a6cf77bbacbcd57e354b6cfe1ca
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/7100
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
If a Cortex-M MCU become unresponsive during a debug session and
re-examination fails to find MEM-AP, debug_ap pointer is set to NULL.
Eventual call of cortex_m_poll() dereferences debug_ap.
Check debug_ap validity at the begin of cortex_m_poll().
Change-Id: I9519f48760c91a48a9e5e8c34634d247098cb14a
Fixes: 35a503b08d (arm_adi_v5: add ap refcount and add get/put around ap use)
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/7108
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Just a cosmetic refactoring.
Change-Id: I7fbc05324e346fafc98d1b42691d33d3d8fbd04e
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/7003
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
AARCH64_COMMON_MAGIC was same as CORTEX_A_COMMON_MAGIC, probably copy pasta.
Define unique AARCH64_COMMON_MAGIC
Change-Id: Ie30e0028453a1fce5624ecad9bf73d5ac3791281
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/6997
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Unify common_magic type to unsigned int
Move common_magic to be the first member of the struct
Add unsigned specifier to xxx_COMMON_MAGIC #defines
Change-Id: If961d33232698529514ba3720e04418baf6dc6fe
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/6996
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
The working area allocation routines use 4 byte word alignment.
In the corner case the size of the working area is not aligned,
target_alloc_working_area() of size = target_get_working_area_avail()
will fail because the size gets aligned up and does not fit to the area
which size is aligned down.
Align down the result of target_get_working_area_avail() to cope with that
corner case.
While on it use fancy ALIGN_... macros instead of bitwise and operator.
Change-Id: Ia2a1e861c401c2c78fe6323379a3776fb4f47b06
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/7096
Tested-by: jenkins
Reviewed-by: Erhan Kurubas <erhan.kurubas@espressif.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
If range's upper bound was equal to 2^64 or the range was wrapping around 0
(which is perfectly legal), writes were not performed due to riscv_addr_t
overflow.
Make the main RISC-V structure more compliant with OpenOCD coding style.
Other typedefs remains as is.
Change-Id: I5657ad28fea8108fd66ab27b2dfe1c868dc5805b
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/6998
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Tim Newsome <tim@sifive.com>
We found that the NPCX has an issue with the byte lanes so that non byte
aligned writes aren't working. To overcome this, for byte accesses we
copy the byte to be written to all of the byte lanes.
doc: Document command nu_npcx_quirks
Signed-off-by: benjbender <benjbender@gmail.com>
[Andreas Fritiofson: Squashed commits]
Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Change-Id: I9ef63bf692f4e68f57459e1ec33f3abcbf533cd2
Reviewed-on: https://review.openocd.org/c/openocd/+/6630
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Replace the FSF boilerplate with the SPDX tag.
The SPDX tag on files *.c is incorrect, as it should use the C99
single line comment using '//'. But current checkpatch doesn't
allow C99 comments, so keep using standard C comments, by now.
Change-Id: I255ad17235ff1e01bf0aa4deed4d944e1d693ddb
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7071
Tested-by: jenkins
The SPDX tag is aimed at machine handling and it's thus expected
to be placed in the first line in specific format.
Move the SPDX tag to the first line and fix it where needed.
The SPDX tag on files *.c is incorrect, as it should use the C99
single line comment using '//'. But current checkpatch doesn't
allow C99 comments, so keep using standard C comments, by now.
Change-Id: Ie9a05f530009d482a4116eebd147fd7e1ee3d41e
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7066
Tested-by: jenkins
Few files have the FSF boilerplate without the latest statement on
where to get the GPL license.
Manually replace the FSF boilerplate with the SPDX tag.
While there, reorganize the copyright statement.
The SPDX tag on files *.c is incorrect, as it should use the C99
single line comment using '//'. But current checkpatch doesn't
allow C99 comments, so keep using standard C comments, by now.
Change-Id: I0c908d01c010e24f9c7e94885e7fbed4ecf26a86
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7063
Tested-by: jenkins
Some file miss completely the license tag.
Add the SPDX tag, using the same GPL-2.0-or-later license of the
OpenOCD project.
The SPDX tag on files *.c is incorrect, as it should use the C99
single line comment using '//'. But current checkpatch doesn't
allow C99 comments, so keep using standard C comments, by now.
Change-Id: I1fb51e722232d14f050458a820c3041de3dc9138
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7058
Tested-by: jenkins
SPDX tag is replacing the FSF boilerplate.
For files that have both, remove the FSF boilerplate and keep only
the SPDX tag.
Change-Id: I04c4764d13d4ca92453f30ed16aeae53cd4c3fc8
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7057
Tested-by: jenkins
Add the SPDX tag to makefiles, configuration scripts and tcl files
present in the folders under src/
Change-Id: I1e4552aafe46ef4893d510da9d732c5f181784a4
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7051
Tested-by: jenkins
This one doesn't have the license in there, which means now it's
acceptable to GPLv2 again.
Change-Id: I8ba27801172ffa955470d2627fa656cad282ee99
Signed-off-by: Tim Newsome <tim@sifive.com>
This gets us the new license header, which was requested upstream.
Change-Id: I992b4f3bb230edb9f281e2278dd41c712098ed4c
Signed-off-by: Tim Newsome <tim@sifive.com>
ARM/RISC-V semihosting calls SYS_READ/SYS_WRITE require
inversion of the result value as described in
"Semihosting for AArch32 and AArch64". Prior to
this patch, this was done correctly only if
(semihosting->is_fileio==false).
This patch has been tested with STM32F446.
Change-Id: I1b34c8d8393f7dfa66ee6539904a2eaf8f9154b0
Signed-off-by: Pavel Kirienko <pavel.kirienko@gmail.com>
Fixes: https://sourceforge.net/p/openocd/tickets/232/
Reviewed-on: https://review.openocd.org/c/openocd/+/6803
Tested-by: jenkins
Reviewed-by: Tim Newsome <tim@sifive.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
The variable 'smp_break' is only set and used in case of smp.
But clang cannot track if 'target->smp' get modified between the
set and the use of 'smp_break', so it consider possible to use
'smp_break' uninitialized.
Initialize 'smp_break' to silent clang.
Change-Id: Ifa25a84fe9ffa25b8b58d7920ec77994c3b7ebfe
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Fixes: 77287b8d47 ("target: add Espressif ESP32 basic support")
Reviewed-on: https://review.openocd.org/c/openocd/+/7050
Reviewed-by: Erhan Kurubas <erhan.kurubas@espressif.com>
Tested-by: jenkins
These enum values are useful for the arch level semihosting call handlers.
Currently riscv uses them, we also need similar return codes for the xtensa.
Signed-off-by: Erhan Kurubas <erhan.kurubas@espressif.com>
Change-Id: I8f63749cc203c59b07862f33edf3c393cd7e33a9
Reviewed-on: https://review.openocd.org/c/openocd/+/7039
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Commit b9526f1401 ("semihosting: permit redirection of
semihosting I/O to TCP") introduces a new comparison with NULL.
Remove it.
Change-Id: Ice4333c50d16f7592f0ff86b1640217fa42e34f6
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Fixes: b9526f1401 ("semihosting: permit redirection of semihosting I/O to TCP")
Reviewed-on: https://review.openocd.org/c/openocd/+/7031
Tested-by: jenkins
Commit 6c0151623c ("aarch64: add support for "reset halt"")
introduces the register setting to halt at reset vector, but:
- does not consider the case 'srst_pulls_trst' that makes useless
setting the registers as they will be erased by the pulled trst;
- does not clean sticky errors in case of 'srst_gates_jtag'.
Avoid any register initialization on 'srst_pulls_trst' and move
the cleaning of sticky errors in the common block.
Change-Id: I6f839f06f7b091e234ede31ec18096e51f017bcd
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Fixes: 6c0151623c ("aarch64: add support for "reset halt"")
Reviewed-on: https://review.openocd.org/c/openocd/+/7034
Tested-by: jenkins
Reviewed-by: Christian Hoff <christian.hoff@advantest.com>
Custom user syscalls can be handled with target events in the TCL scripts.
This patch gives another opportunity to handle custom syscalls in the c files.
Besides that some utility functions are also exported for the custom handlers.
Signed-off-by: Erhan Kurubas <erhan.kurubas@espressif.com>
Change-Id: Ice13d527540a0de0b2a8abda912ae3dcff3834b7
Reviewed-on: https://review.openocd.org/c/openocd/+/6889
Tested-by: jenkins
Reviewed-by: Ian Thompson <ianst@cadence.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
ESP32-S3 is a dual core Xtensa SoC
Not full featured yet. Some of the missing functionality:
-Semihosting
-Flash breakpoints
-Flash loader
-Apptrace
-FreeRTOS
Signed-off-by: Erhan Kurubas <erhan.kurubas@espressif.com>
Change-Id: I44e17088030c96a9be9809f6579a4f16dbfc5794
Reviewed-on: https://review.openocd.org/c/openocd/+/6990
Tested-by: jenkins
Reviewed-by: Ian Thompson <ianst@cadence.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
ESP32 is a dual core Xtensa SoC
Not full featured yet. Some of the missing functionality:
-Semihosting
-Flash breakpoints
-Flash loader
-Apptrace
-FreeRTOS
Signed-off-by: Erhan Kurubas <erhan.kurubas@espressif.com>
Change-Id: I76fb184aa38ab9f4e30290c038b5ff8850060750
Reviewed-on: https://review.openocd.org/c/openocd/+/6989
Tested-by: jenkins
Reviewed-by: Ian Thompson <ianst@cadence.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Arm "CoreSight System-on-Chip SoC-600" specification describes a
bridge "Access Port v1 adapter" aimed to "connect a legacy Access
Port (AP) ... into an CoreSight Architecture v3 system".
A ROM table can be located in the "legacy" part of the system,
on the legacy AP behind the APv1 adapter.
For the purpose of scanning the ROM tables, consider an ADIv6
SoC-600 APv1 adapter as an ADIv5 AP.
Change-Id: I97d42fb77013c1251fb68d0caa4274086bf38a70
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6827
Tested-by: jenkins
Configuration file can specify, as target's debug AP, an AP that
contains a ROM table that points, in turn, to other APs.
Current code in cortex_a and aarch64 is not able to handle a
return from dap_lookup_cs_component() that points to another AP.
While it could be interesting to specify 'root' as target's debug
AP, drop any found value if it's not in the starting AP.
Change-Id: Id206e4fa7a29e9402c8e2393026817b410bbb8bd
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6826
Tested-by: jenkins
ADIv6 adds AP that only contain a ROM table in the AP itself, that
can point to other AP containing either another AP level ROM table
or a MEM-AP to be parsed as usual.
Add support for parsing AP level ROM tables.
Change-Id: Ic25863b16463b8a6adc3b15e26db7fdca858d6df
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6467
Tested-by: jenkins
ADIv6 adds AP that only contain a ROM table in the AP itself, that
can point to other AP containing either another AP level ROM table
or a MEM-AP to be parsed as usual.
To handle recursive AP access, reorganize the code to:
- pass the depth==0 from the command 'dap info';
- print the AP number as first line, adding proper indentation on
depth>0;
- align the following print with proper indentation.
Change-Id: I5b811810c807fc51b307bd60f67817d9de2aa095
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6466
Tested-by: jenkins
On ADIv6 the system root ROM table is found by reading the DAP DP
registers BASEPTR0 and BASEPTR1.
Add option 'root' to the commands 'dap info' to let it retrieve
the system root ROM table's AP from DAP DP, then use such AP for
following dump.
Change-Id: I1789457a005faa3870c5d14f763378d2f6a5f095
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6462
Tested-by: jenkins
ADIv5 DAP can only have 256 AP, while ADIv6 can provide till
2**40 (1,099,511,627,776) AP per DAP.
Reuse the field ap_num in struct adiv5_ap, currently used on ADIv5
to hold the ADIv5 AP number (apsel), to contain the ADIv6 AP base
address.
Convert struct adiv5_ap->ap_num to 64 bit and initialize it to
DP_APSEL_INVALID for unused AP.
Restrict dap_find_get_ap() to ADIv5 only. To be enhanced.
On ADIv6, let dap_get_ap() return an already allocated AP, or
allocate and return an unused AP.
Add function is_ap_num_valid() and use it.
Change-Id: Ib2fe8c7ec0d08393cd91c29fdac5d632dfc1e438
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6461
Reviewed-by: Daniel Goehring <dgoehrin@os.amperecomputing.com>
Tested-by: jenkins
During enter in SWD read DP_DPIDR without selecting the register
bank through DP_SELECT_DPBANK.
Handle the different format of DP_SELECT register.
Change-Id: Iea1b8eb6ec94177e16a430d5885595a38e833eeb
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6697
Tested-by: jenkins
ADIv5 reports:
Accessing AP registers or debug resources in connected
device through an AP can be subjected to other variable
response delays in the system. A debugger that can adapt
to these delays and avoid wasting WAIT scans operates more
efficiently and provides higher maximum data throughput.
The existing code in OpenOCD uses extra tck only for accessing
resources through an AP.
Extend the use of extra tck also for accessing an AP register.
Split from change https://review.openocd.org/6077/
Change-Id: I2082362e098d09f4ba0668e01f5196afc965c8f3
Signed-off-by: Kevin Burke <kevinb@os.amperecomputing.com>
Signed-off-by: Daniel Goehring <dgoehrin@os.amperecomputing.com>
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6460
Tested-by: jenkins
swd and dap-direct are not implemented yet
Split from change https://review.openocd.org/6077/
Change-Id: I6d73d8adf6a6090001c5d4771325fb1d63c45e3c
Signed-off-by: Kevin Burke <kevinb@os.amperecomputing.com>
Signed-off-by: Daniel Goehring <dgoehrin@os.amperecomputing.com>
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6459
Tested-by: jenkins
By accessing invalid AP in JTAG mode, it's possible to trigger the
error:
JTAG-DP STICKY ERROR
After that the sticky error is never cleared and the whole DAP
gets not anymore accessible.
Clean-up the sticky error once detected.
Change-Id: I8b07263b30f9e46645f0c29084b8f1626e241f45
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6430
Tested-by: jenkins
Required for parsing ADIv6 ROM tables.
Split from change https://review.openocd.org/6077/
Change-Id: I849543b7b4a4455b10bd9fc7da38a37849d71700
Signed-off-by: Kevin Burke <kevinb@os.amperecomputing.com>
Signed-off-by: Daniel Goehring <dgoehrin@os.amperecomputing.com>
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6458
Tested-by: jenkins
ADIv5 MEM-AP registers are a subset of ADIv6 MEM-AP registers and
are located at different offset.
To prepare for introducing ADIv6, add 'struct adiv5_dap *' as
argument to ADIv5 registers macro.
Check the ADI version and use the proper address.
Both adapter drivers rshim and stlink are ADIv5 only, so let them
use the ADIv5 macros only.
Split from change https://review.openocd.org/6077/
Change-Id: Ib861ddcdab74637b2082cc9f2612dea0007d77b1
Signed-off-by: Kevin Burke <kevinb@os.amperecomputing.com>
Signed-off-by: Daniel Goehring <dgoehrin@os.amperecomputing.com>
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6457
Tested-by: jenkins
Add flags to 'dap create' command and set the field adi_version
in struct adiv5_dap.
Actually only ADIv5 is functional. Other patches are needed to get
ADIv6 working.
Split from change https://review.openocd.org/6077/
Change-Id: I63d3902f99a7f139c15ee4e07c19eae9ed4534b9
Signed-off-by: Kevin Burke <kevinb@os.amperecomputing.com>
Signed-off-by: Daniel Goehring <dgoehrin@os.amperecomputing.com>
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6456
Tested-by: jenkins
While an ADIv5 DAP can only have 256 AP, ADIv6 can provide till
2**40 (1,099,511,627,776) AP per DAP.
The actual trivial code implementation for ADIv5 (that uses an
array of 256 ap in the struct adiv5_dap) cannot be extended as-is
to handle ADIv6.
The simple array of 256 AP can be reused as a dynamic storage for
ADIv6 ap:
- the ADIv5 AP number is replaced by the ADIv6 base address;
- the index of the array (equal to ADIv5 AP number) has no link to
any ADIv6 property;
- the ADIv6 base_address has to be searched in the array of AP.
The 256 elements in the AP array should be enough for any device
available today. In future it can be easily increased, if needed.
To efficiently use the 256 elements in the AP array, the code
should associate one element of the array to an ADIv6 AP (through
the AP base address), then cancel the association when the AP is
not anymore needed. This is important to avoid saturating the AP
array while exploring the device through 'dap apreg' commands.
Add a reference counter in the struct adiv5_ap to track how many
times the struct has been associated with the same base address.
Introduce the function dap_get_ap() to associate and return the
struct, and dap_put_ap() to release the struct. For the moment the
code covers ADIv5 only, so the association is through the index.
Use the two functions above and dap_find_get_ap() throughout the
code.
Check the return value of dap_get_ap(). It is always not NULL in
the current ADIv5-only implementation, but can be NULL for ADIv6
when there are no more available AP in the array.
Instrument dap_queue_ap_read() and dap_queue_ap_write() to log an
error message if the AP has reference counter zero, meaning that
the AP has not been 'get' yet. This helps identifying AP used
without get/put, e.g. code missed by this patch, or merged later.
Instrument dap_cleanup_all() to log an error message if an AP has
reference counter not zero at openocd exit, meaning that the AP
has not been 'put' yet.
Change-Id: I98316eb42b9f3d9c9bbbb6c73b1091b53f629092
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6455
Reviewed-by: Daniel Goehring <dgoehrin@os.amperecomputing.com>
Tested-by: jenkins
The segfault could be triggered if:
- At least one target failed to get examined (therefore does not have the
register cache set up yet),
- and "reset" TCL command was issued, which internally tries to
invalidate the register cache.
Minor cleanup: "registers_initialized" member removed from riscv_info_t
because it is not used anywhere.
Change-Id: I6288c0d4343ef6a330fb2a6b49d388e7eafa32a2
Signed-off-by: Jan Matyas <matyas@codasip.com>
There is an accsess to wrong index, when arm semihosting_basedir
command not used or basedir set to empty string.
Signed-off-by: Erhan Kurubas <erhan.kurubas@espressif.com>
Change-Id: I3afa049d74b30496f5c03ba4ef67431784f81bdc
Fixes: ce5027ab01 ("semihosting: add semihosting_basedir command")
Reviewed-on: https://review.openocd.org/c/openocd/+/7005
Tested-by: jenkins
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
In function adiv5_jim_configure() check that calloc() returns a
valid allocated memory pointer.
Change-Id: I97287e168834693900341add9d9eb9a5f38c55b4
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reported-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/7014
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
While scan-build complains that dap_p or ap_num_p could be NULL,
the current code never passes NULL pointers.
Add an assert() to silent scan-build and prevent any further use
of the function with incorrect parameters.
Change-Id: I656810dddcea61e85d85b13efb114f7607ef837c
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7012
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Commit d01b3d69ec ("arm_adi_v5: separate ROM table parsing from
command output [3/3]") introduces a new scan-build warning because
removing one return in case of error causes using uninitialized
values.
Add back the return on error.
Change-Id: I10ddc548b756d34aaccc0511f091b4caa5ec271a
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Fixes: d01b3d69ec ("arm_adi_v5: separate ROM table parsing from command output [3/3]")
Reviewed-on: https://review.openocd.org/c/openocd/+/7011
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Commit 21f7885d1c ("arm_adi_v5: separate ROM table parsing from
command output [1/3]") introduces a new scan-build warning because
continues the execution even when dap_get_debugbase() returns
error. The value of 'apid' can be uninitialized:
5th function call argument is an uninitialized value
Check the return value and quit on error.
While there, remove the useless initialization of 'dbgbase' that
was apparently required for the same problem.
Change-Id: Iade26a152925ee0f1bf114ed829b94f7ed5b254f
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Fixes: 21f7885d1c ("arm_adi_v5: separate ROM table parsing from command output [1/3]")
Reviewed-on: https://review.openocd.org/c/openocd/+/7010
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
ESP32-S2 is a single core Xtensa chip.
Not full featured yet. Some of the missing functionality:
-Semihosting
-Flash breakpoints
-Flash loader
-Apptrace
-FreeRTOS
Signed-off-by: Erhan Kurubas <erhan.kurubas@espressif.com>
Change-Id: I2fb32978e801af5aa21616c581691406ad7cd6bb
Reviewed-on: https://review.openocd.org/c/openocd/+/6940
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-by: Ian Thompson <ianst@cadence.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
when using semi-hosting with cortex_a this LOG_INFO pollutes openocd
console, so just reduce the log level of this message.
Change-Id: I91aa70492f4e361b25a0e5517d0cf73f2f8ed599
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-on: https://gerrit.st.com/c/stm32ide/official/openocd/+/248225
Tested-by: Tarek BOCHKATI <tarek.bouchkati@st.com>
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@st.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6993
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
The command 'flash erase_check' showed the message
'Running slow fallback erase check - add working memory'
even in the case the target didn't implement blank_check_memory.
Change return code of target_blank_check_memory() in this case
and sense it in default_flash_blank_check() and show a message
without a request for working memory.
Change-Id: I7cf9bf77742964b4f377c9ce48ca689e57d0882f
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/6765
Tested-by: jenkins
Reviewed-by: Tim Newsome <tim@sifive.com>
This helps e.g. if there are 8 cores, and cores 0--3 are in one SMP
group while 4--7 are in another group. (And there are 2 gdb instances
connected, one debugging the first group, and one the second.)
Signed-off-by: Tim Newsome <tim@sifive.com>
Change-Id: I7b6c9382eadf964529105eaf0411a42d48768668
Reviewed-on: https://review.openocd.org/c/openocd/+/6979
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
* Update debug_defines from the spec.
Now it includes constants for field values, so use them instead of
duplicating that here.
Change-Id: I2fca6e89f25123c39d4bf483b8244e47aefb0f88
* Remove unused #defines
Change-Id: Id20351851c9ed2c3aa82ccf8c04b604bef11692a
* Use debug spec constants in a few more places
Change-Id: Ic4578729c89e3c6a26a72772e1635c5345bd6a52
Signed-off-by: Tim Newsome <tim@sifive.com>
* Use macros for trigger action types.
Which were added with the very latest debug_defines.h.
Change-Id: I47f73e11d2ec529c720f2e1df05f7b0d3026e43a
Signed-off-by: Tim Newsome <tim@sifive.com>
This command allows users to set base working directory for the
semihosting I/O operations.Default is the current OpenOCD directory.
Signed-off-by: Erhan Kurubas <erhan.kurubas@espressif.com>
Change-Id: I80c5979e4c96d66cccdd12cc6fcd5f353e5c6b4d
Reviewed-on: https://review.openocd.org/c/openocd/+/6888
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Removes Warning: line 6482, column 12
1st function call argument is an uninitialized value
Use target ptr directly as checked in previous lines instead of
dereferencing head->target
Change-Id: I6804b776fd493af71f3098d702f9cdc7acb50151
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/6970
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
* Change set_haltgroup() to more general set_group()
Change-Id: Ib91a252ac63604e54b756f70c549ccd47241fd10
Signed-off-by: Tim Newsome <tim@sifive.com>
* Properly use enum.
Change-Id: I0edef6053fac388db38a22fe7557623fa93ec705
Co-authored-by: Jan Matyas <50193733+JanMatCodasip@users.noreply.github.com>
* Style changes suggested in review.
Change-Id: I29e83d3dbef09cb971ec0355aff733191a6e4679
Signed-off-by: Tim Newsome <tim@sifive.com>
Co-authored-by: Jan Matyas <50193733+JanMatCodasip@users.noreply.github.com>
The function target_type::deassert_reset() is called for every
target after reset is deasserted. If the target fails to get
halted, we log a warning and issue a halt request for the target
itself.
Current code calls the generic target_halt() that:
- extends the halt to all the targets in the SMP node;
- waits for targets to halt.
This breaks the logic of running target_type::deassert_reset()
per target. Plus, waiting for targets to halt delays the call of
target_type::deassert_reset() for the next targets.
Replace the call to target_halt() with the aarch64 specific
function to halt the single target. Pass the parameter HALT_LAZY
to prevent the wait for target halted.
Similar solution is already implemented for cortex_a.
Change-Id: I446dc03cb91524c6d388db485bc2388177af77b6
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6947
Tested-by: jenkins
Arm documentation does not explicitly report the order of the two
32bit words that compose the 64bit value. But both ADIv5 and ADIv6
specify that only little-endian is supported (ADIv5.2 obsoletes
the big-endian support). This change reads the 64bit value in
little-endian.
Detect the 64bit content and use it.
Change-Id: I723ec099c7e8c70c1f9a568e32ea867fcbf1f1db
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6465
Tested-by: jenkins
With the generic function for ROM table walk-through, reimplement
dap_lookup_cs_component().
Catch the code CORESIGHT_COMPONENT_FOUND and halt the search.
While there, drop two macros in arm_coresight.h, now unused.
Change-Id: I589ef7ae8a651d0c422ce7d0b4ed913713a8217e
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6824
Tested-by: jenkins
Simplify the code in cortex_a and aarch64 by moving the call to
dap_get_debugbase() inside dap_lookup_cs_component().
This has the further effects:
- dap_get_debugbase() is not referenced outside arm_adi_v5.c and
becomes static;
- dap_lookup_cs_component() looses one parameter;
- the coreid parameter 'idx' is passed as value;
- the caller in aarch64 don't have and don't print the irrelevant
value of AP register APID;
- fixes the debug message in the caller in aarch64 to print the
coreid value instead of always zero.
Change-Id: Ic7f0f643fdf067c059c8f2455a02ff18a3fed054
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6823
Tested-by: jenkins
Now all the actions (build command output) of command "dap info"
are decoupled from the ROM walk-through.
Pass the actions as a generic parameter to ROM walk-through code.
Put as private data every information that is only required by the
actions and not by the ROM walk-through.
Change-Id: I3b6ad112ea21296458c94aebbf91bf65bf6657a7
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6822
Tested-by: jenkins
This change only targets the output of rtp_rom_loop().
Change-Id: If9ac013798923428c3b897a969887e98b6935a2b
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6821
Tested-by: jenkins
This change only targets the output of rtp_cs_component().
To easily propagate the coordinates of the CoreSight component,
add them in the struct that holds the register values.
While there, define a macro for the max depth of ROM tables.
Change-Id: I75e5ef4f9419da3192123aebcd61471c2af9374f
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6820
Tested-by: jenkins
In OpenOCD arm_adi_v5 we have already two implementations of code
for parsing the ADIv5 ROM table:
- in the commands "dap info" and "$dap_name info";
- in the function dap_lookup_cs_component().
Adding support for ADIv6 requires extending both implementations.
Moreover, current code does not handle few aspects of the ROM
parsing, e.g. the "Power Domain IDs".
To add such extensions both implementations should be touched.
I plan to add a command to parses (again) the ROM table and dump a
simple prototype of a configuration script for the target, useful
while analysing a new target.
Keeping aligned all these implementation would be too complex.
With focus to "dap info" command, decouple the part of code to
walk-through the ROM table from the code that creates the command
output.
The idea is to keep a single implementation for the walk-through
code, while parametrizing the output code to handle the generation
of a configuration script or the result of the function
dap_lookup_cs_component().
This change only targets the output of MEM-AP header
Further changes will target other parts of the code.
While there, add a message if MEM-AP is not accessible.
Change-Id: I112f637edfdb8688afb4e631297f6536da9604f1
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6819
Tested-by: jenkins
ARM IHI0031F "Arm Debug Interface Architecture Specification"
chapter C2.6.1 "BASE, Debug Base Address register" reports:
A debugger must handle the following situations as
non-fatal errors:
- ...
- An entry in the ROM Table points to a faulting location.
- ...
Typically, a debugger issues a warning if it encounters
one of these situations. However, Arm recommends that it
continues operating. An example of an implementation that
might cause errors of this type is a system with static
base address or ROM Table entries that enable entire
subsystems to be disabled, for example by a tie-off input,
packaging choice, fuse, or similar.
Don't halt ROM table parsing if one entry causes an error; log the
error condition and continue to next entry.
Not sure if we have to send an ABORT before continuing.
Change-Id: I94fdb5b175bfb07dde378149421582b7e7cd5b09
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6818
Tested-by: jenkins
Reviewed-by: Daniel Goehring <dgoehrin@os.amperecomputing.com>
As Class 0x1 ROM table, also Class 0x9 ROM tables encodes a flag
for system memory access.
Detect the flag in rtp_cs_component() and dump the same message
for both type of ROM tables.
Extend rtp_read_cs_regs() to read ARM_CS_C9_DEVID.
Change-Id: Ic85d1ea068ed706ceedfd65076ff4c96d04e9792
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6817
Tested-by: jenkins
Reviewed-by: Daniel Goehring <dgoehrin@os.amperecomputing.com>
During ROM table parsing, each ROM table entry points to a
CoreSight component that can, in turn, be another ROM table.
Split the specific code for ROM table handling from the generic
CoreSight code.
Log an error if a ROM table entry cannot be read.
Change-Id: I5ad106a99b9c21ddb48b5b162ae87101e4f49878
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6816
Tested-by: jenkins
Rework dap_read_part_id() while preparing for reorganizing the
'ROM Table Parsing' (RTP):
- rename it with 'rtp' prefix;
- extends it to read other CoreSight registers, thus improving the
overall speed by queuing more reads;
- reduce the list of arguments by using a struct;
- reorder the reads by increasing offset, potentially gaining
speed using MEM_AP_REG_BDx and/or auto-increment;
- log a debug message in case of read error.
Change-Id: I6544ac7740b808a6c0fbacf97ac00b97f5bd3832
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6815
Tested-by: jenkins
ADI v5.1 and v6.0 permit the definition of CoreSight components (class 9
ROM entries).
dap_rom_display() is refactored a bit such that we always end up with
attempting to parse the ROM contents using the appropriate upper limit
for class 1 and 9 ROM types.
Change-Id: I4ba497b3807f1f11f06186eb6e61959ea3540c59
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6359
Tested-by: jenkins
Use the list of values from ARM IHI0029E to decode and print the
Device Architecture register.
Add attribute 'unused' to the function, not used yet.
Change-Id: I7b1dd204bd1db671578c588372b667e23611876c
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6463
Tested-by: jenkins
Reviewed-by: Daniel Goehring <dgoehrin@os.amperecomputing.com>
In case of AP not responding, e.g. not clocked, the first WAIT
reply is logged as:
DAP transaction stalled (WAIT) - slowing down
then OpenOCD retries the transaction few times, until it timeouts.
At each retry it prints the message:
DAP transaction stalled during replay (WAIT) - resending
Depending on JTAG speed and transport latency, the amount of log
messages can be quite annoying and not relevant.
The last printed line is at timeout:
Timeout during WAIT recovery
Reduce the verbosity.
Change-Id: I5a7a337527c98b2450de59066b13713511c2894f
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6814
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-by: Daniel Goehring <dgoehrin@os.amperecomputing.com>
Right now it has a single use but it will soon be used more.
Change-Id: I9a819c65df467fc859e4b5251035a17ed33daa35
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6813
Tested-by: jenkins
Reviewed-by: Daniel Goehring <dgoehrin@os.amperecomputing.com>
In jimtcl 0.80 the prototype of Jim_DictPairs() has changed.
The only code in OpenOCD that uses Jim_DictPairs() has been merged
recently and it only uses the current jimtcl syntax.
To allow compiling OpenOCD master branch with older versions of
jimtcl, detect the version of jimtcl and use the appropriate
syntax.
Change-Id: I6fc78303b6a4db064a97f326c46119f4568e88f3
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reported-by: dullfire@yahoo.com
Reviewed-on: https://review.openocd.org/c/openocd/+/6948
Tested-by: jenkins
The deprecation was already in the documentation since v0.11.0
through commit 85ba2dc4c6 ("rtos/hwthread: add hardware-thread
pseudo rtos") but OpenOCD was not informing the user printing a
runtime message.
Remove the deprecated method from the documentation and print a
deprecated message at runtime.
There is no reliable way to print the same message in GDB console,
so we have to rely on user noticing it in the OpenOCD log.
Target is to remove the functionality after v0.12.0.
Change-Id: Idd2d9e3b6eccc92dcf0432c3c7de2f8a0fcabe9f
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6862
Tested-by: jenkins
Conflicts:
tcl/target/gd32vf103.cfg
I kept our version, except I changed the flash device as happened in
mainline. Once this file settles down in mainline, we can copy it
wholesale into this fork.
Change-Id: I4c5b21fec0734b5e08eba392883e006a46386b1c
on macos (homebrew base) `pkg-config --cflags capstone` output with
`-I/opt/homebrew/Cellar/capstone/4.0.2/include/capstone`
gcc not find headers on parent "include" path,
causes build error `fatal error: 'capstone/capstone.h' file not found`
it's ok to change to <capstone.h> for all platforms.
Signed-off-by: fatalc <cnfatal@gmail.com>
Change-Id: Ia2e2058024d4fc1a57a8b4ea847c664d74f67efb
Reviewed-on: https://review.openocd.org/c/openocd/+/6946
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Handle JIM_CONTINUE return value of adiv5_jim_mem_ap_spot_configure(),
otherwise OpenOCD silently quits when an unknown option is provided.
Change-Id: I9b1351c0911e74999d8dd1260ede9760088510d7
Signed-off-by: Marc Schink <dev@zapb.de>
Reviewed-on: https://review.openocd.org/c/openocd/+/6944
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Fixed the reading of p_flags in ELF64 segment headers - that field
is 64 bits wide.
Change-Id: I053ca57d36efb54b7c638484acd6c7a2fbcbd05a
Signed-off-by: Jan Matyas <matyas@codasip.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6927
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
* riscv: Add a option to specify the JTAG TAP IR used to access the bscan tunnel.
Change-Id: Ice8798823313e2177e75473e62b06e7da74bbba2
Signed-off-by: Charles Papon <charles.papon.90@gmail.com>
* risc-v: Add litex doc about the set_bscan_tunnel_ir command
Change-Id: I1237213f32886d20fc7d60d5ca1e2124953eaeda
Signed-off-by: Dolu1990 <charles.papon.90@gmail.com>
* risc-v: remove tunnel ir length assert when ir is set by the user
Change-Id: I2b33fc6205f37461ff1bd15601b460a2467ea32b
Signed-off-by: Dolu1990 <charles.papon.90@gmail.com>
* Open riscv: Add a option to specify the JTAG TAP tunnel IR
Typo
Co-authored-by: Tim Newsome <tim@sifive.com>
* riscv: Add a option to specify the JTAG TAP tunnel IR
typo
Co-authored-by: Tim Newsome <tim@sifive.com>
Co-authored-by: Tim Newsome <tim@sifive.com>
Including config.h as first is required for every C file.
Add it to the C files that still miss it.
Change-Id: I1a210e7d3a854958a85a290b086ad8a9f5176425
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6856
Tested-by: jenkins
While the documentation reports that SWO pin frequency can be
omitted to let the adapter autodetect the value, the code wrongly
drops an error when pin frequency is not specified.
Don't require the pin frequency to be set at "enable", but verify
that the adapter has properly changes it to a valid value.
Change-Id: I3dfbe3256e8887ef4f03512769b06381cdc9db0d
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reported-by: Karl Palsson <karlp@tweak.net.au>
Fixes: 184724d14e ("arm_tpiu_swo: add support for independent TPIU and SWO")
Reviewed-on: https://review.openocd.org/c/openocd/+/6310
Tested-by: jenkins
Reviewed-by: zapb <dev@zapb.de>
Commit dbbac5f11d ("semihosting: use open mode flags from GDB,
not from sys/stat.h") fixes the conversion of the mode flags from
ARM semihosting encoding for SEMIHOSTING_SYS_OPEN to GDB mapping
for open().
Doing this, it breaks the conversion to local host's OS mapping
for open().
Split the conversion array to one for GDB and one for local host.
The local host conversion array is taken directly from the old
code.
Change-Id: I385321ddd32c3ac5cf6da3f1ce9eff76b05dd527
Fixes: dbbac5f11d ("semihosting: use open mode flags from GDB, not from sys/stat.h")
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reported-by: Erhan Kurubas <erhan.kurubas@espressif.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6870
Tested-by: jenkins
* Fix checkpatch workflow: ignore changes in .github/
Ignore changes in .github/ directory when running checkpatch.
Checkpatch emits false alarms on substrings "CC:" found in *.yml
workflow files, apparently thinking it is a "Cc:" signature in
commit message.
Change-Id: Id977d5a8838797e4676758066af4825651c41a87
* Fix: Set proper debug_reason in deassert_reset()
The issue was visible for example when user's .cfg file ended
with "reset halt" command:
In such case, the hart would remain halted but the debug_reason would not be
updated and may retain an incorrect value, e.g. DBG_REASON_NOTHALTED.
In such cases, gdb_last_signal() would provide an incorrect reply to GDB.
Change-Id: Ie6f050295fb5cbe9db38b189c4bc385662acf5b4
Signed-off-by: Jan Matyas <matyas@codasip.com>
* Fix checkpatch workflow: add 'apt-get update'
Change-Id: Ic5843ec86d16a187d01970a3253caade3d13b7ab
Signed-off-by: Jan Matyas <matyas@codasip.com>
Some configuration of GCC could default to -fno-inline, causing
the build to fail after commit fb43f1ff4e ("target: Rework 'set'
variable of break-/watchpoints").
Switch the new inline functions to 'static inline', as it's widely
used in the rest of the code.
Change-Id: I8bf31045a137bd34ed825f4b2a9338eb3c70046d
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Fixes: fb43f1ff4e ("target: Rework 'set' variable of break-/watchpoints")
Reviewed-on: https://review.openocd.org/c/openocd/+/6881
Tested-by: jenkins
The 'set' variable name suggests a boolean data type which determines
whether a breakpoint (or watchpoint) is active. However, it is also
used to store the number of the breakpoint.
This encoding leads to inconsistent value assignments: boolean and
integer values are mixed. Also, associated hardware comparator
numbers, which are usually numbered from 0, cannot be used directly.
An additional offset is required to store the comparator numbers.
In order to make the code more readable and the value assignment more
consistent, change the variable name to 'is_set', its data type to 'bool'
and introduce a dedicated variable for the break-/watchpoint
number.
In order to make the review easier, the data types of various related
variables (e.g. number of breakpoints) are not changed.
While at it, fix a few coding style issues.
Change-Id: I2193f5639247cce6b80580d4c1c6afee916aeb82
Signed-off-by: Marc Schink <dev@zapb.de>
Reviewed-on: https://review.openocd.org/c/openocd/+/6319
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
This command permits the usage of a TCP port to perform debug and stdio
operations:
- debug : READC, WRITEC and WRITE0
- stdio : READ, WRITE
This will permit the separation of semihosting message from OpenOCD log,
and separate semihosting messages per core.
syntax: arm semihosting_redirect (disable | tcp <port> [debug|stdio|all])
this allows to select which operations to be performed via TCP (debug,
stdio or all (default)).
Note: for stdio operations, only I/O from/to ':tt' file descriptors are
redirected.
tested using netcat on ubuntu
Change-Id: I37053463667ba109d52429d4f98bc98d0ede298d
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/5562
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
To easily add new methods to a service, pass all the methods
through a struct.
While there, drop the typedef for the methods and add currently
unused new methods to support keep-alive and connections during
keep-alive.
No change in functionality.
Change-Id: I2b5e7140db95021f6e7201e9d631ee340c60b453
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6838
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Tested-by: jenkins
Replace 'mem2array' and 'array2mem' with a Tcl wrapper that
internally uses 'read_memory' and 'write_memory'.
The target-specific 'mem2array' and 'array2mem' functions
remain for now.
Change-Id: If24c22a76ac72d4c26916a95f7f17902b41b6d9e
Signed-off-by: Marc Schink <dev@zapb.de>
Reviewed-on: https://review.openocd.org/c/openocd/+/6308
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
These functions are meant as replacement for 'mem2array' and
'array2mem'.
The main benefits of these new functions are:
* They do not use Tcl arrays but lists which makes it easier
to parse (generate) the data. See the Python Tcl RPC code
in contrib as a negative example.
* They do not operate on Tcl variables but instead return (accept)
the Tcl list directly. This makes the C and Tcl code base
smaller and cleaner.
* The code is slightly more performant when reading / writing
large amount of data. Tested with a simple Python Tcl RPC
benchmark.
Change-Id: Ibd6ece3360c0d002abaadc37f078b10a8bb606f8
Signed-off-by: Marc Schink <dev@zapb.de>
Reviewed-on: https://review.openocd.org/c/openocd/+/6307
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
The current implementation crashes when executing 'tpiu create'
without an object name due to an invalid memory access. Pass 'argv'
instead 'goi.argv' to fix the problem.
While at it, match the style of the error message to the style used for
other Tcl commands. Especially, make the 'name' parameter mandatory.
Change-Id: Ib2b233f8556934af61608ae93d6405585c2c40b7
Signed-off-by: Marc Schink <dev@zapb.de>
Reviewed-on: https://review.openocd.org/c/openocd/+/6329
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
* flash/nor/atsame5: add LAN9255 devices
Support Microchip LAN9255 devices with embedded SAME53J MCU.
Signed-off-by: Hans-Erik Floryd <hans-erik.floryd@rt-labs.com>
Change-Id: Ia811c593bf7cf73e588d32873c68eb67c6fafad7
Reviewed-on: https://review.openocd.org/c/openocd/+/6811
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
* tcl/board: Add EVB-LAN9255 config
Config for EVB-LAN9255, tested using Atmel-ICE debugger on J10
connector.
Signed-off-by: Hans-Erik Floryd <hans-erik.floryd@rt-labs.com>
Change-Id: I8bcf779e9363499a98aa0b7d10819c53da6a19e7
Reviewed-on: https://review.openocd.org/c/openocd/+/6812
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
* aarch64: support for aarch32 ARM_MODE_UND
Fix:
unrecognized psr mode: 0x1b
cannot read system control register in this mode: (UNRECOGNIZED : 0x1b)
Change-Id: I4dc3e72f90d57e52c0fe63cb59a7529a398757b3
Signed-off-by: Julien Massot <julien.massot@iot.bzh>
Change-Id: Ifa5d21ae97492fde9e8c79ee7d99d8a2a871b1b5
Reviewed-on: https://review.openocd.org/c/openocd/+/6808
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
* Combine register lists of smp targets.
This is helpful when you want to pretend to gdb that your heterogeneous
multicore system is homogeneous, because gdb cannot handle heterogeneous
systems. This won't always works, but works fine if e.g. one of the
cores has an FPU while the other does not. (Specifically, HiFive
Unleashed has 1 core with no FPU, plus 4 cores with an FPU.)
Signed-off-by: Tim Newsome <tim@sifive.com>
Change-Id: I05ff4c28646778fbc00327bc510be064bfe6c9f0
Reviewed-on: https://review.openocd.org/c/openocd/+/6362
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
* semihosting: use open mode flags from GDB, not from sys/stat.h
Values defined in sys/stat.h are not guaranteed to match
the constants defined by the GDB remote protocol, which are defined in
https://sourceware.org/gdb/onlinedocs/gdb/Open-Flags.html#Open-Flags.
On my local system (Manjaro 21.2.1 x86_64), for example, O_TRUNC is
defined as 0x40, whereas GDB requires it to be 0x400,
causing all "w" file open modes to misbehave.
This patch has been tested with STM32F446.
Change-Id: Ifb2c740fd689e71d6f1a4bde1edaecd76fdca910
Signed-off-by: Pavel Kirienko <pavel.kirienko@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6804
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
* semihosting: User defined operation, Tcl command exec on host
Enabling a portion (0x100 - 0x107) of the user defined semihosting
operation number range (0x100 - 0x1FF) to be processed with the help of
the existing target event mechanism, to implement a general-purpose Tcl
interface for the target available on the host, via semihosting
interface.
Example usage:
- The user configures a Tcl command as a callback for one of the newly
defined events (semihosting-user-cmd-0x10X) in the configuration
file.
- The target can make a semihosting call with <opnum>, passing optional
parameters for the call.
If there is no callback registered to the user defined operation number,
nothing happens.
Example usage: Configure RTT automatically with the exact, linked
control block location from target.
Signed-off-by: Zoltán Dudás <zedudi@gmail.com>
Change-Id: I10e1784b1fecd4e630d78df81cb44bf1aa2fc247
Reviewed-on: https://review.openocd.org/c/openocd/+/6748
Tested-by: jenkins
Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
* target/smp: use a struct list_head to hold the smp targets
Instead of reinventing a simply linked list, reuse the list helper
for the list of targets in a smp cluster.
Using the existing helper, that implements a double linked list,
makes trivial going through the list in reverse order.
Change-Id: Ib36ad2955f15cd2a601b0b9e36ca6d948b12d00f
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6783
Tested-by: jenkins
* helper/list: add list_for_each_entry_direction()
Use a bool flag to specify if the list should be forward or
backward iterated.
Change-Id: Ied19d049f46cdcb7f50137d459cc7c02014526bc
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6784
Tested-by: jenkins
* target/riscv: revive 'riscv resume_order'
This functionality was lost in [1], which was merged as commit
615709d140 ("Upstream a whole host of RISC-V changes.").
Now it works as expected again.
Add convenience macro foreach_smp_target_direction().
Link: [1] https://github.com/riscv/riscv-openocd/pull/567
Change-Id: I1545fa6b45b8a07e27c8ff9dcdcfa2fc4f950cd1
Signed-off-by: Tim Newsome <tim@sifive.com>
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6785
Tested-by: jenkins
* doxygen: fix some function prototype description
Change-Id: I49311a643ea73143839d2f6bde976cfd76f8c67f
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6830
Tested-by: jenkins
* Cadence virtual debug interface (vdebug) integration
Change-Id: I1bc105b3addc3f34161c2356c482ff3011e3f2cc
Signed-off-by: Jacek Wuwer <jacekmw8@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6097
Tested-by: jenkins
Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
Reviewed-by: zapb <dev@zapb.de>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
* gdb_server: Include thread name as XML attribute
Explicitly providing a thread name in the "thread" element produces
better thread visualizations in downstream tools like IDEs.
Signed-off-by: Ben McMorran <bemcmorr@microsoft.com>
Change-Id: I102c14ddb8b87757fa474de8e3a3f6a1cfe10d98
Reviewed-on: https://review.openocd.org/c/openocd/+/6828
Tested-by: jenkins
Reviewed-by: zapb <dev@zapb.de>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
* Fix small memory leak.
See https://github.com/riscv/riscv-openocd/pull/672
Change-Id: Ia11ab9bcf860f770ea64ad867102c74b898f6b66
Signed-off-by: Tim Newsome <tim@sifive.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6831
Tested-by: jenkins
Reviewed-by: zapb <dev@zapb.de>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
* server: remove remaining crust from dropped eCos code
Commit 39650e2273 ("ecosboard: delete bit-rotted eCos code") has
removed eCos code but has left some empty function that was used
during non-eCos build to replace eCos mutex.
Drop the functions and the file that contain them.
Change-Id: I31bc0237ea699c11bd70921660f960ee406ffa80
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6835
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
* rtos: threadx: Add hla_target support for ThreadX
Tested with an AZ3166 dev board (which uses the STM32F412ZGT6) running
the Azure RTOS ThreadX demonstration system.
Signed-off-by: Ben McMorran <bemcmorr@microsoft.com>
Change-Id: I44c8f7701d9f1aaa872274166321cd7d34fb1855
Reviewed-on: https://review.openocd.org/c/openocd/+/6829
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
* .gitmodules: switch away from repo.or.cz
The host repo.or.cz is often offline, creating issues for cloning
and building OpenOCD from scratch.
Already 'jimtcl' developer has dropped repo.or.cz, triggering the
OpenOCD commit 861e75f54e ("jimtcl: switch to github").
Change also the link of the remaining submodules 'git2cl' and
'libjaylink' to their respective main repository.
Change-Id: Ib513237427635359ce36a480a8f2060e2fb12ba4
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6834
Tested-by: jenkins
Reviewed-by: zapb <dev@zapb.de>
* flash/nor/stm32f2x: Fix erase of bank 2 sectors
This commit corrects the erase function for stm32f2x when dealing with
sectors in bank 2, for STM32F42x/43x devices with 1MB flash.
On STM32F42x/43x with 1MB flash in dual bank configuration, the sector
numbering is not consecutive. The last sector in bank 1 is number 7, and
the first sector in bank 2 is number 12.
The sector indices used by openocd, however, _are_ consecutive (0 to 15
in this case). The arguments "first" and "last" to stm32x_erase() are of
this type, and so the logic surrounding sector numbers needed to be
corrected.
Since the two banks in dual bank mode have the same number of sectors, a
sector index in bank 2 is larger than or equal to half the total number
of sectors.
Change-Id: I15260f8a86d9002769a1ae1c40ebdf62142dae18
Signed-off-by: Simon Johansson <ampleyfly@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6810
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
* target/cortex_m: fix target_to_cm() helper
The third parameter of container_of() should point to the same member
as target->arch_info points to, struct arm.
It worked just because struct arm is the first member in
struct armv7m_common.
If you move arm member from the first place, OpenOCD fails heavily.
Change-Id: I0c0a5221490945563e17a0a34d99a603f1d6c2ff
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/6749
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
* target/armv7m,cortex_m: introduce checked arch_info cast routines
target_to_armv7m() and target_to_cm() do not match the magic number
so they are not suitable for use outside of target driver code.
Add checked versions of pointer getters. Match the magic number
to ensure the returned value points to struct of the correct type.
Change-Id: If90ef7e969ef04f0f2103e0da29dcbe8e1ac1c0d
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/6750
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
* target/cortex_m: add Cortex-M part number getter
The getter checks the magic numbers in arch_info to detect eventual
type mismatch.
Change-Id: I61134b05310a97ae9831517d0516c7b4240d35a5
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/6751
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
* flash/nor/stm32xx: fix segfault accessing Cortex-M part number
Some of STM32 flash drivers read Cortex-M part number from
cortex_m->core_info.
In corner cases the core_info pointer was observed uninitialised
even if target_was_examined() returned true. See also [1]
Use the new and safe helper to get Cortex-M part number.
While on it switch also target_to_cm()/target_to_armv7m() to the safe
versions. This prevents a crash when the flash bank is misconfigured
with non-Cortex-M target.
Add missing checks for target_was_examined() to flash probes.
[1] 6545: fix crash in case cortex_m->core_info is not set
https://review.openocd.org/c/openocd/+/6545
Change-Id: If2471af74ebfe22f14442f48ae109b2e1bb5fa3b
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Fixes: f5898bd93f (flash/stm32fxx.c: do not read CPUID as this info is stored in cortex_m_common)
Reviewed-on: https://review.openocd.org/c/openocd/+/6752
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
* cpld: altera-epm240: Add additional IDCODEs
This adds some additional IDCODEs from the datasheet. It also adds
support for customizing the tap name.
Signed-off-by: Sean Anderson <sean.anderson@seco.com>
Change-Id: I7cda10b92c229b61836c12cd9ca410de358ede2e
Reviewed-on: https://review.openocd.org/c/openocd/+/6846
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
* cpld: altera-epm240: Increase adapter speed
According to the datasheet, the minimum clock period with Vccio1 = 1.5V
(the lowest voltage supported) is 143ns, or around 6MHz. Set the default
adapter speed to 5 MHz.
Signed-off-by: Sean Anderson <sean.anderson@seco.com>
Change-Id: I21cad33fa7f1e25e81f43b5d2214d1fa4ec924de
Reviewed-on: https://review.openocd.org/c/openocd/+/6847
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
* target: Add support for ls1088a
The LS1088A is an octo-core aarch64 processor from NXP in the layerscape
family. The JTAG is undocumented, but I was able to figure things out
from the output of `dap info`. This is the first in-tree example of
using the hwthread rtos (as far as I know), so hopefully it can serve as
an example to other developers. There are some ETMs, but I was unable to
try them out because I got 'invalid command name "etm"' when trying to
test things out.
Signed-off-by: Sean Anderson <sean.anderson@seco.com>
Change-Id: I9b0791d27d8c41170a413a8d86431107a85feba2
Reviewed-on: https://review.openocd.org/c/openocd/+/6848
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
* target: ls1088a: Add service processor
Normally the service processor is not necessary for debugging. However,
if you are using the hard-coded RCW or your boot source is otherwise
corrupt, then the general purpose processors will never be released from
hold-off. This will cause GDB to become confused if it tries to attach,
since they will appear to be running arm32 processors. To deal with
this, we can release the CPUs manually with the BRRL register. This
register cannot be written to from the axi target, so we need to do it
from the service processor target. This involves halting the service
processor, modifying the register, and then resuming it again. We try
and determine what state the service processor was in to avoid resuming
it if it was already halted.
The reset vector for the general purpose processors is determined by the
boot logation pointer registers in the device configuration unit.
Normally these are set using pre-boot initialization commands, but if
they are not set then they default to 0. This will cause the CPU to
almost immediately hit an illegal instruction. This is fine because we
will almost certainly want to attach to the processor and load a program
anyway.
I considered adding this as an event handler for either gdb-attach or
reset-init. However, this command shouldn't be necessary most of the
time, and so I don't think we should run it automatically.
Signed-off-by: Sean Anderson <sean.anderson@seco.com>
Change-Id: I1b725292d8a11274d03af5313dc83678e10e944c
Reviewed-on: https://review.openocd.org/c/openocd/+/6850
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
* board: Add NXP LS1088ARDB
This adds a board file for the NXP LS1088ARDB. This only covers the
"primary" JTAG header J55, and not the PCIe header (J91). The only
oddity is that the LS1088A and CPLD are muxed by adding/removing a
jumper from J48. Unfortunately, it doesn't look like OpenOCD supports
this CPLD beyond determining the irlen, so it's not very useful. Those
who are interested in experimenting can define CWTAP to access the CPLD,
but the default is to access the CPU.
Signed-off-by: Sean Anderson <sean.anderson@seco.com>
Change-Id: Ia07436a534f86bd907aa5fe2a78a326a27855a24
Reviewed-on: https://review.openocd.org/c/openocd/+/6849
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
* gdb_server: fix double free
Commit 6541233aa7 ("Combine register lists of smp targets.")
unconditionally assigns the output pointers of the function
smp_reg_list_noread(), even if the function fails and returns
error.
This causes a double free from the caller, that has assigned NULL
to the pointers to simplify the error handling.
Use local variables in smp_reg_list_noread() and assign the output
pointers only on success.
Change-Id: Ic0fd2f26520566cf322f0190780e15637c01cfae
Fixes: 6541233aa7 ("Combine register lists of smp targets.")
Reported-by: Michele Bisogno <michele.bisogno.ct@renesas.com>
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6852
Tested-by: jenkins
Reviewed-by: Michele Bisogno <michele.bisogno.ct@renesas.com>
Reviewed-by: Tim Newsome <tim@sifive.com>
* gdb_server: check target examined while combining reg list
Commit 6541233aa7 ("Combine register lists of smp targets.")
assumes that all the targets in the SMP cluster are already
examined and unconditionally call target_get_gdb_reg_list_noread()
that will in turn return error if the target is not examined yet.
Skip targets not examined yet.
Add an additional check in case the register list cannot be built,
e.g. because no target in the SMP cluster is examined. This should
never happen, but it's better to play safe.
Change-Id: I8609815c3d5144790fb05a870cb0c931540aef8a
Fixes: 6541233aa7 ("Combine register lists of smp targets.")
Reported-by: Michele Bisogno <michele.bisogno.ct@renesas.com>
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6853
Tested-by: jenkins
Reviewed-by: Michele Bisogno <michele.bisogno.ct@renesas.com>
Reviewed-by: Tim Newsome <tim@sifive.com>
* flash/stm32l4x: fix maybe-uninitialized compiler error
using gcc (Ubuntu 9.3.0-17ubuntu1~20.04) 9.3.0 we get:
error: ‘retval’ may be used uninitialized in this function
fixes: 13cd75b6ec (flash/nor/stm32xx: fix segfault accessing Cortex-M part number)
Change-Id: I897c40c5d2233f50a5385d251ebfa536023e5cf7
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6861
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
* Fix build.
Change-Id: Ia60246246dd859d75659a43d1c59588dbb274d46
Signed-off-by: Tim Newsome <tim@sifive.com>
Co-authored-by: Hans-Erik Floryd <hans-erik.floryd@rt-labs.com>
Co-authored-by: Julien Massot <julien.massot@iot.bzh>
Co-authored-by: Pavel Kirienko <pavel.kirienko@gmail.com>
Co-authored-by: Zoltán Dudás <zedudi@gmail.com>
Co-authored-by: Antonio Borneo <borneo.antonio@gmail.com>
Co-authored-by: Jacek Wuwer <jacekmw8@gmail.com>
Co-authored-by: Ben McMorran <bemcmorr@microsoft.com>
Co-authored-by: Simon Johansson <ampleyfly@gmail.com>
Co-authored-by: Tomas Vanek <vanekt@fbl.cz>
Co-authored-by: Sean Anderson <sean.anderson@seco.com>
Co-authored-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
The getter checks the magic numbers in arch_info to detect eventual
type mismatch.
Change-Id: I61134b05310a97ae9831517d0516c7b4240d35a5
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/6751
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
target_to_armv7m() and target_to_cm() do not match the magic number
so they are not suitable for use outside of target driver code.
Add checked versions of pointer getters. Match the magic number
to ensure the returned value points to struct of the correct type.
Change-Id: If90ef7e969ef04f0f2103e0da29dcbe8e1ac1c0d
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/6750
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
The third parameter of container_of() should point to the same member
as target->arch_info points to, struct arm.
It worked just because struct arm is the first member in
struct armv7m_common.
If you move arm member from the first place, OpenOCD fails heavily.
Change-Id: I0c0a5221490945563e17a0a34d99a603f1d6c2ff
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/6749
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
This functionality was lost in [1], which was merged as commit
615709d140 ("Upstream a whole host of RISC-V changes.").
Now it works as expected again.
Add convenience macro foreach_smp_target_direction().
Link: [1] https://github.com/riscv/riscv-openocd/pull/567
Change-Id: I1545fa6b45b8a07e27c8ff9dcdcfa2fc4f950cd1
Signed-off-by: Tim Newsome <tim@sifive.com>
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6785
Tested-by: jenkins
Instead of reinventing a simply linked list, reuse the list helper
for the list of targets in a smp cluster.
Using the existing helper, that implements a double linked list,
makes trivial going through the list in reverse order.
Change-Id: Ib36ad2955f15cd2a601b0b9e36ca6d948b12d00f
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6783
Tested-by: jenkins
Continuation of the previous patch. There are two more cases
when progbuf cache in OpenOCD shall be invalidated:
- When OpenOCD resets the debug module undergoes reset (dmactive=0),
e.g. during target examination
- When the user manually performs that very same operation
(via riscv dmi_write)
Change-Id: I53f8f08250eeedcbd55ab4361d5665370b063680
Signed-off-by: Jan Matyas <matyas@codasip.com>
This commit relates to progbuf cache,
implemented in https://github.com/riscv/riscv-openocd/pull/381
Make sure the cache gets invalidated when the progbuf
contents change via other means. I've identified two
such cases where the invalidation is required:
1) When the user manually tinkers with the progbuf registers
(TCL command "riscv dmi_write")
2) When program buffer is used as a scratch memory
(scratch_write64())
Change-Id: Ie7ffb0fccda63297de894ab919d09082ea21cfae
Signed-off-by: Jan Matyas <matyas@codasip.com>
Enabling a portion (0x100 - 0x107) of the user defined semihosting
operation number range (0x100 - 0x1FF) to be processed with the help of
the existing target event mechanism, to implement a general-purpose Tcl
interface for the target available on the host, via semihosting
interface.
Example usage:
- The user configures a Tcl command as a callback for one of the newly
defined events (semihosting-user-cmd-0x10X) in the configuration
file.
- The target can make a semihosting call with <opnum>, passing optional
parameters for the call.
If there is no callback registered to the user defined operation number,
nothing happens.
Example usage: Configure RTT automatically with the exact, linked
control block location from target.
Signed-off-by: Zoltán Dudás <zedudi@gmail.com>
Change-Id: I10e1784b1fecd4e630d78df81cb44bf1aa2fc247
Reviewed-on: https://review.openocd.org/c/openocd/+/6748
Tested-by: jenkins
Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
This lets the RTOS pick the "current" target, which matters if address
translation differs between threads.
Change-Id: I5b5510ab6a06621589c902f42a91562055817dc4
Signed-off-by: Tim Newsome <tim@sifive.com>
Values defined in sys/stat.h are not guaranteed to match
the constants defined by the GDB remote protocol, which are defined in
https://sourceware.org/gdb/onlinedocs/gdb/Open-Flags.html#Open-Flags.
On my local system (Manjaro 21.2.1 x86_64), for example, O_TRUNC is
defined as 0x40, whereas GDB requires it to be 0x400,
causing all "w" file open modes to misbehave.
This patch has been tested with STM32F446.
Change-Id: Ifb2c740fd689e71d6f1a4bde1edaecd76fdca910
Signed-off-by: Pavel Kirienko <pavel.kirienko@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6804
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
We have the API target_event_name().
Use it to improve code readability.
Change-Id: Ic48d2227bdefe9af05aff99a871a45e0612e5254
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6790
Tested-by: jenkins
If the CTI is not specified OpenOCD fails target's examination
without indicating the reason.
Drop an error message about the missing CTI.
Change-Id: I344537fb21cf38785796ba938e71890e04135509
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6788
Tested-by: jenkins
This replaces a static array with 8 bytes per register. When there are
vector registers larger than 8 bytes, they would end up clobbering each
other's values. I can't believe I didn't catch this earlier.
See https://github.com/riscv/riscv-openocd/pull/658
Change-Id: I9df4eaf05617a2c8df3140fff9fe53f61ab2b261
Signed-off-by: Tim Newsome <tim@sifive.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6775
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
We have the macro
#define COMMAND_HANDLER(name) \
static __COMMAND_HANDLER(name)
Use it!
Change-Id: I0e5385cb54197c743348f0d2ce215c93b8e396a4
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6786
Tested-by: jenkins
Unlike cortex_m_load_core_reg_u32() storing core register uses
the same code pattern around DHCSR read as offered by the convenience
helper cortex_m_read_dhcsr_atomic_sticky().
Use the helper.
Change-Id: Ia947204944a8b549f3c2be7fb2f717aad18970c4
SeeAlso: 65d7629183 (cortex_m: poll S_REGRDY on register r/w)
SeeAlso: 0dcf95c717 (target/cortex_m: cumulate DHCSR sticky bits)
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/6767
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Change [1] introduced a regression that results in comparison
in arm_jtag_set_instr() to be always true if the length of the
IR register is not 8 bit. The value on the left side
of the != operator contains only tap->ir_length number of
bits while value on the right is full 8-bit instruction code.
This forces OpenOCD to update the JTAG IR register on each
transaction even if the instruction in the JTAG IR register
is correct. This causes noticeable performance degradation,
especially with slow JTAG adapters.
[1] https://review.openocd.org/c/openocd/+/6285
time ./src/openocd -s tcl/ -f interface/cmsis-dap.cfg \
-c "transport select jtag" -f target/psoc6.cfg \
-c "init; load_image data.bin 0x08000000; exit"
Without this change:
real 0m4,863s
user 0m0,074s
sys 0m0,128s
With this change:
real 0m3,083s
user 0m0,038s
sys 0m0,098s
Signed-off-by: Bohdan Tymkiv <bohdan200@gmail.com>
Change-Id: Iaded83a04ecc7e65f18256afae582267ccc1fc59
Reviewed-on: https://review.openocd.org/c/openocd/+/6762
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
ARM IHI 0031A does not support SWJ-DP, so no switch between JTAG
and SWD is considered.
ARM IHI 0031B is not publicly available and it's reported as
"Confidential Beta" in the history list in following doc versions.
From ARM IHI 0031C the direct switch between JTAG and SWD is
already deprecated in favor of passing through dormant mode. With
no access to IHI 0031B we haven't info if any device strictly
requires the direct switch.
OpenOCD implements only the deprecated direct switch, so changing
it could cause regression on devices that do not implement dormant
mode.
Plus, not all the adapters support dormant mode.
Nevertheless there are already target devices that only allow
entering in SWD by passing through dormant.
Let the code try both method, alternating one tentative with the
deprecated legacy direct switch, then another tentative passing
through dormant, and repeat till timeout.
This would work on any device that don't support dormant, on new
devices that require switch through dormant and will work with
adapters that don't support dormant.
Change-Id: Ib8619635277d497872079a33fa4e38be9beb84a0
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6695
Tested-by: jenkins
The function debugport_init() has never existed in OpenOCD code,
but few comments erroneously references it in place of the
existing function ahbap_debugport_init().
Commit 00dbc185ee ("arm_adi_v5: Split ahbap_debugport_init")
splits the function ahbap_debugport_init() in dap_dp_init() and
mem_ap_init(), but did not removed all the incorrect comments
about debugport_init(). Few of such comments has been removed in
later patches.
Remove the last comment that references debugport_init().
Change-Id: Ibd1f125475386e5653340fedf706903a0ee15897
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6694
Tested-by: jenkins
Standard C library free() allows NULL pointer as a parameter.
Change target_free_working_area() to conform this convention.
Remove NULL pointer tests before target_free_working_area() calls.
While on it add missing setting pointer to NULL after target_free_working_area().
Change-Id: I7c692ab04a9933398ba5bc614723ad0bdecb87b3
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/6712
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Don't reexamine targets until we're past the examine stage of init().
Earlier than that, examine() will likely fail because the scan chain
hasn't been examined yet.
This will likely fix#663.
Change-Id: I76ee9181f35cedcdb1a3e0f8ac33ab361c68d3af
Signed-off-by: Tim Newsome <tim@sifive.com>
hla_target uses the same struct cortex_m_common as the standard cortex_m
target. Unlike the cortex_m target hla missed setting of common_magic.
Set commont_magic to help pointer verification.
Add convenience tests is_cortex_m_or_hla() and
is_cortex_m_with_dap_access()
Use proper test in cortex_m_verify_pointer() - this code relied on
unset common_magic on hla target before the change.
Change-Id: I4dae79f056c3d73adf524e26aa8ef2d3a57b471e
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/6741
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
* Deal with halt race.
What could happen:
1. hart 1 halts due to a breakpoint
2. OpenOCD polls and notices hart 1 has halted.
3. hart 0 halts because it is in a halt group with halt 1
4. OpenOCD decides to halt hart 0 also.
5. OpenOCD discovers hart 0 is already halted, and doesn't update the
debug reason.
In that case OpenOCD would tell gdb that hart 0 halted, while the
interesting event is that hart 1 halted.
Fix this by updating the debug reason when we discover a hart is already
halted when we try to halt it.
This race was exposed in the Sv* address translation tests, but the bug
has nothing to do with address translation.
Change-Id: I59d871e8545bd644bf42581266f15234b93e9900
Signed-off-by: Tim Newsome <tim@sifive.com>
* Comment set_debug_reason
Co-authored-by: Jan Matyas <50193733+JanMatCodasip@users.noreply.github.com>
Co-authored-by: Jan Matyas <50193733+JanMatCodasip@users.noreply.github.com>
Just to avoid name clash when comparing documentation with
registered commands through scripts.
Change-Id: I8832545d8d9236ea5dabe6e73732f51e5246caff
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6717
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Tested-by: jenkins
Do not split in multiple lines the calls to register_commands*().
No change in code behaviour, just make it easy to grep in the code
and identify the commands that can be registered.
This would help detecting undocumented commands.
Change-Id: Id654e107cdabf7ee31fc3d227c1d2a59acc5669e
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6716
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Raise error if
* more than one plain SWD DAPs are defined
* plain and multidrop DAPs are mixed
* two multidrop DAPs have the same TARGETSEL value
Inspired by Graham Sanderson's http://review.openocd.org/4935
Change-Id: I7279744464f5cc6477e50695c596be9c5e5507bf
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/6142
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Based on Graham Sanderson's http://review.openocd.org/4935
Unlike Graham Sanderson's version this patch does not add
any multidrop specific queuing.
Multidrop SWD is handled mostly by the same code as single SWD,
just a selection sequence is prepended to a SWD operation
as needed.
This is a minimal working implementation without checking for
configuration errors (mixing multidrop and non multidrop DPs,
multiple use of the same selection id etc...).
Multidrop switching likely demands changes in the adapter code.
Change-Id: I99a5742c209b49c0483e800f6105cb5e59a897d9
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/6141
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
dap_configure() contained first time init related tasks, as the call to
dap_init_instance() and the check for configured tap.
Move all first time init related stuff to dap_create() to make dap_configure()
usable in eventual stand-alone 'dap configure' command.
Change-Id: Ia86eadb4e960ce54e8581630d01af75720d2318d
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/6702
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
This is a preparatory change for swd multidrop, mostly refactoring.
Split swd_queue_dp_read/write() to inner and outer parts.
Use the inner parts in swd_queue_dp_bankselect(), swd_connect()
they do not need to check reconnect.
Use the outer parts exclusively in swd_dap_ops.
Rearrange the code to reduce forward declarations.
Change-Id: I47b7f0cb037e0032a267463f06ba02123ba96fe7
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/6139
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
I missed this when I first add mcontrol6 support.
https://github.com/riscv/riscv-openocd/pull/648
Change-Id: I1a2706c7ea3a6757ed5083091cd2c764a8b0267c
Signed-off-by: Tim Newsome <tim@sifive.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6684
Tested-by: jenkins
Reviewed-by: Jan Matyas <matyas@codasip.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
The main intention is to get access to some of the CSRs
that were so far unknown to OpenOCD (tinfo, mcountinhibit, ...).
https://github.com/riscv/riscv-openocd/pull/659
Signed-off-by: Tim Newsome <tim@sifive.com>
Change-Id: I824fdb558d5c1f73432b0f56f3b0b4d865eceeba
Reviewed-on: https://review.openocd.org/c/openocd/+/6682
Tested-by: jenkins
Reviewed-by: Jan Matyas <matyas@codasip.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Add the value DORMANT_TO_JTAG in the enum listing the SWJ-DP
switching sequences.
The corresponding bit-sequence is already available.
Change-Id: I6f1ffd29a8f5729ec70ce0303248bc251409d37d
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6689
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Tested-by: jenkins
If the target is in a state where S_REGRDY polling is necessary (slow
clock, low power state...?), OpenOCD will continue to use the slow
path even if the condition is temporary and the target at a later
point would be capable of fast reads again.
Revert to fast reads if a full register dump can be made without need
for polling any of the registers; presumably it will succeed the next
time too.
Change-Id: I557f0d90b7ce6f9d81aa409b6400fc9c83d16008
Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6678
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Without the change cortex_m_debug_entry() reads all registers
calling cortex_m_load_core_reg_u32() for each register with
a poor usage of JTAG/SWD queue.
It is time consuming, especially on an USB FS based adapter.
Moreover if target_request debugmsgs are enabled, DCB_DCRDR
is saved and restored on each register read.
This change introduces cortex_m_fast_read_all_regs()
which queues all register reads and a single dap_run() transaction
does all work.
cortex_m_fast_read_all_regs() reads all registers unconditionally
regardless register cache is valid or not. This is a difference
from the original cortex_m_debug_entry() code.
cortex_m_debug_entry times from -d3 log, Cortex-M4F and CMSIS-DAP
(Kinetis K28F-FRDM kit)
target_request | time [ms]
debugmsgs | without the change | with the change
---------------+--------------------+-----------------
disable | 186 | 27
enable | 232 | 29
Added checking of DHCSR.S_REGRDY flag. If "not ready" is seen,
cortex_m->slow_register_read is set and fallback to the old
register read method cortex_m_slow_read_all_regs() is used
instead of cortex_m_fast_read_all_regs().
Change-Id: I0665d94b97ede217394640871dc451ec93410254
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/5321
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Accordingly to arm documentation [1], chapter C1.6.4, the
operation to read/write from/to core registers can require time,
and the specific flag DHCSR.S_REGRDY has to be polled to verify
that the operation has been completed.
The lack of check on S_REGRDY causes OpenOCD to fail handling
correctly the core registers on a Cortex-M4 emulated in a slow
FPGA, and it could also fail on devices clocked at very low speed
while using a fast adapter.
Poll S_REGRDY as specified in [1] while either reading or writing
the core registers.
A timeout of 0.5s is added. This could still be too small in some
extremely slow cases, but at least now we log the timeout event,
which can help tracking down such odd issue.
During register read include in the polling loop the read of DCRSR
and to flush the JTAG queue only once.
During register write, relax the write in DCRSR by removing the
atomicity that is now useless since followed by the atomic read to
S_REGRDY.
During register read include the read of DCRSR inside the polling
loop to relax the read of S_REGRDY since followed by the atomic
read to DCRSR.
This change has the drawback of adding other transfers to the
adapter while reading/writing the registers, so it is expected to
introduce some speed degradation during step-by-step.
[1] DDI0403E - "ARMv7-M Architecture Reference Manual"
Change-Id: I61f454248f11a3bec6dcf4c58a50c5c996d7ef81
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/5319
Tested-by: jenkins
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
DCB DHCSR register contains S_RETIRE_ST and S_RESET_ST bits cleared
on a read.
The change introduces a helper function cortex_m_cumulate_dhcsr_sticky().
Call this function each time DHCSR is read to preserve S_RESET_ST state
in the case of a reset event was detected.
Introduce cortex_m_read_dhcsr_atomic_sticky() convenience helper to
read DHCSR, store it to cortex_m->dcb_dhcsr and cumulate sticky bits.
The cumulated state of S_RESET_ST is read and cleared in cortex_m_poll()
Change-Id: Ib679599f850fd219fb9418c6ff32eed7cf5740da
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/6180
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
cortex_m->dcb_dhcsr caches status of DHCSR register.
Use it instead of local variable in cortex_m_soft_reset_halt()
like in other code.
Extracted from [1].
[1] Antonio Borneo: 6207: cortex_m: rework handling of dcb_dhcsr
Link: https://review.openocd.org/c/openocd/+/6207
Change-Id: I9a0aeba0b6b0b4969f05f4a32fc2fc8d244f56ca
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/6677
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
cortex_m_single_step_core() used mem_ap_write_atomic_u32() to manipulate
dhcsr bits unlike the rest of code, where a specialized function
cortex_m_write_debug_halt_mask() takes place.
Unify setting of dhcsr bits and use cortex_m_write_debug_halt_mask() here as well.
Extracted from [1].
[1] Antonio Borneo: 6207: cortex_m: rework handling of dcb_dhcsr
Link: https://review.openocd.org/c/openocd/+/6207
Change-Id: I9ef05ce88a9dce42e1d3d5404a4fe87ec86b5fe8
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/6676
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
After moved the code, align the include files.
Change-Id: I514a3020648816810d69f76c2ec4f6e52a1c57ab
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6643
Tested-by: jenkins
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
This functionality was lost in #567. Now it works as expected again.
Change-Id: I11a36e076867c0268034ceee763e28b2d4e6ff0f
Signed-off-by: Tim Newsome <tim@sifive.com>
This replaces a static array with 8 bytes per register. When there are
vector registers larger than 8 bytes, they would end up clobbering each
other's values. I can't believe I didn't catch this earlier.
Change-Id: I9df4eaf05617a2c8df3140fff9fe53f61ab2b261
Signed-off-by: Tim Newsome <tim@sifive.com>
This causes trouble if you disconnect/reconnect gdb, because in that
case a halt is issued again. (It probably would be possible to run into
this problem in other ways as well.)
Change-Id: Id5815f9d1dc2c2dd627770e001c03874a307c279
Signed-off-by: Tim Newsome <tim@sifive.com>
This makes things work as expected when OpenOCD disconnects and then
connects again. (This became a problem in #645, which started using the
cache.)
Change-Id: I764e5b410a1a68ca47d2ec39968085618ee363c2
Signed-off-by: Tim Newsome <tim@sifive.com>
This primarily contains the large upstreaming of RISC-V changes, so lots
more RISC-V changes than usual.
Conflicts:
src/target/riscv/opcodes.h
src/target/riscv/riscv-011.c
src/target/riscv/riscv-013.c
src/target/riscv/riscv.c
src/target/riscv/riscv.h
Change-Id: I1145dad538a5470ad209848572e6b0f560b671e9
Signed-off-by: Tim Newsome <tim@sifive.com>
Doxygen cannot resolve the path of the files in folder contrib.
Use a path relative to current folder, as done in other files.
Change-Id: If39b416ed422b4854dd108777fa32dd4c809450a
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6635
Tested-by: jenkins
Reviewed-by: Tim Newsome <tim@sifive.com>
There is no reason to add the 'src' prefix.
Remove it.
Change-Id: Id7d7ee8b3807fb90381cc1d6d545321020bc06c1
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6634
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Made no attempt to separate this out into reviewable chunks, since this
is all RISC-V-specific code developed at
https://github.com/riscv/riscv-openocd
Memory sample and repeat read functionality was left out of this change
since it requires some target-independent changes that I'll upstream
some other time.
Change-Id: I92917c86d549c232cbf36ffbfefc93331c05accd
Signed-off-by: Tim Newsome <tim@sifive.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6529
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Clang scan-build complains for three dead assignments:
Although the value stored to 'data' is used in the
enclosing expression, the value is never actually read
from 'data'
Value stored to 'address' is never read
Remove the useless assignment and the variable 'data'.
Change-Id: Ie8dcb74b1c1aa5eea1acd06b3c45c5b44954c9e7
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6592
Tested-by: jenkins
Clang scan-build complains for a dead assignment:
Value stored to 'tapstatus' is never read
Remove the assignment and add a comment to point for a potential
removal of the line.
Change-Id: Iad2fdc7e6faf650e24cc086ee74c745acb0d1c73
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6591
Tested-by: jenkins
Clang scan-build complains for five dead assignments:
Value stored to 'retval' is never read
Check the returned value and propagate the error.
Change-Id: I01172887a056d6f39ddcf2807848423970db1e89
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6590
Tested-by: jenkins
Clang scan-build complains for two dead assignments:
Value stored to 'r' is never read
Use the variable in the following line, instead of re-computing
the pointer.
Change-Id: I5d4069872be9da85fb28bbe0a82020b90f1efe46
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6589
Tested-by: jenkins
Clang scan-build complains for two dead assignments:
Value stored to 'retval' is never read
Since the timer callback should not return error, print an error
message if the data cannot be send out. Add a FIXME comment
because in current code there is no string/name to report which
connection has failed.
In command tpiu enable check the returned value and propagate the
error.
Change-Id: I9a89e4c4f7b677e8222b2df09a31b2478ac9ca4f
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6588
Tested-by: jenkins
* Properly handle held-in-reset targets.
1. Let OpenOCD continue into some pre-existing code that will periodically
call examine() until it passes.
2. Fix crash in riscv_openocd_poll()
When SMP is configured, it's not guaranteed that all targets have been
examine()d when poll is called on one of them.
Change-Id: Ic6c1d217dc766ea69b67bb2e9a4898e37ee94927
Signed-off-by: Tim Newsome <tim@sifive.com>
* Actually poll for examine at least every 5s.
That's what the comment says the code is trying to do.
Change-Id: I34ff909a98f8aebb3c514e0f3ee403be7699c094
Signed-off-by: Tim Newsome <tim@sifive.com>
* Compact this error message a bit.
Reduces clutter when some targets haven't been properly examined yet.
Change-Id: Id865f191f0fbb48abece8b8558cc9fa2041a26df
Signed-off-by: Tim Newsome <tim@sifive.com>
Broken by #645. It probably broke some other uses as well, but it was
reported (and easy to reproduce) as an issue with flashing.
Change-Id: Ic1b579c1361442479ced14156102ce68ab232396
Signed-off-by: Tim Newsome <tim@sifive.com>
The header files under src/helper/ can currently be included with
either
#include <bits.h>
or
#include <helper/bits.h>
This is because we specify both "src/" and "src/helper/" directories
as include directories. Some files name under "src/helper/", such as
types.h, log.h, and util.h are too generic and could be ambiguous
depending on the search path.
This commit remove "src/helper/" from our include dir and make C files
include explicitly.
Change-Id: I38fc9b96ba01a513d4a72757d40007e21b502f25
Signed-off-by: Yasushi SHOJI <yashi@spacecubics.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6507
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
For example: before this change in cortex_m_examine, if we fail reading CPUID
we return a failure code but target was set to examined which is not consistent.
Change-Id: I9f0ebe8f811849e54d1b350b0db506cb3fdd58f4
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6548
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Giving the example of STM32WL55x the examine log is the following:
Info : stm32wlx.cpu0: hardware has 6 breakpoints, 4 watchpoints
Info : stm32wlx.cpu1: hardware has 4 breakpoints, 2 watchpoints
After this change the examine log becomes:
Info : stm32wlx.cpu0: Cortex-M4 r0p1 processor detected
Info : stm32wlx.cpu0: target has 6 breakpoints, 4 watchpoints
Info : stm32wlx.cpu1: Cortex-M0+ r0p1 processor detected
Info : stm32wlx.cpu1: target has 4 breakpoints, 2 watchpoints
Change-Id: I1873a75eb76f0819342c441129427b38e984f0df
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6553
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
The jimtcl API Jim_GetCommand() sets an error message when the
command is not found and flag JIM_ERRMSG is set.
OpenOCD is checking if the command has already been registered,
thus 'command not found' is the desired case.
Pass flag JIM_NONE to prevent jimtcl from setting the error
message.
Change-Id: I3329c2f8722eda0cc9a5f9cbd888a37915b46107
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6562
Tested-by: jenkins
Commit dc7b32ea4a ("armv7m_trace: get rid of the old tpiu code")
is not handling correctly the old 'tpiu' command if it is run
during the config phase (before command 'init').
Move the call to the old event handler 'trace-config' in function
jim_arm_tpiu_swo_enable(), so it is correctly executed after
'init'.
Add the call to the old event handler 'trace-config' also during
jim_arm_tpiu_swo_disable(), to match the old behaviour.
Add more information while alerting that the event 'trace-config'
is deprecated.
Change-Id: If831d9159b4634c74e19c04099d041a6e2be3f2a
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Fixes: dc7b32ea4a ("armv7m_trace: get rid of the old tpiu code")
Reviewed-on: https://review.openocd.org/c/openocd/+/6561
Tested-by: jenkins
Reviewed-by: Karl Palsson <karlp@tweak.net.au>
The initial version of the table dap_part_nums contains only the
part number of the device and not the manufacturer ID.
This causes collisions between devices with same part number but
from different manufacturer.
The table has been extended to include the manufacturer JEDEC code
in commit 2f131d3c30 ("ARM ADIv5: CoreSight ROM decode part
number and designer id").
For two old/legacy table's entries reported without manufacturer
code it was defined a special ANY_ID manufacturer, meaning skip
the check for manufacturer!
The two legacy entries report the comment "from OMAP3 memmap", and
thanks to the associated string has been possible through Google
to identify a Master Report [1] about using OpenOCD with the OMAP3
in a BeagleBoard. The ROM table is printed with OpenOCD command
"dap info 1" at page 8 and reports the Peripheral ID required to
extract the manufacturer ID that, out of any surprise, belong to
Texas Instruments.
Set the two missing manufacturer ID to Texas Instruments JEDEC
code.
Remove the now redundant definition and use of ANY_ID.
While revisiting this old code, remove also the useless comment
"0x113: what?". It was introduced in commit ddade10d4a ("ARM
ADIv5: "dap info" gets more readable") and from the same dump in
[1] it's clearly another element in OMAP3. It is listed as entry
0x8 in the ROM table and there is no further info available.
OpenOCD will anyway list it as:
Designer is 0x017, Texas Instruments
Part is 0x113, Unrecognized
Another link https://elinux.org/BeagleBoardOpenOCD reports the
text "Part number 0x113: This is ????", which sounds familiar!
No public document from Texas Instruments reports what is this
device at address 0x54012000.
[1] Warren Clay Grant - University of Texas at Austin
"Implementation of an Open Source JTAG Debugging Development
Chain for the BeagleBoard ARM® Cortex A-8" - May 2012
Link: https://repositories.lib.utexas.edu/bitstream/handle/2152/ETD-UT-2012-05-5478/GRANT-MASTERS-REPORT.pdf
Change-Id: I7e007addbb5c6e90303e4e8c110c7d27810fbe9c
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6454
Tested-by: jenkins
Reviewed-by: Daniel Goehring <dgoehrin@os.amperecomputing.com>
Extract new part numbers from Arm Cortex-R52 Processor Technical
Reference Manual Revision r1p3 and add them to the array
dap_partnums.
Change-Id: I8020f36de587951af60422ef33d7e438dc7d9d53
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6451
Tested-by: jenkins
Reviewed-by: Daniel Goehring <dgoehrin@os.amperecomputing.com>
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Extract new part numbers from ARM CoreSight System-on-Chip SoC-600
Technical Reference Manual Revision r4p1 and add them to the array
dap_partnums.
Change-Id: I88d8aa3c084f6e832b75032e75bfb6d377a08360
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6450
Tested-by: jenkins
Reviewed-by: Daniel Goehring <dgoehrin@os.amperecomputing.com>
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
For readability, move in a separate function the decoding and the
display of devtype register.
The function will be reused with ADIv6.
Split from change https://review.openocd.org/6077/
Change-Id: I7a26a2c9759d5db5f9acfae5c169b90b3deb2f18
Signed-off-by: Kevin Burke <kevinb@os.amperecomputing.com>
Signed-off-by: Daniel Goehring <dgoehrin@os.amperecomputing.com>
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6448
Tested-by: jenkins
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
The complete AP type should include 'class' and 'manufacturer'.
Cleanup the definition of AP type from AP_REG_IDR register.
Include the check of 'class', together with manufacturer and type.
Add the new MEM-AP from ARM IHI0074C.
Change-Id: Ic8db7c040108ba237b54f73b1abe24b8b853699b
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6447
Tested-by: jenkins
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-by: Daniel Goehring <dgoehrin@os.amperecomputing.com>
Several magic numbers related to ARM CoreSight specification
IHI0029E are spread around OpenOCD code.
Define through macros the ARM CoreSight magic numbers and collect
them in a single include file.
Use the new macros wherever possible.
Change-Id: I9b0c1c651ce4ffbaf08d31791ef16e95983ee4cb
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6446
Tested-by: jenkins
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-by: Daniel Goehring <dgoehrin@os.amperecomputing.com>
The include file 'armv7m.h' includes 'arm_adi_v5.h' only to get
the definition of 'struct adiv5_ap', but doesn't need the struct
content.
Reducing the cross dependencies speeds-up the compile time during
code development by avoiding re-compiling file.
Relax the dependency by locally declaring 'struct adiv5_ap' in
'armv7m.h' and remove the include of 'arm_adi_v5.h'.
Fix the other files that have now lost the includes file that
'arm_adi_v5.h' depends from.
Change-Id: Ic0d40b17db6045fa43f348bda83eaf211a6b347d
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6468
Tested-by: jenkins
Reviewed-by: Daniel Goehring <dgoehrin@os.amperecomputing.com>
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
* WIP on register caching.
So we don't have to save/restore S0 all the time.
Change-Id: I9d83a24dbd92a325213f2b25eebc9ede9dca2868
* Seems to work for RV32.
Change-Id: Ide620faa5dfef4f39c3146e094787ea28d041327
* Use caching everywhere.
Change-Id: I0de249437589e1f49811f34c12726528c045c74f
* Getting closer...
Change-Id: I532455f1e416723b79eecc7d33ec6407ccb8e33c
* All spike tests pass again.
Running all tests now takes 2m54s compared to 3m0s. That's probably not
the thing to measure, since the goal is to improve interactive
performance, while the tests do all kinds of other stuff (like sleep,
and start spike, etc.).
Change-Id: Ic7d944454a64b2baf6e6028debb4a1ba896834d8
* Save s0/s1 during examine.
Change-Id: I4795180e3b04d01433a11d4a0ccb38c35074cc44
Signed-off-by: Tim Newsome <tim@sifive.com>
* Check flush registers result.
Change-Id: I8350c4198cb41881e1143816698aed677a312111
Signed-off-by: Tim Newsome <tim@sifive.com>
* Fix upstream style regression.
Change-Id: I4cc7034151ba62fa51aea77e44b0cad9b9b97876
Signed-off-by: Tim Newsome <tim@sifive.com>
NULL is defined as 'void *'.
There is no need to cast NULL while assigning it to a pointer.
Change-Id: Ibaf18e5d47329707ec9c1c184cd4bba2e8e702ff
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6540
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Tested-by: jenkins
The NULL pointers preceded by cast where not detected by the
scripting tools looking for NULL pointer comparison.
Remove them and, while there, further simplify the code and apply
the other coding style rules.
Change-Id: Ia7406122e07ef56ef311579ab0ee7ddb22c8e4b5
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6539
Tested-by: jenkins
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
This works well with gdb on RISC-V, since hardware breakpoints are
per-core and gdb thinks that targets are really processes on a machine.
Are there targets where this is a bad idea? Should the target definition
specify whether this behavior is desired or not?
Change-Id: Ia32be2707b04347fd8bf2ca6fbb2b0ceaad3704a
Signed-off-by: Tim Newsome <tim@sifive.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6528
Tested-by: jenkins
Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
As per Arm Debug Interface Architecture Specification (ADIv5.0 to
ADIv5.2), B3.3.1, the JTAG-DP as an IR length of 4 or 8 bits
depending on the ARM implementation. The current code
only support 4-bit and this patch extends the support to 8-bit IR.
Not tested back yet on a 4-bit target.
Change-Id: Ie4f875dc336caf014c6cfced57574b54d0970623
Signed-off-by: Antoine C. <acalando@free.fr>
Reviewed-on: https://review.openocd.org/c/openocd/+/6285
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Current implementation ignores the flag '-ap-num' provided to
command 'target create' and searches for the first AP of APB type.
If specified, use the ap number.
Change-Id: If1ac12345220d14a4a60515efe46dc2a2eac079a
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6413
Tested-by: jenkins
JEP106 encodes JEDEC-assigned manufacture code as:
a) a sequence of zero or more escape codes 0x7f;
b) an odd-parity bit of the next 7 bits;
c) 7 bits.
The same code is often represented as a single value composed by
the logical OR between:
- the number of escape codes in a), shifted left by 7 positions;
- the 7 bits in c).
This is the preferred packed representation used by this change.
Currently there are only two uses of JEP106 in openocd to get the
manufacturer name:
- to decode the JTAG IDCODE of each TAP, where the JEP106 code is
already packed as in the preferred representation above in bits
IDCODE[11:1];
- to decode the ARM CoreSight PIDR register, where the JEP106 code
is split in 3 parts:
= PIDR3[3:0], corresponding to bits [10:7] of the packed code;
= PIDR2[2:0], corresponding to bits [6:4] of the packed code;
= PIDR1[7:4], corresponding to bits [3:0] of the packed code.
Wrap the existing JEP106 decode function in a simpler API using
the packed code.
Simplify the callers by skipping the bit unpacking.
Change the manufacturer code in CoreSight table dap_partnums[] to
match the packed representation, by removing the always-one bit 7
erroneously taken from PIDR bit JEDEC and included in the former
table.
Change-Id: I63eb4da9e6801fab25e330f1f6b792d2fd619493
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6418
Tested-by: jenkins
Update the list of ARM coresight classes wrt to latest ARM
documentation.
Use c99 array designator to easily track changes in future.
Add a comment for the entry "OptimoDE DESS". It was added in 2009
by David Brownell, but Google cannot find any reference other than
this line in openocd code its associated commit. It should not be
an issue keeping it as is.
Change-Id: Ia3b646131ee68ca5263095c3a0aeaf75c004b324
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6431
Tested-by: jenkins
The command 'step' accepts an optional parameter 'address' to run
the step-by-step execution from an address different from current
program counter.
When OpenOCD sets the new program counter value in the register
cache, it doesn't flag it as dirty. The following call to function
armv7m_restore_context() does not propagate the new value of the
program counter to the target. This cause the target to continue
from the old program counter value, ignoring the user's request.
It is hard to notice the issue if the target is halted in an idle
loop! In fact the default mode to operate step-by-step is to set a
breakpoint to the following instruction and resume execution. In
the idle loop the CPU will pass through the breakpoint whatever
the resume address is. User will find the target halting at the
instruction following 'address' which is consistent with the
expected behaviour of command 'step address'.
To verify the issue on an STM32F4, use a dummy code in SRAM:
halt
mww 0x20000000 0xbf00bf00
mww 0x20000004 0xbf00bf00
mww 0x20000008 0xe7fcbf00
arm disassemble 0x20000000 6
0x20000000 bf00 nop
0x20000002 bf00 nop
0x20000004 bf00 nop
+--> 0x20000006 bf00 nop
| 0x20000008 bf00 nop
+-<- 0x2000000a e7fc b #0x20000006
resume 0x20000006
halt
step 0x20000000
the target doesn't halt because it is in the loop from 0x20000006
to 0x2000000a. The 'step 0x20000000' did not changed the program
counter so the temporary breakpoint at 0x20000002 is never hit.
Then:
halt
step 0x20000008
target halted ...
... pc: 0x2000000a
gives the feeling that only the instruction at 0x20000008 has been
executed, but actually the whole loop has been executed from the
place 'halt' stopped the execution till the breakpoint at the
instruction following 0x20000008.
Flag the program counter cached value as 'valid' and 'dirty' to
force armv7m_restore_context() to update the target's register.
Change-Id: I49bd8bb95b2f5429ec38ed016f2ad706618ae68a
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/6434
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Commit 11019a824d ("adi_v5: enforce check on AP number value")
introduces the macro DP_APSEL_MAX and use it in place of hardcoded
magic numbers for the upper limit of AP selection value.
Fix one more place where the macro should be used.
Change-Id: I6c57f72405c69bbb40924221309d95dfeb5f7540
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Fixes: 11019a824d ("adi_v5: enforce check on AP number value")
Reviewed-on: http://openocd.zylin.com/6415
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Tested-by: jenkins
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Commit ac22cdc573 ("target/adiv5: Large Physical Address
Extension") reads the register MEM_AP_REG_CFG and keeps it in a
new field of struct adiv5_ap. The test on LE bit (Large Extension)
is used to identify if mem_ap addresses are 32 or 64 bits.
But the register MEM_AP_REG_CFG is only read during mem_ap_init(),
that is called only when the AP is used as a target debug AP or if
a target mem_ap is attached to that AP.
The openocd commands '<dapname> baseaddr', '<dapname> info' and
'dap info' can be executed on AP that has not been associated yet
to a target, thus executed without any knowledge of MEM_AP_REG_CFG
value. The initialization to ADI_BAD_CFG causes openocd to always
use 32 bit mode on un-associated APs.
Verify if MEM_AP_REG_CFG has not been read and eventually read it.
In case of 32 bits mode AP, MEM_AP_REG_BASE64 is defined as 'RES0'
(reserved, but readable); the code can queue both the read of
MEM_AP_REG_CFG and MEM_AP_REG_BASE64, before knowing if the former
is required. This speeds-up the operation.
Rename ADI_BAD_CFG as MEM_AP_REG_CFG_INVALID.
Change-Id: If3bbd792b56a483022c37ccc2ce82b5ba5c36caa
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Fixes: ac22cdc573 ("target/adiv5: Large Physical Address Extension")
Reviewed-on: http://openocd.zylin.com/6412
Tested-by: jenkins
Reviewed-by: Daniel Goehring <dgoehrin@os.amperecomputing.com>
In both arm ADIv5 and ADIv6 documentation, for both Class 0x1 and
Class 0x9 ROM tables, the offset field from ROM tables is supposed
to be a signed value: "Negative values of OFFSET are permitted,
using two’s complement."
The commit ac22cdc573 ("target/adiv5: Large Physical Address
Extension") extends to 64 bits the addresses while managing the ROM
tables. The offset is read as unsigned and in the former 32 bits
implementation the wrap-around was hiding the need for converting
the offset to signed. The new implementation requires the proper
cast to the offset.
On a STM32F411, without this fix the ROM table dump is incorrectly
reporting addresses out of the 32 bit bus range:
MEM-AP BASE 0xe00ff003
Valid ROM table present
Component base address 0xe00ff000
Peripheral ID 0x00000a0411
Designer is 0x0a0, STMicroelectronics
Part is 0x411, Unrecognized
Component class is 0x1, ROM table
MEMTYPE system memory present on bus
ROMTABLE[0x0] = 0xfff0f003
Component base address 0x1e000e000
^^^^^^^^^^^
Cast the offset before adding it to the base address of the ROM
table.
Change-Id: I8d31fd2b3d657286cb96f8e22fb00842baa728f7
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Fixes: ac22cdc573 ("target/adiv5: Large Physical Address Extension")
Reviewed-on: http://openocd.zylin.com/6410
Tested-by: jenkins
Reviewed-by: Daniel Goehring <dgoehrin@os.amperecomputing.com>
Use the new helper to make the code more readable.
Change-Id: I11b2a79dbc6f93f6cfde382bcc00dd7ff710d908
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6375
Tested-by: jenkins
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
The existing implementation blocks in select() for a fixed amount of
time. This change tracks when the next event (likely poll()) wants to be
run, and uses a shorter timeout in select() if necessary.
Also track all these timeouts using milliseconds as returned by
timeval_ms() instead of `struct timeval` to simplify the code.
This feature is helpful if poll() wants to do something like sample PCs
or memory values for basically the entire time that otherwise OpenOCD
would be hung in select(). See
https://github.com/riscv/riscv-openocd/pull/541 for an example of that.
The RISC-V code using this change will be upstreamed some day, too.
Signed-off-by: Tim Newsome <tim@sifive.com>
Change-Id: I67104a7cf69ed07c8399c14aa55963fc5116a67d
Reviewed-on: http://openocd.zylin.com/6363
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Add identifiers of the Cortex-A76 ROM and debug unit.
Change-Id: Ieef0d990189d3c0502e8d530874dc9cbca4417d8
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Reviewed-on: http://openocd.zylin.com/6358
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
The Broadcom Brahma-B53 CPUs contains a number of custom ROM table
entries for its PMU, Debug unit, and a couple of ROM tables.
Change-Id: I1f21f07ed296579c374f24e781325789bf4ebf51
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Reviewed-on: http://openocd.zylin.com/6368
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
The new checkpatch can automatically fix the code, but this
feature is still error prone and not complete.
Patch generated automatically through the new checkpatch with
flags "--types CONSTANT_COMPARISON --fix-inplace".
Some Yoda condition is detected by checkpatch but not fixed; it
will be fixed manually in a following commit.
Change-Id: Ifaaa1159e63dbd1db6aa3c017125df9874fa9703
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6355
Tested-by: jenkins
For the remaining NULL comparisons, remove then manually.
While there, make more readable a loop, by moving the assigment
out of the loop condition.
Change-Id: I44193aaa95813156a3a79c16b80e1ad333dc1eaf
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6353
Tested-by: jenkins
Patch generated automatically through a modified checkpatch that
detects the patterns
if (NULL == symbol)
if (NULL != symbol)
and through flags "--types COMPARISON_TO_NULL --fix-inplace".
The unmodified checkpatch detects this pattern as Yoda condition,
but it's odd fixing it as Yoda condition and then again as NULL
comparison. This triggered the modification to the script.
Change-Id: I5fe984a85e9c4fc799f049211797aef891ebce18
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6352
Tested-by: jenkins
Patch generated automatically through the new checkpatch with
flags "--types COMPARISON_TO_NULL --fix-inplace".
This only fixes the comparisons
if (symbol == NULL)
if (symbol != NULL)
The case of NULL on the left side of the comparison is not tested.
Some automatic fix is incorrect and has been massaged by hands:
- if (*psig == NULL)
+ if (*!psig)
changed as
+ if (!*psig)
Change-Id: If4a1e2b4e547e223532e8e3d9da89bf9cb382ce6
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6351
Tested-by: jenkins
There are more than 1000 NULL comparisons to be aligned to the
coding style.
For recurrent NULL comparison it's preferable using trivial
scripts in order to minimize the review effort.
Patch generated automatically with the command:
sed -i PATTERN $(find src/ -type f)
where PATTERN is in the list:
's/(\([a-z][a-z0-9_]*\) == NULL)/(!\1)/g'
's/(\([a-z][a-z0-9_]*->[a-z][a-z0-9_]*\) == NULL)/(!\1)/g'
's/(\([a-z][a-z0-9_]*\.[a-z][a-z0-9_]*\) == NULL)/(!\1)/g'
's/(\([a-z][a-z0-9_]*\) != NULL)/(\1)/g'
's/(\([a-z][a-z0-9_]*->[a-z][a-z0-9_]*\) != NULL)/(\1)/g'
's/(\([a-z][a-z0-9_]*\.[a-z][a-z0-9_]*\) != NULL)/(\1)/g'
's/(NULL == \([a-z][a-z0-9_]*\))/(!\1)/g'
's/(NULL == \([a-z][a-z0-9_]*->[a-z][a-z0-9_]*\))/(!\1)/g'
's/(NULL == \([a-z][a-z0-9_]*\.[a-z][a-z0-9_]*\))/(!\1)/g'
's/(NULL != \([a-z][a-z0-9_]*\))/(\1)/g'
's/(NULL != \([a-z][a-z0-9_]*->[a-z][a-z0-9_]*\))/(\1)/g'
's/(NULL != \([a-z][a-z0-9_]*\.[a-z][a-z0-9_]*\))/(\1)/g'
Change-Id: Ida103e325d6d0600fb69c0b7a1557ee969db4417
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6350
Tested-by: jenkins
No major cross dependencies, mostly changes internal to each
file/function.
Change-Id: I7cc87458a341bae29a4f772b0af5d97b4bfc2da3
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6343
Tested-by: jenkins
Reviewed-by: Marc Schink <dev@zapb.de>
Expose them in the virtual priv register, and set them on mcontrol6
hardware triggers. I have no good way to test this right now, so it's
all untested. But this change doesn't break anything, at least.
Change-Id: I0343a6169a0b2b1f0cc0abf687c6bdc560d99b1b
Signed-off-by: Tim Newsome <tim@sifive.com>
Fix the remaining Yoda conditions, detected by checkpatch but not
fixed automatically.
While there, apply minor style changes.
Change-Id: I6e1978b89c4d56a20aceaeb2b52968eb6384432a
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6356
Tested-by: jenkins
Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
Reviewed-by: Xiang W <wxjstz@126.com>
There are ~900 Yoda conditions to be aligned to the coding style.
For recurrent Yoda conditions it's preferable using a trivial
script in order to minimize the review effort.
E.g. comparison of uppercase macro/enum with lowercase variable:
- ...(ERROR_OK == retval)...
+ ...(retval == ERROR_OK)...
Patch generated automatically with the command:
sed -i \
's/(\([A-Z][A-Z0-9_]*\) \([=!]=\) \([a-z][a-z0-9_]*\))/(\3 \2 \1)/g' \
$(find src/ -type f)
While there, remove the braces {} around a single statement block
to prevent warning from checkpatch.
Change-Id: If585b0a4b4578879c87b2dd74d9e0025e275ec6b
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6354
Tested-by: jenkins
Reviewed-by: Xiang W <wxjstz@126.com>
Convert to lowercase the name of arrays.
Convert to macro two uppercase const variables.
Change-Id: Ic6f5cad38722dfdf78d662ff4893e94482ab423d
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6348
Tested-by: jenkins
Reviewed-by: Marc Schink <dev@zapb.de>
Reviewed-by: Xiang W <wxjstz@126.com>
No major cross dependencies, mostly changes internal to each
file/function.
Change-Id: Iec58f7fe1d65f621ae0c841b5e25ef222885792b
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6341
Tested-by: jenkins
Reviewed-by: Marc Schink <dev@zapb.de>
Reviewed-by: Xiang W <wxjstz@126.com>
No major cross dependencies, mostly changes internal to each
file/function.
Change-Id: I1325560ef0350517d86d4927cb17ceaae81b75d2
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6340
Tested-by: jenkins
Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
Reviewed-by: Xiang W <wxjstz@126.com>
No major cross dependencies, mostly changes internal to each
file/function.
Change-Id: I3f0879f0f33c6badc36a0dc60229323978a7e280
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6338
Tested-by: jenkins
Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
Reviewed-by: Xiang W <wxjstz@126.com>
- Added support for reading and writing 64-bit data items
using TCL commands "mem2array" and "array2mem". Until now,
data items only up to 32 bits were supportd.
- Cleaned up functions target_array2mem() and
target_mem2array(), especially data types of variables
and variable declarations (scope).
Change-Id: Ia0ba427804f8fd8d7568f12714ab36984d6d5e24
Signed-off-by: Jan Matyas <matyas@codasip.com>
Reviewed-on: http://openocd.zylin.com/6286
Tested-by: jenkins
Reviewed-by: Marc Schink <dev@zapb.de>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Add 64-bit address support to the target mem2array and array2mem commands
Change-Id: Ibdcc076ca5581f4fd87e92318aab33907e22d6ce
Signed-off-by: Daniel Goehring <dgoehrin@os.amperecomputing.com>
Reviewed-on: http://openocd.zylin.com/6246
Tested-by: jenkins
Reviewed-by: Jan Matyas <matyas@codasip.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
This change fixes behavior of the SEMIHOSTING_SYS_CLOSE operation.
It ensures that OpenOCD's own stdin/stdout/stderr streams are never
closed, not even if the target requests it via semihosting.
Change-Id: Ia85af5963d1a3516284fd834f7197369a8fb268c
Signed-off-by: Jan Matyas <matyas@codasip.com>
Reviewed-on: http://openocd.zylin.com/6291
Tested-by: jenkins
Reviewed-by: Tim Newsome <tim@sifive.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Antonio Borneo
Tim Newsome
Amaury Pouly
Evgeniy Naydanov
Jan Matyas
Erhan Kurubas
Julien Massot
Parshintsev Anatoly
Mark Zhuang
François LEGAL
Tomas Vanek
panciyan
Ian Thompson
Peter Collingbourne
Hang Xu
Anatoly Parshintsev
Jan Matyas
Marian Buschsieweke
Boris-Chengbiao Zhou
Koudai Iwahori
Marcin Niestroj
Nima Palizban
Dolu1990
Evgeniy Naydanov
Xiang W
Daniel Goehring
Dmitry Ryzhov
iysheng
Ben Bender
Pavel Kirienko
Kevin Burke
Tarek BOCHKATI
wzgpeter
Florian Fainelli
fatalc
Marc Schink
Jan Matyas
Erhan Kurubas
Zoltán Dudás
Bohdan Tymkiv
Yasushi SHOJI
Andreas Fritiofson
root