target/riscv: RISCV_HALT_BREAKPOINT -> RISCV_HALT_EBREAK

Simple rename to make code slightly more clear.

Change-Id: I959f83164c55de064d902d4e5bcd49333cef5c91
Signed-off-by: Tim Newsome <tim@sifive.com>

src/target/riscv/riscv-013.c

@@ -4376,7 +4376,7 @@ static enum riscv_halt_reason riscv013_halt_reason(struct target *target)
 
 	switch (get_field(dcsr, CSR_DCSR_CAUSE)) {
 	case CSR_DCSR_CAUSE_EBREAK:
-		return RISCV_HALT_BREAKPOINT;
+		return RISCV_HALT_EBREAK;
 	case CSR_DCSR_CAUSE_TRIGGER:
 		/* We could get here before triggers are enumerated if a trigger was
 		 * already set when we connected. Force enumeration now, which has the

src/target/riscv/riscv.c

@@ -1283,7 +1283,7 @@ int set_debug_reason(struct target *target, enum riscv_halt_reason halt_reason)
 	RISCV_INFO(r);
 	r->trigger_hit = -1;
 	switch (halt_reason) {
-		case RISCV_HALT_BREAKPOINT:
+		case RISCV_HALT_EBREAK:
 			target->debug_reason = DBG_REASON_BREAKPOINT;
 			break;
 		case RISCV_HALT_TRIGGER:
@@ -2247,7 +2247,7 @@ static int riscv_poll_hart(struct target *target, enum riscv_next_action *next_a
 				if (set_debug_reason(target, halt_reason) != ERROR_OK)
 					return ERROR_FAIL;
 
-				if (halt_reason == RISCV_HALT_BREAKPOINT) {
+				if (halt_reason == RISCV_HALT_EBREAK) {
 					int retval;
 					/* Detect if this EBREAK is a semihosting request. If so, handle it. */
 					switch (riscv_semihosting(target, &retval)) {

src/target/riscv/riscv.h

@@ -50,7 +50,7 @@ enum riscv_mem_access_method {
 
 enum riscv_halt_reason {
 	RISCV_HALT_INTERRUPT,
-	RISCV_HALT_BREAKPOINT,
+	RISCV_HALT_EBREAK,
 	RISCV_HALT_SINGLESTEP,
 	RISCV_HALT_TRIGGER,
 	RISCV_HALT_UNKNOWN,