Fix: Prevent segfault in riscv_invalidate_register_cache for non-examined targets. (#692)
The segfault could be triggered if: - At least one target failed to get examined (therefore does not have the register cache set up yet), - and "reset" TCL command was issued, which internally tries to invalidate the register cache. Minor cleanup: "registers_initialized" member removed from riscv_info_t because it is not used anywhere. Change-Id: I6288c0d4343ef6a330fb2a6b49d388e7eafa32a2 Signed-off-by: Jan Matyas <matyas@codasip.com>
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@ -3519,7 +3519,6 @@ void riscv_info_init(struct target *target, riscv_info_t *r)
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{
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memset(r, 0, sizeof(*r));
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r->dtm_version = 1;
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r->registers_initialized = false;
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r->current_hartid = target->coreid;
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r->version_specific = NULL;
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@ -3664,7 +3663,10 @@ int riscv_set_current_hartid(struct target *target, int hartid)
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void riscv_invalidate_register_cache(struct target *target)
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{
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RISCV_INFO(r);
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/* Do not invalidate the register cache if it is not yet set up
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* (e.g. when the target failed to get examined). */
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if (!target->reg_cache)
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return;
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LOG_DEBUG("[%d]", target->coreid);
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register_cache_invalidate(target->reg_cache);
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@ -3672,8 +3674,6 @@ void riscv_invalidate_register_cache(struct target *target)
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struct reg *reg = &target->reg_cache->reg_list[i];
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reg->valid = false;
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}
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r->registers_initialized = true;
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}
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int riscv_current_hartid(const struct target *target)
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@ -131,9 +131,6 @@ typedef struct {
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/* The number of entries in the debug buffer. */
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int debug_buffer_size;
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/* This avoids invalidating the register cache too often. */
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bool registers_initialized;
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/* This hart contains an implicit ebreak at the end of the program buffer. */
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bool impebreak;
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