target/riscv: [NFC] rename variables named read/write
read/write is system function Change-Id: I75db4dd5a1c60e9cff8a58a863a887beffc37cab Signed-off-by: Mark Zhuang <mark.zhuang@spacemit.com>
This commit is contained in:
Mark Zhuang
parent
4cccda353c
commit
dfce1d2708
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@ -163,15 +163,6 @@ typedef enum slot {
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#define DRAM_CACHE_SIZE 16
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struct trigger {
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uint64_t address;
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uint32_t length;
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uint64_t mask;
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uint64_t value;
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bool read, write, execute;
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int unique_id;
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};
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struct memory_cache_line {
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uint32_t data;
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bool valid;
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@ -105,17 +105,6 @@ typedef enum slot {
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#define CMDERR_HALT_RESUME 4
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#define CMDERR_OTHER 7
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/*** Info about the core being debugged. ***/
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struct trigger {
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uint64_t address;
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uint32_t length;
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uint64_t mask;
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uint64_t value;
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bool read, write, execute;
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int unique_id;
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};
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#define HART_INDEX_MULTIPLE -1
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#define HART_INDEX_UNKNOWN -2
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@ -987,14 +976,14 @@ static uint32_t abstract_memory_size(unsigned width)
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* Creates a memory access abstract command.
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*/
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static uint32_t access_memory_command(struct target *target, bool virtual,
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unsigned width, bool postincrement, bool write)
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unsigned width, bool postincrement, bool is_write)
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{
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uint32_t command = set_field(0, AC_ACCESS_MEMORY_CMDTYPE, 2);
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command = set_field(command, AC_ACCESS_MEMORY_AAMVIRTUAL, virtual);
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command |= abstract_memory_size(width);
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command = set_field(command, AC_ACCESS_MEMORY_AAMPOSTINCREMENT,
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postincrement);
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command = set_field(command, AC_ACCESS_MEMORY_WRITE, write);
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command = set_field(command, AC_ACCESS_MEMORY_WRITE, is_write);
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return command;
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}
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@ -2279,15 +2268,15 @@ static int sample_memory_bus_v1(struct target *target,
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return ERROR_FAIL;
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}
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unsigned int read = 0;
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unsigned int read_count = 0;
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for (unsigned int n = 0; n < repeat; n++) {
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for (unsigned int i = 0; i < ARRAY_SIZE(config->bucket); i++) {
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if (config->bucket[i].enabled) {
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assert(i < RISCV_SAMPLE_BUF_TIMESTAMP_BEFORE);
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uint64_t value = 0;
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if (config->bucket[i].size_bytes > 4)
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value = ((uint64_t)riscv_batch_get_dmi_read_data(batch, read++)) << 32;
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value |= riscv_batch_get_dmi_read_data(batch, read++);
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value = ((uint64_t)riscv_batch_get_dmi_read_data(batch, read_count++)) << 32;
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value |= riscv_batch_get_dmi_read_data(batch, read_count++);
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buf->buf[buf->used] = i;
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buf_set_u64(buf->buf + buf->used + 1, 0, config->bucket[i].size_bytes * 8, value);
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@ -2571,26 +2560,26 @@ static int execute_fence(struct target *target)
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}
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static void log_memory_access128(target_addr_t address, uint64_t value_h,
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uint64_t value_l, bool read)
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uint64_t value_l, bool is_read)
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{
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if (debug_level < LOG_LVL_DEBUG)
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return;
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char fmt[80];
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sprintf(fmt, "M[0x%" TARGET_PRIxADDR "] %ss 0x%%016" PRIx64 "%%016" PRIx64,
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address, read ? "read" : "write");
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address, is_read ? "read" : "write");
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LOG_DEBUG(fmt, value_h, value_l);
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}
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static void log_memory_access(target_addr_t address, uint64_t value,
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unsigned size_bytes, bool read)
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unsigned size_bytes, bool is_read)
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{
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if (debug_level < LOG_LVL_DEBUG)
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return;
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char fmt[80];
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sprintf(fmt, "M[0x%" TARGET_PRIxADDR "] %ss 0x%%0%d" PRIx64,
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address, read ? "read" : "write", size_bytes * 2);
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address, is_read ? "read" : "write", size_bytes * 2);
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switch (size_bytes) {
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case 1:
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value &= 0xff;
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@ -2915,7 +2904,7 @@ static int read_memory_bus_v1(struct target *target, target_addr_t address,
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return ERROR_OK;
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}
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static void log_mem_access_result(struct target *target, bool success, int method, bool read)
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static void log_mem_access_result(struct target *target, bool success, int method, bool is_read)
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{
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RISCV_INFO(r);
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bool warn = false;
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@ -2924,7 +2913,7 @@ static void log_mem_access_result(struct target *target, bool success, int metho
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/* Compose the message */
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snprintf(msg, 60, "%s to %s memory via %s.",
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success ? "Succeeded" : "Failed",
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read ? "read" : "write",
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is_read ? "read" : "write",
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(method == RISCV_MEM_ACCESS_PROGBUF) ? "program buffer" :
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(method == RISCV_MEM_ACCESS_SYSBUS) ? "system bus" : "abstract access");
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@ -2951,37 +2940,37 @@ static void log_mem_access_result(struct target *target, bool success, int metho
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}
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static bool mem_should_skip_progbuf(struct target *target, target_addr_t address,
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uint32_t size, bool read, char **skip_reason)
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uint32_t size, bool is_read, char **skip_reason)
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{
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assert(skip_reason);
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if (!has_sufficient_progbuf(target, 3)) {
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LOG_DEBUG("Skipping mem %s via progbuf - insufficient progbuf size.",
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read ? "read" : "write");
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is_read ? "read" : "write");
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*skip_reason = "skipped (insufficient progbuf)";
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return true;
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}
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if (target->state != TARGET_HALTED) {
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LOG_DEBUG("Skipping mem %s via progbuf - target not halted.",
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read ? "read" : "write");
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is_read ? "read" : "write");
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*skip_reason = "skipped (target not halted)";
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return true;
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}
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if (riscv_xlen(target) < size * 8) {
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LOG_DEBUG("Skipping mem %s via progbuf - XLEN (%d) is too short for %d-bit memory access.",
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read ? "read" : "write", riscv_xlen(target), size * 8);
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is_read ? "read" : "write", riscv_xlen(target), size * 8);
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*skip_reason = "skipped (XLEN too short)";
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return true;
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}
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if (size > 8) {
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LOG_DEBUG("Skipping mem %s via progbuf - unsupported size.",
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read ? "read" : "write");
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is_read ? "read" : "write");
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*skip_reason = "skipped (unsupported size)";
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return true;
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}
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if ((sizeof(address) * 8 > riscv_xlen(target)) && (address >> riscv_xlen(target))) {
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LOG_DEBUG("Skipping mem %s via progbuf - progbuf only supports %u-bit address.",
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read ? "read" : "write", riscv_xlen(target));
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is_read ? "read" : "write", riscv_xlen(target));
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*skip_reason = "skipped (too large address)";
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return true;
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}
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@ -2990,25 +2979,25 @@ static bool mem_should_skip_progbuf(struct target *target, target_addr_t address
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}
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static bool mem_should_skip_sysbus(struct target *target, target_addr_t address,
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uint32_t size, uint32_t increment, bool read, char **skip_reason)
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uint32_t size, uint32_t increment, bool is_read, char **skip_reason)
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{
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assert(skip_reason);
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RISCV013_INFO(info);
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if (!sba_supports_access(target, size)) {
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LOG_DEBUG("Skipping mem %s via system bus - unsupported size.",
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read ? "read" : "write");
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is_read ? "read" : "write");
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*skip_reason = "skipped (unsupported size)";
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return true;
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}
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unsigned int sbasize = get_field(info->sbcs, DM_SBCS_SBASIZE);
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if ((sizeof(address) * 8 > sbasize) && (address >> sbasize)) {
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LOG_DEBUG("Skipping mem %s via system bus - sba only supports %u-bit address.",
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read ? "read" : "write", sbasize);
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is_read ? "read" : "write", sbasize);
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*skip_reason = "skipped (too large address)";
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return true;
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}
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if (read && increment != size && (get_field(info->sbcs, DM_SBCS_SBVERSION) == 0 || increment != 0)) {
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if (is_read && increment != size && (get_field(info->sbcs, DM_SBCS_SBVERSION) == 0 || increment != 0)) {
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LOG_DEBUG("Skipping mem read via system bus - "
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"sba reads only support size==increment or also size==0 for sba v1.");
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*skip_reason = "skipped (unsupported increment)";
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@ -3019,7 +3008,7 @@ static bool mem_should_skip_sysbus(struct target *target, target_addr_t address,
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}
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static bool mem_should_skip_abstract(struct target *target, target_addr_t address,
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uint32_t size, uint32_t increment, bool read, char **skip_reason)
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uint32_t size, uint32_t increment, bool is_read, char **skip_reason)
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{
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assert(skip_reason);
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@ -3027,17 +3016,17 @@ static bool mem_should_skip_abstract(struct target *target, target_addr_t addres
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/* TODO: Add 128b support if it's ever used. Involves modifying
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read/write_abstract_arg() to work on two 64b values. */
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LOG_DEBUG("Skipping mem %s via abstract access - unsupported size: %d bits",
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read ? "read" : "write", size * 8);
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is_read ? "read" : "write", size * 8);
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*skip_reason = "skipped (unsupported size)";
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return true;
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}
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if ((sizeof(address) * 8 > riscv_xlen(target)) && (address >> riscv_xlen(target))) {
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LOG_DEBUG("Skipping mem %s via abstract access - abstract access only supports %u-bit address.",
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read ? "read" : "write", riscv_xlen(target));
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is_read ? "read" : "write", riscv_xlen(target));
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*skip_reason = "skipped (too large address)";
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return true;
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}
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if (read && size != increment) {
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if (is_read && size != increment) {
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LOG_ERROR("Skipping mem read via abstract access - "
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"abstract command reads only support size==increment.");
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*skip_reason = "skipped (unsupported increment)";
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@ -3363,7 +3352,7 @@ static int read_memory_progbuf_inner(struct target *target, target_addr_t addres
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/* Now read whatever we got out of the batch. */
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dmi_status_t status = DMI_STATUS_SUCCESS;
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unsigned read = 0;
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unsigned read_count = 0;
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assert(index >= 2);
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for (unsigned j = index - 2; j < index + reads; j++) {
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assert(j < count);
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@ -3372,9 +3361,9 @@ static int read_memory_progbuf_inner(struct target *target, target_addr_t addres
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if (j + 3 + ignore_last > next_index)
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break;
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status = riscv_batch_get_dmi_read_op(batch, read);
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uint64_t value = riscv_batch_get_dmi_read_data(batch, read);
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read++;
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status = riscv_batch_get_dmi_read_op(batch, read_count);
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uint64_t value = riscv_batch_get_dmi_read_data(batch, read_count);
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read_count++;
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if (status != DMI_STATUS_SUCCESS) {
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/* If we're here because of busy count, dmi_busy_delay will
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* already have been increased and busy state will have been
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@ -3391,7 +3380,7 @@ static int read_memory_progbuf_inner(struct target *target, target_addr_t addres
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goto error;
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}
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if (size > 4) {
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status = riscv_batch_get_dmi_read_op(batch, read);
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status = riscv_batch_get_dmi_read_op(batch, read_count);
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if (status != DMI_STATUS_SUCCESS) {
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LOG_WARNING("Batch memory read encountered DMI error %d. "
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"Falling back on slower reads.", status);
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@ -3400,8 +3389,8 @@ static int read_memory_progbuf_inner(struct target *target, target_addr_t addres
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goto error;
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}
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value <<= 32;
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value |= riscv_batch_get_dmi_read_data(batch, read);
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read++;
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value |= riscv_batch_get_dmi_read_data(batch, read_count);
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read_count++;
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}
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riscv_addr_t offset = j * size;
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buf_set_u64(buffer + offset, 0, 8 * size, value);
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@ -124,7 +124,7 @@ struct trigger {
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uint32_t length;
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uint64_t mask;
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uint64_t value;
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bool read, write, execute;
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bool is_read, is_write, is_execute;
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int unique_id;
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};
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@ -462,9 +462,9 @@ static void trigger_from_breakpoint(struct trigger *trigger,
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trigger->address = breakpoint->address;
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trigger->length = breakpoint->length;
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trigger->mask = ~0LL;
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trigger->read = false;
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trigger->write = false;
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trigger->execute = true;
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trigger->is_read = false;
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trigger->is_write = false;
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trigger->is_execute = true;
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/* unique_id is unique across both breakpoints and watchpoints. */
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trigger->unique_id = breakpoint->unique_id;
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}
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@ -589,9 +589,9 @@ static int maybe_add_trigger_t1(struct target *target, struct trigger *trigger)
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}
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tdata1 = 0;
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tdata1 = set_field(tdata1, bpcontrol_r, trigger->read);
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tdata1 = set_field(tdata1, bpcontrol_w, trigger->write);
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tdata1 = set_field(tdata1, bpcontrol_x, trigger->execute);
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tdata1 = set_field(tdata1, bpcontrol_r, trigger->is_read);
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tdata1 = set_field(tdata1, bpcontrol_w, trigger->is_write);
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tdata1 = set_field(tdata1, bpcontrol_x, trigger->is_execute);
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tdata1 = set_field(tdata1, bpcontrol_u, !!(r->misa & BIT('U' - 'A')));
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tdata1 = set_field(tdata1, bpcontrol_s, !!(r->misa & BIT('S' - 'A')));
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tdata1 = set_field(tdata1, bpcontrol_h, !!(r->misa & BIT('H' - 'A')));
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@ -703,9 +703,9 @@ static struct match_triggers_tdata1_fields fill_match_triggers_tdata1_fields_t2(
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field_value(CSR_MCONTROL_M, 1) |
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field_value(CSR_MCONTROL_S, !!(r->misa & BIT('S' - 'A'))) |
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field_value(CSR_MCONTROL_U, !!(r->misa & BIT('U' - 'A'))) |
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field_value(CSR_MCONTROL_EXECUTE, trigger->execute) |
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field_value(CSR_MCONTROL_LOAD, trigger->read) |
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field_value(CSR_MCONTROL_STORE, trigger->write),
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field_value(CSR_MCONTROL_EXECUTE, trigger->is_execute) |
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field_value(CSR_MCONTROL_LOAD, trigger->is_read) |
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field_value(CSR_MCONTROL_STORE, trigger->is_write),
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.size = {
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.any =
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field_value(CSR_MCONTROL_SIZELO, CSR_MCONTROL_SIZELO_ANY & 3) |
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@ -742,9 +742,9 @@ static struct match_triggers_tdata1_fields fill_match_triggers_tdata1_fields_t6(
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field_value(CSR_MCONTROL6_M, 1) |
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field_value(CSR_MCONTROL6_S, !!(r->misa & BIT('S' - 'A'))) |
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field_value(CSR_MCONTROL6_U, !!(r->misa & BIT('U' - 'A'))) |
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field_value(CSR_MCONTROL6_EXECUTE, trigger->execute) |
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field_value(CSR_MCONTROL6_LOAD, trigger->read) |
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field_value(CSR_MCONTROL6_STORE, trigger->write),
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field_value(CSR_MCONTROL6_EXECUTE, trigger->is_execute) |
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field_value(CSR_MCONTROL6_LOAD, trigger->is_read) |
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field_value(CSR_MCONTROL6_STORE, trigger->is_write),
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.size = {
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.any = field_value(CSR_MCONTROL6_SIZE, CSR_MCONTROL6_SIZE_ANY),
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.s8bit = field_value(CSR_MCONTROL6_SIZE, CSR_MCONTROL6_SIZE_8BIT)
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@ -769,7 +769,7 @@ static int maybe_add_trigger_t2_t6(struct target *target,
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{
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int ret = ERROR_OK;
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if (!trigger->execute && trigger->length > 1) {
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if (!trigger->is_execute && trigger->length > 1) {
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/* Setting a load/store trigger ("watchpoint") on a range of addresses */
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if (can_use_napot_match(trigger)) {
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@ -1194,9 +1194,9 @@ static void trigger_from_watchpoint(struct trigger *trigger,
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trigger->length = watchpoint->length;
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trigger->mask = watchpoint->mask;
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trigger->value = watchpoint->value;
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trigger->read = (watchpoint->rw == WPT_READ || watchpoint->rw == WPT_ACCESS);
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trigger->write = (watchpoint->rw == WPT_WRITE || watchpoint->rw == WPT_ACCESS);
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trigger->execute = false;
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trigger->is_read = (watchpoint->rw == WPT_READ || watchpoint->rw == WPT_ACCESS);
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trigger->is_write = (watchpoint->rw == WPT_WRITE || watchpoint->rw == WPT_ACCESS);
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trigger->is_execute = false;
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/* unique_id is unique across both breakpoints and watchpoints. */
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trigger->unique_id = watchpoint->unique_id;
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}
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@ -2081,9 +2081,9 @@ const char *riscv_get_gdb_arch(struct target *target)
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static int riscv_get_gdb_reg_list_internal(struct target *target,
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struct reg **reg_list[], int *reg_list_size,
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enum target_register_class reg_class, bool read)
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enum target_register_class reg_class, bool is_read)
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{
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LOG_TARGET_DEBUG(target, "reg_class=%d, read=%d", reg_class, read);
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LOG_TARGET_DEBUG(target, "reg_class=%d, read=%d", reg_class, is_read);
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if (!target->reg_cache) {
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LOG_ERROR("Target not initialized. Return ERROR_FAIL.");
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@ -2110,7 +2110,7 @@ static int riscv_get_gdb_reg_list_internal(struct target *target,
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assert(!target->reg_cache->reg_list[i].valid ||
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target->reg_cache->reg_list[i].size > 0);
|
||||
(*reg_list)[i] = &target->reg_cache->reg_list[i];
|
||||
if (read &&
|
||||
if (is_read &&
|
||||
target->reg_cache->reg_list[i].exist &&
|
||||
!target->reg_cache->reg_list[i].valid) {
|
||||
if (target->reg_cache->reg_list[i].type->get(
|
||||
|
|
@ -4324,7 +4324,7 @@ unsigned int riscv_count_harts(struct target *target)
|
|||
* return true iff we are guaranteed that the register will read the same
|
||||
* value in the future as the value we just read.
|
||||
*/
|
||||
static bool gdb_regno_cacheable(enum gdb_regno regno, bool write)
|
||||
static bool gdb_regno_cacheable(enum gdb_regno regno, bool is_write)
|
||||
{
|
||||
/* GPRs, FPRs, vector registers are just normal data stores. */
|
||||
if (regno <= GDB_REGNO_XPR31 ||
|
||||
|
|
@ -4355,7 +4355,7 @@ static bool gdb_regno_cacheable(enum gdb_regno regno, bool write)
|
|||
* WARL registers might not contain the value we just wrote, but
|
||||
* these ones won't spontaneously change their value either. *
|
||||
*/
|
||||
return !write;
|
||||
return !is_write;
|
||||
|
||||
case GDB_REGNO_TSELECT: /* I think this should be above, but then it doesn't work. */
|
||||
case GDB_REGNO_TDATA1: /* Changes value when tselect is changed. */
|
||||
|
|
|
|||
Loading…
Reference in New Issue