arm_adi_v5: add support for display Class 0x9 ROM tables
ADI v5.1 and v6.0 permit the definition of CoreSight components (class 9 ROM entries). dap_rom_display() is refactored a bit such that we always end up with attempting to parse the ROM contents using the appropriate upper limit for class 1 and 9 ROM types. Change-Id: I4ba497b3807f1f11f06186eb6e61959ea3540c59 Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/6359 Tested-by: jenkins
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@ -928,8 +928,8 @@ static const struct {
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};
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#define DEVARCH_ID_MASK (ARM_CS_C9_DEVARCH_ARCHITECT_MASK | ARM_CS_C9_DEVARCH_ARCHID_MASK)
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#define DEVARCH_ROM_C_0X9 ARCH_ID(ARM_ID, 0x0AF7)
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__attribute__((unused))
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static const char *class0x9_devarch_description(uint32_t devarch)
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{
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if (!(devarch & ARM_CS_C9_DEVARCH_PRESENT))
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@ -1449,6 +1449,7 @@ static int dap_devtype_display(struct command_invocation *cmd, uint32_t devtype)
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static int dap_rom_display(struct command_invocation *cmd,
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struct adiv5_ap *ap, target_addr_t dbgbase, int depth)
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{
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unsigned int rom_num_entries;
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int retval;
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uint64_t pid;
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uint32_t cid;
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@ -1513,27 +1514,7 @@ static int dap_rom_display(struct command_invocation *cmd,
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else
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command_print(cmd, "\t\tMEMTYPE system memory not present: dedicated debug bus");
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/* Read ROM table entries from base address until we get 0x00000000 or reach the reserved area */
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for (uint16_t entry_offset = 0; entry_offset < 0xF00; entry_offset += 4) {
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uint32_t romentry;
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retval = mem_ap_read_atomic_u32(ap, base_addr | entry_offset, &romentry);
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if (retval != ERROR_OK)
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return retval;
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command_print(cmd, "\t%sROMTABLE[0x%x] = 0x%" PRIx32 "",
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tabs, entry_offset, romentry);
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if (romentry & ARM_CS_ROMENTRY_PRESENT) {
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/* Recurse. "romentry" is signed */
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retval = dap_rom_display(cmd, ap, base_addr + (int32_t)(romentry & ARM_CS_ROMENTRY_OFFSET_MASK),
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depth + 1);
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if (retval != ERROR_OK)
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return retval;
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} else if (romentry != 0) {
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command_print(cmd, "\t\tComponent not present");
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} else {
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command_print(cmd, "\t%s\tEnd of ROM table", tabs);
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break;
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}
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}
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rom_num_entries = 960;
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} else if (class == ARM_CS_CLASS_0X9_CS_COMPONENT) {
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uint32_t devtype;
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retval = mem_ap_read_atomic_u32(ap, base_addr + ARM_CS_C9_DEVTYPE, &devtype);
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@ -1545,6 +1526,50 @@ static int dap_rom_display(struct command_invocation *cmd,
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return retval;
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/* REVISIT also show ARM_CS_C9_DEVID */
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uint32_t devarch;
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retval = mem_ap_read_atomic_u32(ap, base_addr + ARM_CS_C9_DEVARCH, &devarch);
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if (retval != ERROR_OK)
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return retval;
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if ((devarch & ARM_CS_C9_DEVARCH_PRESENT) == 0)
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return ERROR_OK;
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unsigned int architect_id = (devarch & ARM_CS_C9_DEVARCH_ARCHITECT_MASK) >> ARM_CS_C9_DEVARCH_ARCHITECT_SHIFT;
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unsigned int revision = (devarch & ARM_CS_C9_DEVARCH_REVISION_MASK) >> ARM_CS_C9_DEVARCH_REVISION_SHIFT;
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command_print(cmd, "\t\tDev Arch is 0x%08" PRIx32 ", %s \"%s\" rev.%u", devarch,
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jep106_manufacturer(architect_id), class0x9_devarch_description(devarch),
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revision);
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/* quit if not ROM table */
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if ((devarch & DEVARCH_ID_MASK) != DEVARCH_ROM_C_0X9)
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return ERROR_OK;
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rom_num_entries = 512;
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} else {
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/* Class other than 0x1 and 0x9 */
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return ERROR_OK;
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}
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/* Read ROM table entries from base address until we get 0x00000000 or reach the reserved area */
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for (unsigned int entry_offset = 0; entry_offset < 4 * rom_num_entries; entry_offset += 4) {
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uint32_t romentry;
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retval = mem_ap_read_atomic_u32(ap, base_addr + entry_offset, &romentry);
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if (retval != ERROR_OK)
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return retval;
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command_print(cmd, "\t%sROMTABLE[0x%x] = 0x%08" PRIx32 "",
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tabs, entry_offset, romentry);
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if (romentry & ARM_CS_ROMENTRY_PRESENT) {
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/* Recurse. "romentry" is signed */
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retval = dap_rom_display(cmd, ap, base_addr + (int32_t)(romentry & ARM_CS_ROMENTRY_OFFSET_MASK),
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depth + 1);
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if (retval != ERROR_OK)
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return retval;
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} else if (romentry != 0) {
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command_print(cmd, "\t\tComponent not present");
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} else {
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command_print(cmd, "\t%s\tEnd of ROM table", tabs);
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break;
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}
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}
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return ERROR_OK;
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