target/mips: rename CamelCase symbols
No major cross dependencies, mostly changes internal to each file/function. Change-Id: Iec58f7fe1d65f621ae0c841b5e25ef222885792b Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/6341 Tested-by: jenkins Reviewed-by: Marc Schink <dev@zapb.de> Reviewed-by: Xiang W <wxjstz@126.com>
This commit is contained in:
Antonio Borneo
parent
12d6f6d804
commit
cbaccc5c3e
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@ -248,7 +248,7 @@ struct mips32_algorithm {
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/*MICRO MIPS INSTRUCTIONS, see doc MD00582 */
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#define POOL32A 0X00u
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#define POOL32AXf 0x3Cu
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#define POOL32AXF 0x3Cu
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#define POOL32B 0x08u
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#define POOL32I 0x10u
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#define MMIPS32_OP_ADDI 0x04u
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@ -300,24 +300,24 @@ struct mips32_algorithm {
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#define MMIPS32_CACHE(op, off, base) MIPS32_R_INST(POOL32B, op, base, MMIPS32_OP_CACHE << 1, 0, off)
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#define MMIPS32_J(tar) MIPS32_J_INST(MMIPS32_OP_J, ((0x07FFFFFFu & ((tar) >> 1))))
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#define MMIPS32_JR(reg) MIPS32_R_INST(POOL32A, 0, reg, 0, MMIPS32_OP_JALR, POOL32AXf)
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#define MMIPS32_JR(reg) MIPS32_R_INST(POOL32A, 0, reg, 0, MMIPS32_OP_JALR, POOL32AXF)
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#define MMIPS32_LB(reg, off, base) MIPS32_I_INST(MMIPS32_OP_LB, reg, base, off)
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#define MMIPS32_LBU(reg, off, base) MIPS32_I_INST(MMIPS32_OP_LBU, reg, base, off)
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#define MMIPS32_LHU(reg, off, base) MIPS32_I_INST(MMIPS32_OP_LHU, reg, base, off)
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#define MMIPS32_LUI(reg, val) MIPS32_I_INST(POOL32I, MMIPS32_OP_LUI, reg, val)
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#define MMIPS32_LW(reg, off, base) MIPS32_I_INST(MMIPS32_OP_LW, reg, base, off)
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#define MMIPS32_MFC0(gpr, cpr, sel) MIPS32_R_INST(POOL32A, gpr, cpr, sel, MMIPS32_OP_MFC0, POOL32AXf)
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#define MMIPS32_MFLO(reg) MIPS32_R_INST(POOL32A, 0, reg, 0, MMIPS32_OP_MFLO, POOL32AXf)
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#define MMIPS32_MFHI(reg) MIPS32_R_INST(POOL32A, 0, reg, 0, MMIPS32_OP_MFHI, POOL32AXf)
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#define MMIPS32_MTC0(gpr, cpr, sel) MIPS32_R_INST(POOL32A, gpr, cpr, sel, MMIPS32_OP_MTC0, POOL32AXf)
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#define MMIPS32_MTLO(reg) MIPS32_R_INST(POOL32A, 0, reg, 0, MMIPS32_OP_MTLO, POOL32AXf)
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#define MMIPS32_MTHI(reg) MIPS32_R_INST(POOL32A, 0, reg, 0, MMIPS32_OP_MTHI, POOL32AXf)
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#define MMIPS32_MFC0(gpr, cpr, sel) MIPS32_R_INST(POOL32A, gpr, cpr, sel, MMIPS32_OP_MFC0, POOL32AXF)
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#define MMIPS32_MFLO(reg) MIPS32_R_INST(POOL32A, 0, reg, 0, MMIPS32_OP_MFLO, POOL32AXF)
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#define MMIPS32_MFHI(reg) MIPS32_R_INST(POOL32A, 0, reg, 0, MMIPS32_OP_MFHI, POOL32AXF)
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#define MMIPS32_MTC0(gpr, cpr, sel) MIPS32_R_INST(POOL32A, gpr, cpr, sel, MMIPS32_OP_MTC0, POOL32AXF)
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#define MMIPS32_MTLO(reg) MIPS32_R_INST(POOL32A, 0, reg, 0, MMIPS32_OP_MTLO, POOL32AXF)
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#define MMIPS32_MTHI(reg) MIPS32_R_INST(POOL32A, 0, reg, 0, MMIPS32_OP_MTHI, POOL32AXF)
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#define MMIPS32_MOVN(dst, src, tar) MIPS32_R_INST(POOL32A, tar, src, dst, 0, MMIPS32_OP_MOVN)
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#define MMIPS32_NOP 0
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#define MMIPS32_ORI(tar, src, val) MIPS32_I_INST(MMIPS32_OP_ORI, tar, src, val)
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#define MMIPS32_RDHWR(tar, dst) MIPS32_R_INST(POOL32A, dst, tar, 0, MMIPS32_OP_RDHWR, POOL32AXf)
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#define MMIPS32_RDHWR(tar, dst) MIPS32_R_INST(POOL32A, dst, tar, 0, MMIPS32_OP_RDHWR, POOL32AXF)
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#define MMIPS32_SB(reg, off, base) MIPS32_I_INST(MMIPS32_OP_SB, reg, base, off)
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#define MMIPS32_SH(reg, off, base) MIPS32_I_INST(MMIPS32_OP_SH, reg, base, off)
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#define MMIPS32_SW(reg, off, base) MIPS32_I_INST(MMIPS32_OP_SW, reg, base, off)
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@ -327,7 +327,7 @@ struct mips32_algorithm {
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#define MMIPS32_SYNCI(off, base) MIPS32_I_INST(POOL32I, MMIPS32_OP_SYNCI, base, off)
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#define MMIPS32_SLL(dst, src, sa) MIPS32_R_INST(POOL32A, dst, src, sa, 0, MMIPS32_OP_SLL)
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#define MMIPS32_SLTI(tar, src, val) MIPS32_I_INST(MMIPS32_OP_SLTI, tar, src, val)
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#define MMIPS32_SYNC 0x00001A7Cu /* MIPS32_R_INST(POOL32A, 0, 0, 0, 0x1ADu, POOL32AXf) */
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#define MMIPS32_SYNC 0x00001A7Cu /* MIPS32_R_INST(POOL32A, 0, 0, 0, 0x1ADu, POOL32AXF) */
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#define MMIPS32_XOR(reg, val1, val2) MIPS32_R_INST(POOL32A, val1, val2, reg, 0, MMIPS32_OP_XOR)
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#define MMIPS32_XORI(tar, src, val) MIPS32_I_INST(MMIPS32_OP_XORI, tar, src, val)
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@ -336,8 +336,8 @@ struct mips32_algorithm {
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/* ejtag specific instructions */
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#define MMIPS32_DRET 0x0000E37Cu /* MIPS32_R_INST(POOL32A, 0, 0, 0, 0x38D, POOL32AXf) */
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#define MMIPS32_SDBBP 0x0000DB7Cu /* MIPS32_R_INST(POOL32A, 0, 0, 0, 0x1BD, POOL32AXf) */
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#define MMIPS32_DRET 0x0000E37Cu /* MIPS32_R_INST(POOL32A, 0, 0, 0, 0x38D, POOL32AXF) */
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#define MMIPS32_SDBBP 0x0000DB7Cu /* MIPS32_R_INST(POOL32A, 0, 0, 0, 0x1BD, POOL32AXF) */
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#define MMIPS16_SDBBP 0x46C0u /* POOL16C instr */
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/* instruction code with isa selection */
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@ -296,8 +296,8 @@ static void mips_ejtag_init_mmr(struct mips_ejtag *ejtag_info)
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ejtag_info->ejtag_dbm_offs = EJTAG_V20_DBM_OFFS;
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ejtag_info->ejtag_dbv_offs = EJTAG_V20_DBV_OFFS;
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ejtag_info->ejtag_iba_step_size = EJTAG_V20_IBAn_STEP;
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ejtag_info->ejtag_dba_step_size = EJTAG_V20_DBAn_STEP;
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ejtag_info->ejtag_iba_step_size = EJTAG_V20_IBAN_STEP;
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ejtag_info->ejtag_dba_step_size = EJTAG_V20_DBAN_STEP;
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} else {
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ejtag_info->ejtag_ibs_addr = EJTAG_V25_IBS;
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ejtag_info->ejtag_iba0_addr = EJTAG_V25_IBA0;
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@ -312,8 +312,8 @@ static void mips_ejtag_init_mmr(struct mips_ejtag *ejtag_info)
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ejtag_info->ejtag_dbc_offs = EJTAG_V25_DBC_OFFS;
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ejtag_info->ejtag_dbv_offs = EJTAG_V25_DBV_OFFS;
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ejtag_info->ejtag_iba_step_size = EJTAG_V25_IBAn_STEP;
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ejtag_info->ejtag_dba_step_size = EJTAG_V25_DBAn_STEP;
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ejtag_info->ejtag_iba_step_size = EJTAG_V25_IBAN_STEP;
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ejtag_info->ejtag_dba_step_size = EJTAG_V25_DBAN_STEP;
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}
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}
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@ -147,33 +147,33 @@
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#define EJTAG_V20_IBA0 0xFF300100
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#define EJTAG_V20_IBC_OFFS 0x4 /* IBC Offset */
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#define EJTAG_V20_IBM_OFFS 0x8
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#define EJTAG_V20_IBAn_STEP 0x10 /* Offset for next channel */
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#define EJTAG_V20_IBAN_STEP 0x10 /* Offset for next channel */
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#define EJTAG_V20_DBS 0xFF300008
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#define EJTAG_V20_DBA0 0xFF300200
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#define EJTAG_V20_DBC_OFFS 0x4
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#define EJTAG_V20_DBM_OFFS 0x8
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#define EJTAG_V20_DBV_OFFS 0xc
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#define EJTAG_V20_DBAn_STEP 0x10
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#define EJTAG_V20_DBAN_STEP 0x10
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#define EJTAG_V25_IBS 0xFF301000
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#define EJTAG_V25_IBA0 0xFF301100
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#define EJTAG_V25_IBM_OFFS 0x8
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#define EJTAG_V25_IBASID_OFFS 0x10
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#define EJTAG_V25_IBC_OFFS 0x18
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#define EJTAG_V25_IBAn_STEP 0x100
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#define EJTAG_V25_IBAN_STEP 0x100
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#define EJTAG_V25_DBS 0xFF302000
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#define EJTAG_V25_DBA0 0xFF302100
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#define EJTAG_V25_DBM_OFFS 0x8
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#define EJTAG_V25_DBASID_OFFS 0x10
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#define EJTAG_V25_DBC_OFFS 0x18
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#define EJTAG_V25_DBV_OFFS 0x20
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#define EJTAG_V25_DBAn_STEP 0x100
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#define EJTAG_V25_DBAN_STEP 0x100
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#define EJTAG_DBCn_NOSB (1 << 13)
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#define EJTAG_DBCn_NOLB (1 << 12)
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#define EJTAG_DBCn_BLM_MASK 0xff
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#define EJTAG_DBCn_BLM_SHIFT 4
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#define EJTAG_DBCn_BE (1 << 0)
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#define EJTAG_DBCN_NOSB (1 << 13)
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#define EJTAG_DBCN_NOLB (1 << 12)
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#define EJTAG_DBCN_BLM_MASK 0xff
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#define EJTAG_DBCN_BLM_SHIFT 4
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#define EJTAG_DBCN_BE (1 << 0)
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#define EJTAG_VERSION_20 0
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#define EJTAG_VERSION_25 1
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@ -880,8 +880,8 @@ static int mips_m4k_set_watchpoint(struct target *target,
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* and exclude both load and store accesses from watchpoint
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* condition evaluation
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*/
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int enable = EJTAG_DBCn_NOSB | EJTAG_DBCn_NOLB | EJTAG_DBCn_BE |
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(0xff << EJTAG_DBCn_BLM_SHIFT);
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int enable = EJTAG_DBCN_NOSB | EJTAG_DBCN_NOLB | EJTAG_DBCN_BE |
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(0xff << EJTAG_DBCN_BLM_SHIFT);
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if (watchpoint->set) {
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LOG_WARNING("watchpoint already set");
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@ -907,13 +907,13 @@ static int mips_m4k_set_watchpoint(struct target *target,
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switch (watchpoint->rw) {
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case WPT_READ:
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enable &= ~EJTAG_DBCn_NOLB;
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enable &= ~EJTAG_DBCN_NOLB;
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break;
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case WPT_WRITE:
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enable &= ~EJTAG_DBCn_NOSB;
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enable &= ~EJTAG_DBCN_NOSB;
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break;
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case WPT_ACCESS:
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enable &= ~(EJTAG_DBCn_NOLB | EJTAG_DBCn_NOSB);
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enable &= ~(EJTAG_DBCN_NOLB | EJTAG_DBCN_NOSB);
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break;
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default:
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LOG_ERROR("BUG: watchpoint->rw neither read, write nor access");
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@ -410,8 +410,8 @@ static int mips_mips64_set_watchpoint(struct target *target,
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* and exclude both load and store accesses from watchpoint
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* condition evaluation
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*/
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int enable = EJTAG_DBCn_NOSB | EJTAG_DBCn_NOLB | EJTAG_DBCn_BE
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| (0xff << EJTAG_DBCn_BLM_SHIFT);
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int enable = EJTAG_DBCN_NOSB | EJTAG_DBCN_NOLB | EJTAG_DBCN_BE
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| (0xff << EJTAG_DBCN_BLM_SHIFT);
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if (watchpoint->set) {
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LOG_WARNING("watchpoint already set");
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@ -438,13 +438,13 @@ static int mips_mips64_set_watchpoint(struct target *target,
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switch (watchpoint->rw) {
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case WPT_READ:
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enable &= ~EJTAG_DBCn_NOLB;
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enable &= ~EJTAG_DBCN_NOLB;
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break;
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case WPT_WRITE:
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enable &= ~EJTAG_DBCn_NOSB;
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enable &= ~EJTAG_DBCN_NOSB;
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break;
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case WPT_ACCESS:
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enable &= ~(EJTAG_DBCn_NOLB | EJTAG_DBCn_NOSB);
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enable &= ~(EJTAG_DBCN_NOLB | EJTAG_DBCN_NOSB);
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break;
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default:
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LOG_ERROR("BUG: watchpoint->rw neither read, write nor access");
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